ISO7420E, ISO7420FE ISO7421E, ISO7421FE www.ti.com SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 Low-Power Dual Channel Digital Isolators Check for Samples: ISO7420E, ISO7420FE, ISO7421E, ISO7421FE FEATURES APPLICATIONS • • • 1 2 • • • • • • • • Signaling Rate > 50 Mbps For Devices with Suffix F, Output is Low in Fail-Safe Mode Low Power Consumption: Typical ICC per Channel (3.3V Supplies): – ISO7420: 1.4 mA at 1 Mbps, 2.5 mA at 25 Mbps – ISO7421: 1.8 mA at 1 Mbps, 2.8 mA at 25 Mbps Low Propagation Delay: 7 ns (Typical) Low Pulse Skew: 200 ps (Typical) Wide TA Range Specified: –40°C to 125°C 50 KV/ms Transient Immunity, Typical Isolation Barrier Life: > 25 Years Operates from 3V to 5.5V Supply Levels Narrow Body SOIC-8 Package Opto-Coupler Replacement in: – Industrial FieldBus – ProfiBus – ModBus – DeviceNet™ Data Buses – Servo Control Interface – Motor Control – Power Supplies – Battery Packs SAFETY AND REGULATORY APPROVALS • • • • • 2.5 KVRMS for 1 minute per UL 1577 CSA Component Acceptance Notice 5A IEC 60747-5-2 (VDE 0884 Rev. 2) IEC 60950-1 and IEC 61010-1 End Equipment Standards All Approvals Pending DESCRIPTION ISO7420E, ISO7420FE, ISO7421E and ISO7421FE provide galvanic isolation up to 2.5 KVRMS for 1 minute per UL. These devices have two isolated channels. Each channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. The suffix F indicates low-output option in fail-safe condition (see Table 1). These devices have TTL input thresholds and operate from 3V to 5.5V supplies. All inputs are 5V tolerant when supplied from a 3.3V supply. 1 INA 2 INB 3 GND1 4 ISO7421 D Package (Top View) 8 VCC2 VCC1 1 7 OUTA OUTA 2 6 OUTB INB 3 5 GND2 GND1 4 Isolation VCC1 Isolation ISO7420 D Package (Top View) 8 VCC2 7 INA 6 OUTB 5 GND2 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DeviceNet is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated ISO7420E, ISO7420FE ISO7421E, ISO7421FE SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN DESCRIPTIONS PIN NAME I/O DESCRIPTION ISO7420x ISO7421x INA 2 7 I Input, channel A INB 3 3 I Input, channel B GND1 4 4 – Ground connection for VCC1 GND2 5 5 – Ground connection for VCC2 OUTA 7 2 O Output, channel A OUTB 6 6 O Output, channel B VCC1 1 1 – Power supply, VCC1 VCC2 8 8 – Power supply, VCC2 Table 1. FUNCTION TABLE (1) INPUT SIDE VCC OUTPUT SIDE VCC PU PU INPUT INA, INB ISO7420E / ISO7421E ISO7420FE / ISO7421FE H H H L L L Open (1) (2) (3) OUTPUT OUTA, OUTB PD PU X PU PD X H (2) L (3) H (2) L (3) Z Z PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.4 V); X = Irrelevant; H = High level; L = Low level; Z = High Impedance In fail-safe condition, output defaults to high level In fail-safe condition, output defaults to low level AVAILABLE OPTIONS PRODUCT RATED ISOLATION PACKAGE INPUT THRESHOLD RATED TA CHANNEL DIRECTION ISO7420E (1) MARKED AS SO7420 Same ISO7420FE 2.5 KVRMS ISO7421E D-8 (1) ~1.5 V TTL (CMOS compatible) I7420F –40°C to 125°C SO7421 Opposite ISO7421FE (1) (1) 2 I7421F ORDERING NUMBER ISO7420ED (rail) ISO7420EDR (reel) ISO7420FED (rail) ISO7420FEDR (reel) ISO7421ED (rail) ISO7421EDR (reel) ISO7421FED (rail) ISO7421FEDR (reel) Product Preview Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE ISO7420E, ISO7420FE ISO7421E, ISO7421FE www.ti.com SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 ABSOLUTE MAXIMUM RATINGS (1) VALUE VCC Supply voltage (2), VCC1, VCC2 –0.5 V to 6 V VI Voltage at IN, OUT –0.5 V to 6 V IO Output current ESD Electrostatic discharge ±15 mA Human-body model JEDEC Standard 22, Test Method A114-C.01 Field-induced charged-device model JEDEC Standard 22, Test Method C101 Machine model ANSI/ESDS5.2-1996 ±3 kV All pins ±1.5 kV ±200 V TJ(Max) Maximum junction temperature Tstg (1) 150°C Storage temperature -65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. (2) RECOMMENDED OPERATING CONDITIONS MIN VCC1, VCC2 Supply voltage 3.0 IOH High-level output current –4 IOL Low-level output current VIH High-level input voltage VIL Low-level input voltage tui Input pulse duration 1 / tui Signaling rate TJ (2) TA (1) (2) TYP MAX 5.5 2 VCC 0 0.8 20 –40 -40 mA V V ns 0 Ambient Temperature V mA 4 Junction temperature UNIT 25 50 (1) Mbps 136 °C 125 °C Under typical conditions, the device is capable of signaling rate > 150 Mbps. To maintain the recommended operating conditions for TJ, see the Package Thermal Characteristics table. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE 3 ISO7420E, ISO7420FE ISO7421E, ISO7421FE SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 = 5V ± 10%, TA = -40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage MIN TYP IOH = –4 mA; see Figure 1. TEST CONDITIONS VCCx (1)– 0.8 4.6 IOH = –20 mA; see Figure 1. VCCx (1)– 0.1 5 High-level input current IIL Low-level input current 0.2 0.4 IOL = 20 mA; see Figure 1. 0 0.1 CMTI Common-mode transient immunity 400 –10 VI = VCC or 0 V; see Figure 3. 25 V mV 10 INx at 0 V or VCC UNIT V IOL = 4 mA; see Figure 1. VI(HYS) Input threshold voltage hysteresis IIH MAX mA mA 50 kV/ms SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15pF 50 Mbps ICC2 0.4 0.8 3.4 5 0.6 1 4.5 6 1 1.5 6.2 8 1.7 2.5 9 12 2.3 3.6 2.3 3.6 2.9 4.2 2.9 4.2 3.9 5.3 3.9 5.3 5.5 7 5.5 7 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15pF 50 Mbps ICC2 (1) DC Input: VI = VCC or 0 V, AC Input: CL = 15pF mA VCCx is the supply voltage for the output channel that is being measured SWITCHING CHARACTERISTICS VCC1 and VCC2 = 5V ± 10%, TA = -40°C to 125°C PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(o) (2) Channel-to-channel output skew time tsk(pp) (3) Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (3) 4 MIN See Figure 1. TYP MAX 7 11 ns 0.2 3 ns 0.3 1 ns 3.7 ns Part-to-part skew time tr (1) (2) TEST CONDITIONS See Figure 1. See Figure 2. UNIT 1.8 ns 1.7 ns 6 ms Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE ISO7420E, ISO7420FE ISO7421E, ISO7421FE www.ti.com SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS VCC1 = 5V ± 10%, VCC2 = 3.3V ± 10%, TA = -40°C to 125°C PARAMETER TEST CONDITIONS MIN TYP VCC1 – 0.8 4.6 ISO7420x/7421x (3.3V side) VCC2 - 0.4 3 IOH = –20 mA; ISO7421x (5V side) see Figure 1, ISO7420x/7421x (3.3V side) VCC1 – 0.1 5 VCC2 – 0.1 3.3 IOH = –4 mA; see Figure 1. VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity ISO7421x (5V side) MAX V IOL = 4 mA; see Figure 1. 0.2 0.4 IOL = 20 mA; see Figure 1. 0 0.1 400 –10 VI = VCC or 0 V; see Figure 3. 25 V mV 10 INx at 0 V or VCC UNIT mA mA 50 kV/ms SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15pF 50 Mbps ICC2 0.4 0.8 2.6 3.7 0.6 1 3.3 4.3 1 1.5 4.4 5.6 1.7 2.5 6.2 7.5 2.3 3.6 1.8 2.8 2.9 4.2 2.2 3.2 3.9 5.3 2.8 3.9 5.5 7 3.8 5 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15pF 50 Mbps ICC2 mA SWITCHING CHARACTERISTICS VCC1 = 5V ± 10%, VCC2 = 3.3V ± 10%, TA = -40°C to 125°C PARAMETER tPLH, tPHL PWD (1) Propagation delay time MIN See Figure 1. TYP MAX UNIT 8 13.5 ns 3 ns tsk(o) (2) Channel-to-channel output skew time 1.5 ns tsk(pp) (3) Part-to-part skew time 5.4 ns tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) (2) (3) Pulse width distortion |tPHL – tPLH| TEST CONDITIONS 0.3 2 See Figure 1. See Figure 2. ns 2 ns 6 ms Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE 5 ISO7420E, ISO7420FE ISO7421E, ISO7421FE SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 = 3.3V ± 10%, VCC2 = 5V ± 10%, TA = -40°C to 125°C PARAMETER VOH TEST CONDITIONS MIN TYP IOH = –4 mA; see Figure 1. ISO7421x (3.3V side) VCC1 – 0.4 3 ISO7420x/7421x (5V side) VCC2 – 0.8 4.6 IOH = –20 mA; see Figure 1 ISO7421x (3.3V side) VCC1 – 0.1 3.3 ISO7420x/7421x (5V side) VCC2 – 0.1 High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CMTI Common-mode transient immunity MAX V 5 IOL = 4 mA; see Figure 1. 0.2 0.4 IOL = 20 mA; see Figure 1. 0 0.1 400 –10 VI = VCC or 0 V; see Figure 3. 25 V mV 10 INx at 0 V or VCC UNIT mA mA 50 kV/ms SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 0.2 DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15pF 5 0.4 0.6 4.5 6 0.6 0.9 6.2 8 1 1.3 9 12 1.8 2.8 2.3 3.6 2.2 3.2 2.9 4.2 2.8 3.9 3.9 5.3 3.8 5 5.5 7 50 Mbps ICC2 0.4 3.4 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 10 Mbps ICC2 Supply current for VCC2 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15pF 50 Mbps ICC2 mA SWITCHING CHARACTERISTICS VCC1 = 3.3V ± 10%, VCC2 = 5V ± 10%, TA = -40°C to 125°C PARAMETER tPLH, tPHL PWD (1) Propagation delay time Pulse width distortion |tPHL – tPLH| tsk(o) (2) Channel-to-channel output skew time tsk(pp) (3) Part-to-part skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) (2) (3) 6 TEST CONDITIONS MIN See Figure 1. TYP MAX 7.5 12 ns 0.7 3 ns 0.5 1.5 ns 4.6 ns 1.7 See Figure 1. See Figure 2. UNIT ns 1.6 ns 6 ms Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE ISO7420E, ISO7420FE ISO7421E, ISO7421FE www.ti.com SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS VCC1 and VCC2 = 3.3 V ± 10%, TA = -40°C to 125°C PARAMETER TEST CONDITIONS VOH High-level output voltage VOL Low-level output voltage MIN TYP IOH = –4 mA; see Figure 1. VCCx (1) – 0.4 3 IOH = –20 mA; see Figure 1. VCCx (1) – 0.1 3.3 High-level input current IIL Low-level input current 0.2 0.4 IOL = 20 mA; see Figure 1. 0 0.1 CMTI Common-mode transient immunity 400 –10 VI = VCC or 0 V; see Figure 3. 25 V mV 10 INx at 0 V or VCC UNIT V IOL = 4 mA; see Figure 1. VI(HYS) Input threshold voltage hysteresis IIH MAX mA mA 50 kV/ms SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V, AC Input: CL = 15pF 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15pF 50 Mbps ICC2 0.2 0.4 2.6 3.7 0.4 0.6 3.3 4.3 0.6 0.9 4.4 5.6 1 1.3 6.2 7.5 1.8 2.8 1.8 2.8 2.2 3.2 2.2 3.2 2.8 3.9 2.8 3.9 3.8 5 3.8 5 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC2 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15pF 50 Mbps ICC2 (1) DC Input: VI = VCC or 0 V, AC Input: CL = 15pF mA VCCx is the supply voltage for the output channel that is being measured SWITCHING CHARACTERISTICS VCC1 and VCC2 = 3.3 V ± 10%, TA = -40°C to 125°C PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(o) (2) Part-to-part skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (3) MIN See Figure 1. Channel-to-channel output skew time tsk(pp) (3) (1) (2) TEST CONDITIONS TYP MAX 8.5 14 ns 0.5 2 ns 2 ns 6.2 ns 0.4 2 See Figure 1. See Figure 2. UNIT ns 1.8 ns 6 ms Also known as pulse skew. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. tsk(pp) is the magnitude of the difference in propagation delay times between terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE 7 ISO7420E, ISO7420FE ISO7421E, ISO7421FE SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com Isolation Barrier PARAMETER MEASUREMENT INFORMATION IN Input Generator (1) 50 W VI VCC1 VI OUT 1.4 V 1.4 V 0V VO CL tPLH (2) tPHL 90% 10% VCC/2 VO VCC/2 VOH VOL tr tf S0412-01 (1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, a 50-Ω resistor is required to terminate the Input Generator signal. It is not needed in an actual application. (2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI VCC1 VCC1 (1) Isolation Barrier 0 V IN or VCC1 VI 2.7 V 0V tfs OUT VO VOH VO 50% VO 50% Fail-Safe HIGH (ISO742xE) VOL (1) CL VOH Fail-Safe LOW (ISO742xFE) VOL CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms S1 IN C = 0.1 mF ±1% Isolation Barrier VCC1 GND1 VCC2 C = 0.1 mF ±1% Pass-fail criteria – output must remain stable. OUT + VOH or VOL GND2 (1) – + VCM – (1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit 8 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE ISO7420E, ISO7420FE ISO7421E, ISO7421FE www.ti.com SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 DEVICE INFORMATION IEC INSULATION AND SAFETY-RELATED SPECIFICATIONS FOR THE D-8 PACKAGE over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4.8 mm L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4.3 mm CTI Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 >400 V Minimum internal gap (internal clearance) Distance through the insulation 0.014 mm RIO Isolation resistance, input to output (1) CIO Barrier capacitance, input to output (1) CI Input capacitance (2) (1) (2) >1012 Ω 11 Ω VIO = 0.4 sin (2pft), f = 1 MHz 1 pF VI = VCC/2 + 0.4 sin (2pft), f = 1 MHz, VCC = 5 V 1 pF VIO = 500 V, TA < 100°C VIO = 500 V, 100°C ≤ TA ≤ max >10 All pins on each side of the barrier tied together creating a two-terminal device. Measured from input pin to ground. NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. INSULATION CHARACTERISTICS (3) over recommended operating conditions (unless otherwise noted) PARAMETER VIORM TEST CONDITIONS Maximum working insulation voltage Input-to-output test voltage per IEC 60747-5-2 VPR VIOTM Transient overvoltage per IEC 60747-5-2 VISO Isolation voltage per UL RS Insulation resistance UNIT 560 VPEAK Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC 896 Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC 1050 After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 672 VTEST = VIOTM t = 60 sec (qualification) t= 1 sec (100% production) 4000 VTEST = VISO, t = 60 sec (qualification) 2500 VTEST = 1.2 x VISO, t = 1 sec (100% production) 3000 VIO = 500 V at TS >109 Pollution degree (3) SPECIFICATION VPEAK VPEAK VRMS Ω 2 Climatic Classification 40/125/21 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE 9 ISO7420E, ISO7420FE ISO7421E, ISO7421FE SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com Table 2. IEC 60664-1 RATINGS TABLE PARAMETER TEST CONDITIONS Basic isolation group SPECIFICATION Material group Installation classification II Rated mains voltage ≤ 150 Vrms I–IV Rated mains voltage ≤ 300 Vrms I–III Rated mains voltage ≤ 400 Vrms I–II REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program (1) File number: pending (40016131) File number: pending (220991) File number: pending (E181974) (1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577. LIFE EXPECTANCY vs WORKING VOLTAGE Life Expectancy – Years 100 VIORM at 560 V 28 Years 10 0 120 250 500 750 880 1000 VIORM – Working Voltage – V G001 Figure 4. Life Expectancy vs Working Voltage IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current TS Maximum case temperature MIN TYP MAX qJA = 212°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 107 qJA = 212°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 164 150 UNIT mA °C The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 10 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE ISO7420E, ISO7420FE ISO7421E, ISO7421FE www.ti.com SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 PACKAGE THERMAL CHARACTERISTICS (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS Junction-to-air thermal resistance qJB Junction-to-board thermal resistance qJC Junction-to-case thermal resistance PD (1) 212 122 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 100-Mbps 50% duty-cycle square wave Device power dissipation TYP High-K thermal resistance (1) Low-K thermal resistance qJA MIN (1) MAX UNIT °C/W 37 °C/W 69.1 °C/W 138 mW Tested in accordance with the low-K or high-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages Safety Limiting Current − mA 180 160 VCC1, VCC2 at 3.6 V 140 120 100 VCC1, VCC2 at 5.5 V 80 60 40 20 0 0 50 100 150 200 Case Temperature − °C Figure 5. qJC Thermal Derating Curve per IEC 60747-5-2 VCC1 0.1mF OUTPUT INPUT GND1 VCC2 2 mm 2 mm max. max. ISO7421 from from VCC1 VCC2 8 1 OUTA INA 7 2 INB OUTB 6 3 5 4 0.1mF INPUT OUTPUT GND2 S0417-01 Figure 6. Typical ISO742x Application Circuit Note: For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE 11 ISO7420E, ISO7420FE ISO7421E, ISO7421FE SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com ISO0742xE Input VCC1 VCC1 VCC1 1 MW 500 W Output VCC2 IN 8W OUT 13 W ISO0742xFE Input VCC1 VCC1 500 W IN 1 MW Figure 7. Device I/O Schematics 12 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE ISO7420E, ISO7420FE ISO7421E, ISO7421FE www.ti.com SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS ISO7420 SUPPLY CURRENT PER CHANNEL vs DATA RATE (NO LOAD) ISO7420 SUPPLY CURRENT ALL CHANNELS vs DATA RATE (NO LOAD) 12 6 TA = 25oC No Load o TA = 25 C No Load ICC2 at 5 V 10 Supply Current - mA Supply Current - mA 5 4 ICC2 at 3.3 V 3 2 ICC1 at 5 V ICC2 at 5 V 8 ICC2 at 3.3 V 6 4 ICC1 at 5 V 2 1 ICC1 at 3.3 V ICC1 at 3.3 V 0 0 0 20 40 60 80 100 0 120 20 40 80 120 Figure 9. ISO7420x ISO7420 SUPPLY CURRENT PER CHANNEL vs DATA RATE (15 pF LOAD) ISO7420 SUPPLY CURRENT ALL CHANNELS vs DATA RATE (15 pF LOAD) 16 o o TA = 25 C CL = 15 pF Load 7 TA = 25 C CL = 15 pF Load 14 ICC2 at 5 V ICC2 at 5 V 12 Supply Current - mA 6 ICC2 at 3.3 V 5 4 3 10 ICC2 at 3.3 V 8 6 4 ICC1 at 5 V 2 ICC1 at 5 V 2 1 ICC1 at 3.3 V ICC1 at 3.3 V 0 100 Figure 8. ISO7420x 8 Supply Current - mA 60 Data Rate - Mbps Data Rate - Mbps 0 0 20 40 60 80 100 120 0 20 40 60 Data Rate - Mbps Data Rate - Mbps Figure 10. Figure 11. Copyright © 2010–2011, Texas Instruments Incorporated 80 100 Submit Documentation Feedback Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE 120 13 ISO7420E, ISO7420FE ISO7421E, ISO7421FE SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 10.5 VCC1 = VCC2 = 5 V, CL = 15 pF tpd - Propagation Delay Time - ns tpd - Propagation Delay Time - ns 8 7.5 tPLH 7 tPHL 6.5 6 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - °C 125 150 10 VCC1 = VCC2 = 3.3 V, CL = 15 pF tPLH 9.5 9 8.5 tPHL 8 7.5 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - °C Figure 12. Figure 13. INPUT VCC FAIL-SAFE VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEl OUTPUT CURRENT 2.7 125 150 6 TA = 25°C Fail-Safe Voltage Threshold - V VOH - High-Level Output Voltage - V FS+ 2.65 2.6 2.55 2.5 FS2.45 2.4 -50 -25 0 25 50 75 100 TA - Free-Air Temperature - °C Figure 14. 14 Submit Documentation Feedback 125 150 5 4 Output VCC = 5 V 3 2 Output VCC = 3.3 V 1 0 -80 -70 -60 -50 -40 -30 -20 IOH - High-Level Output Current - mA -10 0 Figure 15. Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE ISO7420E, ISO7420FE ISO7421E, ISO7421FE www.ti.com SLLSE45B – DECEMBER 2010 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEl OUTPUT CURRENT 6 VOL - Low-Level Output Voltage - V TA = 25°C 5 4 3 Output VCC = 3.3 V 2 Output VCC = 5 V 1 0 0 10 20 30 40 50 60 70 IOL - Low-Level Output Current - mA Figure 16. TA = 25°C, VCC1 = VCC2 = 3.3 V, TA = 25°C, VCC1 = VCC2 = 3.3 V, Pattern: PRBS 27-1 Pattern: PRBS 27-1 Figure 17. Typical Eye Diagram at 50 MBPS, 3.3 V Operation Figure 18. Typical Eye Diagram at 100 MBPS, 3.3 V Operation Spacer REVISION HISTORY Changes from Original (December 2010) to Revision A • Page Changed the Max values for Supply current for VCC1 and VCC2, CL = 15pF ......................................................................... 7 Changes from Revision A (December 2010) to Revision B Page • Changed Feature bullet From: ISO7421: TBDmA at 1Mbps, TBDmA at 25Mbps To: ISO7421: 1.8mA at 1Mbps, 2.8mA at 25Mbps .................................................................................................................................................................. 1 • Updated the ISO7421x Supply Current values for VCC1 and VCC2 = 5V ............................................................................... 4 • Updated the ISO7421x Supply Current values for VCC1 = 5V and VCC2 = 3.3V ................................................................... 5 • Updated the ISO7421x Supply Current values for VCC1 = 3.3V and VCC2 = 5V ................................................................... 6 • Updated the ISO7421x Supply Current values for VCC1 and VCC2 = 3.3V ............................................................................ 7 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7420E, ISO7420FE ISO7421E, ISO7421FE 15 PACKAGE OPTION ADDENDUM www.ti.com 5-Jan-2011 PACKAGING INFORMATION Orderable Device ISO7420FED Status (1) ACTIVE Package Type Package Drawing SOIC D Pins Package Qty 8 75 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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