NCP334, NCP335 2A Ultra-Small Controlled Load Switch with Auto-Discharge Path The NCP334 and NCP335 are low Ron MOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, due to a current consumption optimization with PMOS structure, leakage currents are eliminated by isolating connected IC’s on the battery when not used. Output discharge path is also embedded to eliminate residual voltages on the output rail in the NCP335. Proposed in wide input voltage range from 1.2 V to 5.5 V, and a very small 0.96 x 0.96 mm WLCSP4, 0.5 mm pitch. http://onsemi.com MARKING DIAGRAM 1 XX WLCSP4 CASE 567FG Features • • • • • • • • • 1.2 V – 5.5 V Operating Range 47 mW P MOSFET at 3.3 V DC Current Up to 2 A Output Auto−discharge (NCP335) Active high EN pin WLCSP4 0.96 x 0.96 mm ESD Ratings: 4 kV Human Body Model, 2 kV CDM, 250 V Machine Model These are Pb−Free Devices XX A WL YY WW G PIN DIAGRAM Typical Applications • • • • • = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Mobile Phones Tablets Digital Cameras GPS Portable Devices 1 2 A OUT IN B GND EN (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2012 August, 2012 − Rev. 1 1 Publication Order Number: NCP334/D NCP334, NCP335 U5 EN GND EN AVIN SW 2 1 2 NCP63xy/WDFN8 B1 FB NCP335 5 MODE/PG 3 EN EN 4 6 PGND OUT 7 1 B2 IN A1 AGND A2 B+ PVIN 8 VOUT Figure 1. Typical Application Circuit PIN FUNCTION DESCRIPTION Pin Name Pin Number Type Description IN A2 POWER Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as close as possible to the IC. GND B1 POWER Ground connection. EN B2 INPUT OUT A1 OUTPUT Enable input, logic high turns on power switch. Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as possible to the IC is recommended. BLOCK DIAGRAM IN: Pin A2 OUT: Pin A1 Gate driver and soft start control Control logic EN: Pin B2 Optional: NCP335 EN block GND: Pin B1 Figure 2. Block Diagram http://onsemi.com 2 NCP334, NCP335 MAXIMUM RATINGS Rating Symbol Value Unit VEN , VIN, VOUT 0.3 to + 7.0 V VIN, VOUT 0 to + 7.0 V TJ −40 to + 125 °C TSTG −40 to + 150 °C Human Body Model (HBM) ESD Rating are (Notes 1 and 2) ESD HBM 4000 V Machine Model (MM) ESD Rating are (Notes 1 and 2) ESD MM 250 V ESD CDM 2000 V IN, OUT, EN, Pins From IN to OUT Pins: Input/Output Maximum Junction Temperature Storage Temperature Range Charge Device Model (CDM) ESD Rating are (Notes 1 and 2) Latch−up protection (Note 3) − Pins IN, OUT, EN LU Moisture Sensitivity (Note 4) mA 100 MSL Level 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. According to JEDEC standard JESD22−A108. 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±4.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins. Charge Device Model (CDM) ±2.0 kV per JEDEC standard: JESD22−C101 for all pins. 3. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II. 4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. OPERATING CONDITIONS Symbol Parameter VIN Operational Power Supply VEN Enable Voltage TA Ambient Temperature Range CIN Decoupling input capacitor COUT Decoupling output capacitor RqJA Thermal Resistance Junction to Air IOUT Maximum DC current PD Conditions Min Max Unit 1.2 5.5 V 0 5.5 −40 Typ 25 + 85 1 mF 1 WLCSP package (Note 5) mF 100 °C/W 2 Power Dissipation Rating (Note 6) A TA ≤ 25 °C WLCSP package 0.5 W TA = 85°C WLCSP package 0.2 W 5. The RqJA is dependent of the PCB heat dissipation and thermal via. 6. The maximum power dissipation (PD) is given by the following formula: PD + http://onsemi.com 3 °C T JMAX * T A R qJA NCP334, NCP335 ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C for VIN between 1.2 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25 °C and VIN = 4 V (Unless otherwise noted). Parameter Symbol Conditions Min Typ Max Unit mW POWER SWITCH Static drain−source on−state resistance RDS(on) VIN = 5.5 V TA = 25°C, I = 200 mA (Note 8) 38 40 VIN = 4.2 V TA = 25°C, I = 200 mA 42 46 VIN = 3.3 V TA = 25°C, I = 200 mA 47 52 VIN = 1.8 V TA = 25°C, I = 200 mA 76 87 Full RDIS Output discharge path 100 VIN = 1.2 V TA = 25°C, I = 200 mA 211 420 EN = low VIN = 3.3 V, NCP335 only 65 110 W TR Output rise time VIN = 3.6 V CLOAD = 1 mF, RLOAD = 25 W (Note 7) 71 ms TF Output fall time VIN = 3.6 V CLOAD = 1 mF, RLOAD = 25 W (Note 7) 42 ms Ton Gate turn on VIN = 3.6 V Gate turn on + Output rise time 116 ms Ten Enable time VIN = 3.6 V From EN low to high to VOUT = 10% of fully on 45 ms VIH High−level input voltage VIL Low−level input voltage REN Pull down resistor 0.9 V 0.5 5 V MW QUIESCENT CURRENT IQ Current consumption VIN = 3.3 V, EN = low, No load 1 mA VIN = 3.3 V, EN= high, No load 1 mA 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground 8. Guaranteed by design and characterization, not production tested. TIMINGS Vin EN Vout TEN TDIS TR TOFF TON Figure 3. Enable, Rise and fall time http://onsemi.com 4 TF NCP334, NCP335 TYPICAL CHARACTERISTICS 60 300 −40°C −25°C 0°C 25°C 50°C 85°C 200 55 RDS(on) (mW) RDS(on) (mW) 250 150 100 50 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 −50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 40 30 0 500 1000 1500 2000 2500 VIN (V) IOUT (mA) Figure 4. RDS(on) (mW) vs. Vin (V) Figure 5. RDS(on) (mW) vs. Iload (mA) at 3.6 V 65 VIN = 5.5 V 60 VIN = 4.2 V 55 RDS(on) (mW) RDS(on) (mW) 45 35 0 1.0 VIN = 3.6 V VIN = 3.3 V 50 45 40 35 30 −25 0 25 50 75 100 125 25 −50 −25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) Figure 6. RDS(on) (mW) vs. Temperature (5C) at 3.3 V, Iload 100 mA Figure 7. RDS(on) (mW) vs. Temperature (5C), Iload 2 A 1.8 100 1.8 Temperature = −40°C 1.6 1.2 1.2 IIN (mA) 0.8 0.6 1.0 0.8 0.6 0.4 0.4 0.2 0.2 0 0 −25 0 25 Temperature = 25°C Temperature = 85°C Temperature = 125°C 1.4 1.0 −0.2 −50 Temperature = −40°C 1.6 Temperature = 25°C Temperature = 85°C Temperature = 125°C 1.4 IIN (mA) 50 50 75 100 125 −0.2 0 1 2 3 4 5 VIN (V) VIN (V) Figure 8. Standby Current (mA) versus VIN (V), No Load Figure 9. Standby Current (mA) versus VIN (V), Vout Short to GND. http://onsemi.com 5 6 NCP334, NCP335 1.8 Temperature = −40°C 1.6 Temperature = 25°C Temperature = 85°C Temperature = 125°C 1.4 IIN (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0 −0.2 0 1 2 3 VIN (V) 4 5 6 Figure 10. Quiescent Current (mA) versus VIN (V), No load. Figure 11. Enable Time, Rise Time, and Ton Time http://onsemi.com 6 NCP334, NCP335 Figure 12. Disable Time, Fall Time and Toff Time FUNCTIONAL DESCRIPTION Overview The auto−discharge is activated when EN pin is set to low level (disable state). The discharge path ( Pull down NMOS) stays activated as long as EN pin is set at low level and VIN > 1.2 V. In order to limit the current across the internal discharge N−MOSFET, the typical value is set at 65 W. The NCP334 – NCP335 are high side P channel MOSFET power distribution switch designed to isolate ICs connected on the battery in order to save energy. The part can be turned on, with a range of battery from 1.2 V to 5.5 V. Enable Input Enable pin is an active high. The path is opened when EN pin is tied low (disable), forcing P MOS switch off. The IN/OUT path is activated with a minimum of Vin of 1.2V and EN forced to high level. Cin and Cout Capacitors IN and OUT, 1 mF, at least, capacitors must be placed as close as possible the part for stability improvement. Auto Discharge (NCP335 Only) NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. http://onsemi.com 7 NCP334, NCP335 APPLICATION INFORMATION Power Dissipation TJ RqJA TA Main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: PD = RDS(on) x (IOUT)2 PD = Power dissipation (W) = Power MOSFET on resistance (W) RDS(on) IOUT = Output current (A) TJ = PD x RqJA + TA = Junction temperature (°C = Package thermal resistance (°C/W) = Ambient temperature (°C) PCB Recommendations The NCP334 – NCP335 integrate an up to 2 A rated PMOS FET, and the PCB design rules must be respected to properly evacuate the heat out of the silicon. By increasing PCB area, especially around IN and OUT pins, the RqJA of the package can be decreased, allowing higher power dissipation. Figure 13. Routing Example 1 oz, 2 Layers, 1005C/W http://onsemi.com 8 NCP334, NCP335 Figure 14. Routing Example 2 oz, 4 Layers, 605C/W Example of application definition. T J * T A + R qJA Pd + R qJA R DS(on) At 2 A, 25°C ambient temperature, RDS(on) 42 mW @ VIN 4.2 V, the junction temperature will be: I2 TJ + TA ) Rq TJ: Junction Temperature. TA: Ambient Temperature. Rq = Thermal resistance between IC and air, through PCB. RDS(on): Intrinsic resistance of the IC MOSFET. I: load DC current. Taking into account of Rtheta obtain with: 1 oz, 2 layers: 100°C/W. Pd + 25 ) ǒ0.042 2 2Ǔ 100 + 41.8° CńW Taking into account of Rq obtain with: 2 oz, 4 layers: 60°C/W. At 2 A, 25°C ambient temperature, RDS(on) 42 mW @ VIN 4.2 V, the junction temperature will be: TJ + TA ) Rq Pd + 25 ) ǒ0.042 2 2Ǔ 60 + 35° C. ORDERING INFORMATION Marking Package Shipping† NCP334FCT2G AD WLCSP 0.96 x 0.96 mm (Pb−Free) 3000 / Tape & Reel NCP335FCT2G AA WLCSP 0.96 x 0.96 mm (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NCP334, NCP335 PACKAGE DIMENSIONS WLCSP4, 0.96x0.96 CASE 567FG ISSUE O ÈÈ ÈÈ D PIN A1 REFERENCE 2X 0.05 C 2X 0.05 C A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. B E DIM A A1 A2 b D E e TOP VIEW A2 0.05 C RECOMMENDED SOLDERING FOOTPRINT* A A1 0.05 C NOTE 3 4X 0.03 C SEATING PLANE e b 0.05 C A B C SIDE VIEW A1 MILLIMETERS MIN MAX 0.54 0.63 0.22 0.28 0.33 REF 0.29 0.34 0.96 BSC 0.96 BSC 0.50 BSC 0.50 PITCH e B PACKAGE OUTLINE 4X 0.50 PITCH 0.25 DIMENSIONS: MILLIMETERS A 1 2 BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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