NCP451 - ON Semiconductor

NCP451
3A Ultra-Small Low Ron
and Controlled Load Switch
with Auto-Discharge Path
The NCP451 is a very low Ron MOSFET controlled by external
logic pin, allowing optimization of battery life, and portable device
autonomy.
Indeed, due to a current consumption optimization with NMOS
structure, leakage currents are eliminated by isolating connected IC on
the battery when not used.
Output discharge path is also embedded to eliminate residual
voltages on the output rail.
Proposed in a wide input voltage range from 0.75 V to 5.5 V, in a
small 0.9 x 1.4 mm WLCSP6, pitch 0.5 mm.
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MARKING
DIAGRAM
WLCSP6
FC SUFFIX
CASE 499BR
XXXXG
AYWW
Features
•
•
•
•
•
•
•
•
0.75 V – 5.5 V Operating Range
12 mW N MOSFET from 3.6 V to 5.5 V
13 mW N MOSFET from 1 V to 3.3 V
DC Current Up to 3 A
Output Auto−Discharge
Active High EN Pin
WLCSP6 0.9 x 1.4 mm
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
XXXX
A
Y
WW
G
Mobile Phones
Tablets
Digital Cameras
GPS
Portable Devices
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PINOUT DIAGRAM
1
2
A
OUT
IN
B
OUT
IN
C
GND
EN
Typical Applications
•
•
•
•
•
XXXXG
AYWW
WLCSP6
AFC SUFFIX
CASE 567KB
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 9
1
Publication Order Number:
NCP451/D
NCP451
V+
LS
NCP451
DCDC Converter
A2
or
B2
LDO
A1
IN
IN
OUT
OUT
Platform IC’n
GND
C2
B1
C1
EN
ENx
EN
0
Figure 1. Typical Application Circuit
PIN FUNCTION DESCRIPTION
Pin Name
Pin Number
Type
Description
IN
A2, B2
POWER
Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as
close as possible to the IC.
GND
C1
POWER
Ground connection.
EN
C2
INPUT
OUT
A1, B1
OUTPUT
Enable input, logic high turns on power switch.
Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as
possible to the IC is recommended.
BLOCK DIAGRAM
IN: Pin A2, B2
OUT: Pin A1, B1
Charge Pump and
soft start control
Control
logic
EN: Pin C2
EN Block
GND: Pin C1
Figure 2. Block Diagram
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2
NCP451
MAXIMUM RATINGS
Rating
Value
Unit
IN, OUT, EN, Pins: (Note 1)
Symbol
VEN, VIN,
VOUT
−0.3 to + 7.0
V
From IN to OUT Pins: Input/Output (Note 1)
VIN, VOUT
0 to + 7.0
V
Human Body Model (HBM) ESD Rating are (Notes 1 and 2)
ESD HBM
1.5
kV
Machine Model (MM) ESD Rating are (Notes 1 and 2)
ESD MM
250
V
ESD CDM
2000
V
Latch−up protection (Note 3)
−Pins IN, OUT, EN
LU
100
mA
Maximum Junction Temperature
TJ
−40 to + 125
°C
Storage Temperature Range
TSTG
−40 to + 150
°C
Moisture Sensitivity (Note 4)
MSL
Level 1
Charge Device Model (CDM) ESD Rating are (Notes 1 and 2)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. According to JEDEC standard JESD22−A108.
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±1.5 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins.
Charge Device Model (CDM) ±2.0 kV per JEDEC standard: JESD22−C101 for all pins.
3. Latchup Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
OPERATING CONDITIONS
Symbol
Parameter
VIN
Operational Power Supply
VEN
Enable Voltage
Conditions
Min
Typ
Max
Unit
0.75
5.5
V
0
5.5
V
TA
Ambient Temperature Range
−40
25
+85
°C
TJ
Junction Temperature Range
−40
25
+125
°C
CIN
Decoupling input capacitor
1
mF
COUT
Decoupling output capacitor
1
mF
RqJA
Thermal Resistance Junction to Air
IOUT
Maximum DC current
PD
(Note 5)
°C/W
100
3
Power Dissipation Rating (Note 6)
Over temperature
0.315
A
W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. The RqJA is dependent of the PCB heat dissipation and thermal via.
6. The maximum power dissipation (PD) is given by the following formula:
PD +
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3
T JMAX * T A
R qJA
NCP451
ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN between 0.75 V to 5.0 V
(Unless otherwise noted). Typical values are referenced to TA = + 25 °C and VIN = 3.6 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
12
20
Unit
POWER SWITCH
IOUT = 200 mA, TA = 25°C
VIN = 5 V
TJ = 125°C
IOUT = 200 mA, TA = 25°C
VIN = 3.6 V
Static drain−source on−state
resistance
TJ = 125°C
VIH
High−level input voltage
VIL
Low−level input voltage
IEN
EN pin leakage current
13
TJ = 125°C
mW
24
28
IOUT = 200 mA, TA = 25°C
13
TJ = 125°C
24
28
IOUT = 200 mA, TA = 25°C
15
TJ = 125°C
EN = low
24
28
IOUT = 200 mA, TA = 25°C
VIN = 0.75 V
Output discharge path
13
TJ = 125°C
VIN = 1.0 V
24
28
IOUT = 200 mA, TA = 25°C
VIN = 2.5 V
20
25
13
TJ = 125°C
VIN = 1.8 V
Rdis
12
IOUT = 200 mA, TA = 25°C
VIN = 3.3 V
RDS(on)
25
28
35
NCP451
NCP451A
1.2
1.7
MW
1.0
1.7
kW
0.8
0.4
VIN = 3.6 V
V
0.1
mA
QUIESCENT CURRENT
Istd
Iq
Standby current
VIN = 4.2 V
EN = low, No load
0.9
2
mA
Quiescent current
VIN = 3.6 V
VIN = 2.5 V
VIN = 1.8 V
VIN = 1.2 V
VIN = 1.0 V
VIN = 0.75 V
EN = high, No load (Note 7)
8
15
mA
RL = 25 W, COUT = 1 mF
600
RL = 25 W, COUT = 1 mF
800
RL = 25 W, COUT = 1 mF
1400
RL = 25 W, COUT = 1 mF
55
RL = 10 W, COUT = 0.1 mF
540
RL = 10 W, COUT = 0.1 mF
670
RL = 10 W, COUT = 0.1 mF
1210
RL = 10 W, COUT = 0.1 mF
2.5
TIMINGS
TEN
Enable time
TR
Output rise time
TON
TF
ON time (TEN + TR)
VIN = 3.6 V
(Note 8)
Output fall time
ms
TIMINGS
TEN
Enable time
TR
Output rise time
TON
TF
ON time (TEN + TR)
VIN = 3.6 V
(Note 8)
Output fall time
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Production tested at VIN = 3.6 V.
8. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground
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4
NCP451
TIMINGS
VIN
EN
VOUT
TEN
TR
TF
TON
Figure 3. Enable, Rise and Fall Time
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5
NCP451
ELECTRICAL CURVES
20
25
19
18
20
RDS(on) (mW)
RDS(on) (mW)
17
16
15
14
13
−40°C
0°C
−25°C
25°C
50°C
85°C
15
10
12
11
10
0.5
1.0
1.5
2.0 2.5
3.0
3.5
4.0 4.5
5.0
5
0.5
5.5
1.0
1.5
2.0 2.5
VIN (V)
Figure 4. RDS(on) vs. VIN, Low Load
4.0 4.5
5.0 5.5
3.0
VIN = 5.5 V
VIN = 4.2 V
VIN = 3.3 V
VIN = 1.8 V
VIN = 0.75 V
25
20
−40°C
VIN = 5 V
VIN = 3.6 V
VIN = 2.5 V
VIN = 1.0 V
85°C
2.0
15
1.5
10
1.0
5
0.5
0
−50
−25
0
25
50
25°C
2.5
IIN (mA)
RDS(on) (mW)
3.5
Figure 5. RDS(on) vs. VIN, Low Load, Multi
Temperature
30
75
100
0
125
0
1
2
3
4
5
JUNCTION TEMPERATURE (°C)
VIN (V)
Figure 6. RDS(on) vs. Temperature, Multi VIN
Voltage
Figure 7. Standby Current (mA) vs.
Temperature
6
3.5
20
−40°C
−40°C
25°C
85°C
125°C
18
16
14
3.0
25°C
85°C
2.5
12
IIN (mA)
IIN (mA)
3.0
VIN (V)
10
8
6
2.0
1.5
1.0
4
0.5
2
0
0
1
2
3
4
5
0
6
0
1
2
3
4
5
VIN (V)
VIN (V)
Figure 8. Quiescent Current (mA) vs.
Temperature
Figure 9. MOSFET Leakage Current (mA) vs.
Temperature
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6
6
NCP451
ELECTRICAL CURVES
VEN = VIN = 5.5 V
VEN = VIN = 3.6 V
IENleak (nA)
4
2
0
−50
−25
0
25
50
75
100
JUNCTION TEMPERATURE (°C)
Figure 10. EN Pin Leakage vs. Temperature
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7
125
NCP451
FUNCTIONAL DESCRIPTION
Overview
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path (Pull down NMOS) stays activated as
long as EN pin is set at low level and VIN > 0.75 V.
In order to limit the current across the internal discharge
N−MOSFET, the typical value is set at RDIS.
The NCP451 is a high side N channel MOSFET power
distribution switch designed to isolate ICs connected on the
battery in order to save energy. The part can be turned on,
with a wide range of battery from 0.75 V to 5.5 V.
Enable Input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing N−MOSFET switch off.
The IN/OUT path is activated with a minimum of Vin of
0.75 V and EN forced to high level.
CIN and COUT Capacitors
IN and OUT, 1 mF, at least, capacitors must be placed as
close as possible the part to for stability improvement.
Auto Discharge
N−MOSFET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
APPLICATION INFORMATION
Power Dissipation
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
equations:
P D + R DS(on)
ǒIOUTǓ
2
PD
= Power dissipation (W)
RDS(on)
IOUT
= Power MOSFET on resistance (W)
= Output current (A)
TJ + PD
R qJA ) T A
Figure 11.
TJ
= Junction temperature (°C)
RqJA
TA
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
Example of application definition.
T J * T A + R qJA
PCB Recommendations
R DS(on)
I2
TJ: junction temperature.
TA: ambient temperature.
Rtheta= Thermal resistance between IC and air, through
PCB.
RDS(on): intrinsic resistance of the IC MOSFET.
I: load DC current.
The NCP451 integrates an up to 3 A rated NMOS FET,
and the PCB design rules must be respected to properly
evacuate the heat out of the silicon. By increasing PCB area,
especially around IN and OUT pins, the RqJA of the package
can be decreased, allowing higher power dissipation.
Routing example: 2 oz, 4 layers with vias across 2 internal
inners.
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8
NCP451
Taking into account of Rtheta obtain with:
1 oz, 2 layers: 100°C/W.
At 3 A, 25°C ambient temperature, RDS(on) 20 mW @ VIN
5 V, the junction temperature will be:
T J * T A + Rtheta
P D + 25 ) ǒ0.02
3 3Ǔ
100 + 43° C
Taking into account of Rtheta obtain with:
2 oz, 4 layers: 60°C/W.
At 3 A, 65°C ambient temperature, RDS(on) 24 mW @ VIN
5 V, the junction temperature will be:
T J + T A ) Rtheta
P D + 65 ) ǒ0.024
3 2Ǔ
60 + 78° C
Figure 13. Demoboard PCB Top View
Figure 12. Demoboard PCB Top View
GND
INPUT1
INPUT2
OUT1
OUT2
GND1
1
1
NCP451
U1
EN
C2
D2
DIODE ZENER1
GND
GND2
2
C2
GND
C1
C1
R1
100 k
A1
OUT B1
OUT
2
D1
DIODE ZENER1
IN
IN
GND
A2
B2
GND3
EN
R2
100 k
Figure 14. Demobard schematic
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NCP451
BILL OF MATERIAL
Quantity
2
3
3
1
2
2
1
Reference Scheme
IN, OUT
IN_2, OUT_2, , EN
C1, C2
D1, D2
GND2,GND
R2, R3
U1
Part Description
Socket, 4mm, metal, PK5
HEADER200
1uF
TVS (not mounted)
GND JUMPER
Resistor 100k 0603
Load switch
Part Number
B010
2.54 mm, 77313−101−06LF
GRM155R70J105KA12#
ESD9x
D3082F05
MC 0.063 0603 1% 100K
NCP451
Manufacturer
HIRSCHMANN
FC
Murata
ON semiconductor
Harvin
MULTICOMP
ON semiconductor
ORDERING INFORMATION
Marking
Option
Package
Shipping†
NCP451FCT2G
451
Auto Discharge
1.2 MW
Case 499BR
(Pb−Free)
3000 / Tape & Reel
NCP451AFCT2G
51A
Auto Discharge
1.0 kW
Case 567KB*
(Pb−Free)
3000 / Tape & Reel
51AC
Auto Discharge
1.0 kW with ChipCoat
Case 567KB*
(Pb−Free)
3000 / Tape & Reel
Device
NCP451AFCCT2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*UBM = 205 mm (±8 mm)
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10
NCP451
PACKAGE DIMENSIONS
WLCSP6, 1.40x0.90
CASE 567KB
ISSUE A
D
PIN A1
REFERENCE
0.25 C
2X
0.25 C
2X
A
ÈÈ
ÈÈ
ÈÈ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
E
DIM
A
A1
A2
b
D
E
e
TOP VIEW
A2
0.10 C
RECOMMENDED
SOLDERING FOOTPRINT*
A
PACKAGE
OUTLINE
0.05 C
NOTE 3
6X
e
b
SEATING
PLANE
e/2
0.50
PITCH
e
0.05 C A B
0.03 C
C
SIDE VIEW
A1
MILLIMETERS
MIN
NOM
MAX
−−−
0.510
−−−
0.142
−−−
0.172
−−−
0.320
0.338
0.195
−−−
0.235
−−−
1.400
1.440
−−−
0.900
0.940
0.50 BSC
1
6X
A1
0.50
PITCH
0.25
DIMENSIONS: MILLIMETERS
2
A
B
C
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
NCP451
PACKAGE DIMENSIONS
WLCSP6, 1.40x0.90
CASE 499BR
ISSUE A
D
PIN A1
REFERENCE
0.25 C
2X
0.25 C
2X
A
ÈÈ
ÈÈ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
E
DIM
A
A1
A2
b
D
E
e
TOP VIEW
A2
MILLIMETERS
MIN
MAX
0.50
−−−
0.17
0.23
0.25 REF
0.21
0.25
1.40 BSC
0.90 BSC
0.50 BSC
0.10 C
RECOMMENDED
SOLDERING FOOTPRINT*
A
PACKAGE
OUTLINE
0.05 C
NOTE 3
6X
e
b
SEATING
PLANE
e/2
0.50
PITCH
e
0.05 C A B
0.03 C
C
SIDE VIEW
A1
6X
A1
1
0.50
PITCH
0.25
DIMENSIONS: MILLIMETERS
2
A
B
C
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
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Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP451/D