NCP333 1.5 A Ultra-Small Controlled Load Switch with Auto-Discharge Path Description http://onsemi.com The NCP333 are low Ron MOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, thanks to a current consumption optimization with PMOS structure, leakage currents are eliminated by isolating connected IC’s on the battery when not used. Output discharge path is also embedded to eliminate residual voltages on the output rail. Proposed in a wide input voltage range from 1.2 V to 5.5 V, and a very small 0.76 x 0.76 mm WLCSP4, 0.4 pitch. WLCSP4 FC SUFFIX CASE 567FJ PIN CONNECTIONS 1 2 A OUT IN B GND EN Features • • • • • • • 1.2 V − 5.5 V Operating Range 55 mW P MOSFET at 3.3 V DC Current up to 1.5 A Output Auto−Discharge Active High EN Pin WLCSP4 0.76 x 0.76 mm This Device is Pb−Free, Halogen Free/BFR Free and is RoHS Compliant ORDERING INFORMATION Applications • • • • • See detailed ordering and shipping information on page 10 of this data sheet. Mobile Phones Tablets Digital Cameras GPS Portable Devices © Semiconductor Components Industries, LLC, 2014 May, 2014 − Rev. 1 (Top View) 1 Publication Order Number: NCP333/D NCP333 A2 B+ B2 IN OUT EN GND SW 7 A1 2 1 2 AVIN NCP63xy/WDFN8 B1 FB U5 EN VOUT 8 PVIN NCP333 4 6 5 EN MODE/PG EN AGND 3 PGND 1 Figure 1. Typical Application Circuit Table 1. PIN FUNCTION DESCRIPTION Pin Name Pin Number Type Description IN A2 POWER Load−switch input voltage; connect a 0.1 mF or greater ceramic capacitor from IN to GND as close as possible to the IC. GND B1 POWER Ground connection. EN B2 INPUT OUT A1 OUTPUT Enable input, logic high turns on power switch. Load−switch output; connect a 0.1 mF ceramic capacitor from OUT to GND as close as possible to the IC is recommended. IN: pin A2 OUT: pin A1 Gate driver and soft start control Control logic EN: pin B2 EN block GND: pin B1 Figure 2. Block Diagram http://onsemi.com 2 NCP333 Table 2. MAXIMUM RATINGS Rating Symbol Value Unit VEN, VIN, VOUT −0.3 to + 7.0 V From IN to OUT Pins: Input/Output VIN, VOUT 0 to + 7.0 V Human Body Model (HBM) ESD Rating are (Notes 1, 2) ESD HBM 4000 V Machine Model (MM) ESD Rating are (Notes 1, 2) ESD MM 200 V TJ −40 to +125 °C Storage Temperature Range TSTG −40 to +150 °C Moisture Sensitivity (Note 4) MSL Level 1 IN, OUT, EN, Pins Maximum Junction Temperature Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. OPERATING CONDITIONS Symbol Parameter Max Unit VIN Operational Power Supply 1.2 5.5 V VEN Enable Voltage 0 5.5 V TA Ambient Temperature Range −40 +85 °C CIN Decoupling input capacitor 0.1 mF COUT Decoupling output capacitor 0.1 mF RqJA Thermal Resistance Junction to Air IOUT Maximum DC current Ipeak Maximum Peak current PD Power Dissipation Rating (Note 6) Conditions WLCSP package (Note 5) Typ 25 °C/W 150 1 ms 1.5 A 2 A TA ≤ 25°C WLCSP package 0.4 W TA = 85°C WLCSP package 0.16 W 1. According to JEDEC standard JESD22−A108. 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22-A114 for all pins. Machine Model (MM) ±200 V per JEDEC standard: JESD22-A115 for all pins. 3. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II. 4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. 5. The RqJA is dependent of the PCB heat dissipation and thermal via. 6. The maximum power dissipation (PD) is given by the following formula: PD + Min T JMAX * T A R qJA http://onsemi.com 3 NCP333 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN between 1.2 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 3.3 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit mW POWER SWITCH RDSON Static drain-source on-state resistance, (Note 7) Vin = 5.5 V, IOUT = 200 mA TA = 25°C 45 55 Vin = 3.3 V, IOUT = 200 mA TA = 25°C 55 74 Vin = 1.8 V, IOUT = 200 mA TA = 25°C 90 125 Vin = 1.2 V, IOUT = 200 mA TA = 25°C 300 400 110 TA = 85°C 135 W Rdis Output discharge path Vin = 3.3 V EN = low 70 TR Output rise time (Note 8) VIN = 3.6 V CLOAD = 1 mF, RLOAD = 25 W 95 ms TF Output fall time (Note 8) VIN = 3.6 V CLOAD = 1 mF, RLOAD = 5 W 11 ms CLOAD = 1 mF, RLOAD = 25 W 40 CLOAD = 1 mF, RLOAD = 100 W 94 Ton Turn on (Note 8) VIN = 3.6 V CLOAD = 1 mF, RLOAD = 25 W 195 ms Ten Enable time VIN = 3.6 V From EN low to high to Vout = 10% of fully on 100 ms VIH High-level input voltage VIL Low-level input voltage ENpd EN pull down resistor 0.9 V 0.5 5 V MW QUIESCENT CURRENT Iq Current consumption Vin = 4.2 V, EN = low, No load 1 mA Vin = 4.2 V, EN = high, No load 1 mA 7. Guaranteed by design and characterization 8. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground http://onsemi.com 4 NCP333 TIMINGS Vin EN Vout TEN TR TDIS TON TOFF Figure 3. Enable, Rise and Fall Time TYPICAL CHARACTERISTICS 400 350 RDS(on) (mW) 300 250 200 150 100 50 0 1 2 3 4 5 V_IN (V) Figure 4. RDS(on) (mW) vs. VIN (V) (ILOAD = 100 mA & Temp 255C) http://onsemi.com 5 6 TF NCP333 TYPICAL CHARACTERISTICS 400 130 1.8 V 120 350 110 RDS(on) (mW) RDS(on) (mW) 1.2 V 300 100 90 80 70 3.3 V 60 0 250 500 200 100 Vin = 5.5 V 50 750 1000 1250 3.6 V 150 3.6 V 50 40 30 250 1.8 V 3.3 V Vin = 5.5 V 0 −50 1500 4.2 V −25 0 25 50 75 100 125 I_OUT (mA) TEMPERATURE (°C) Figure 5. RDS(on) (mW) vs. ILOAD (mA) Figure 6. RDS(on) (mW) vs. Temperature (5C) at ILOAD 100 mA 0.3 150 1.8 V 85°C 0.2 110 I_IN (mA) RDS(on) (mW) 130 90 3.6 V 3.3 V 70 25°C 0.1 Temp = −40°C 50 Vin = 5.5 V 30 −50 4.2 V 0 0 50 100 0 1 2 3 4 5 TEMPERATURE (°C) V_IN (V) Figure 7. RDS(on) (mW) vs. Temperature (5C) at ILOAD 1500 mA Figure 8. Standbycurrent vs. Temperature (5C) No Load 0.4 6 1.0 0.9 0.7 0.2 I_IN (mA) I_IN (mA) 25°C 0.8 0.3 85°C 25°C 85°C 0.6 0.5 Temp = −40°C 0.4 0.3 0.1 0.2 Temp = −40°C 0.1 0 0 0 1 2 3 4 5 0 6 1 2 3 4 5 V_IN (V) V_IN (V) Figure 9. Standbycurrent vs. Temperature (5C) Output Shorted to GND Figure 10. Quiescent Current vs. Temperature (5C) http://onsemi.com 6 6 NCP333 Figure 11. Enable Time and Rise Time Figure 12. Disable Time and Fall Time http://onsemi.com 7 NCP333 FUNCTIONAL DESCRIPTION Overview The auto-discharge is activated when EN pin is set to low level (disable state). The discharge path (Pull down NMOS) stays activated as long as EN pin is set at low level, and Vin > 1.2 V. In order to limit the current across the internal discharge Nmosfet, the typical value is set at 70 W. The NCP333 are a high side P channel MOSFET power distribution switch designed to isolate ICs connected on the battery in order to save energy. The part can be turned on, with a wide range of battery from 1.2 V to 5.5 V. Enable Input Enable pin is an active high. The path is opened when EN pin is tied low (disable), forcing P MOS switch off. The IN/OUT path is activated with a minimum of Vin of 1.2 V and EN forced to high level. Soft Start Each part has a gate soft start control (tr) in order to limit voltage ring when part is enable on a load. Cin and Cout Capacitors IN and OUT, 0.1 mF, at least, capacitors must be placed as close as possible the part for stability improvement. Auto Discharge NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. APPLICATION INFORMATION • TJ = PD x RqJA + TA Power Dissipation Main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: • PD = RDS(on) x (IOUT)2 PD = Power dissipation (W) RDS(on) = Power MOSFET on resistance (W) IOUT = Output current (A) TJ = Junction temperature (°C) RqJA = Package thermal resistance (°C/W) TA = Ambient temperature (°C) PCB Recommendations The NCP333 integrates an up to 1.5 A rated PMOS FET, and the PCB design rules must be respected to properly evacuate the heat out of the silicon. By increasing PCB area, especially around IN and OUT pins, the RqJA of the package can be decreased, allowing higher power dissipation. http://onsemi.com 8 NCP333 Figure 13. Routing Example: 2 oz, 4 Layers with Vias across 2 Internal Inners Example of application definition. TJ−TA = RqJA x PD = RqJA x RDS(on) x I2 TJ: junction temperature. TA: ambient temperature. RqJA = Thermal resistance between IC and air, through PCB. RDS(on): intrinsic resistance of the IC Mosfet. I: load DC current. Taking into account of R_ obtain with: • 1 oz, 2 layers: 150_C/W. At 1.5 A, 25_C ambient temperature, RDS(on) 45 mΩ @ Vin 5 V, the junction temperature will be: TJ = TA + RqJA x PD = 25 + 150 x 0.045 x 1.52 = 40°C/W http://onsemi.com 9 NCP333 ORDERING INFORMATION Device Marking Option Package Shipping† NCP333FCT2G AE Autodischarge WLCSP 0.76 x 0.76 mm 3000 Tape / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. PACKAGE DIMENSIONS WLCSP4, 0.76x0.76 CASE 567FJ ISSUE O A D PIN A1 REFERENCE ÈÈ E 0.05 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. B DIM A A1 A2 b D E e 0.05 C 2X TOP VIEW A2 0.05 C A RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 3 4X A1 0.05 C A B C SIDE VIEW SEATING PLANE A1 e b MILLIMETERS MIN MAX 0.57 0.63 0.18 0.23 0.40 REF 0.24 0.28 0.76 BSC 0.76 BSC 0.40 BSC 0.40 PITCH e B 0.03 C A PACKAGE OUTLINE 4X 0.40 PITCH 0.20 DIMENSIONS: MILLIMETERS 1 2 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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