NCP338 2A Ultra-Small Controlled Load Switch with Auto-discharge Path The NCP338 is very low Ron MOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, due to a current consumption optimization with PMOS structure, leakage currents are eliminated by isolating connected IC on the battery when not used. Output discharge path is also embedded to eliminate residual voltages on the output rail. Proposed in a wide input voltage range from 1.0 V to 3.6 V, in a small 0.8 x 1.2 mm WLCSP6, pitch 0.4 mm. http://onsemi.com MARKING DIAGRAM AM A Y W G Features • • • • • • • • 1.0 V − 3.6 V Operating Range 16 mW P MOSFET at 3.6 V DC Current Up to 2 A Output Auto−discharge Active High EN Pin WLCSP6 0.8 x 1.2 mm ESD Ratings: 6 kV HBM, 250 V MM This is a Pb−Free Device = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package PIN DIAGRAM Typical Applications • • • • • AM AYW G WLCSP6 CASE 567FY Mobile Phones Tablets Digital Cameras GPS Portable Devices 1 2 A OUT IN B OUT IN C GND EN ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. V+ LS NCP338 A2 B2 or LDO EN OUT OUT A1 B1 Platform IC’n C1 C2 IN IN GND DCDC Converter ENx EN 0 Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2013 August, 2013 − Rev. 2 1 Publication Order Number: NCP338/D NCP338 PIN FUNCTION DESCRIPTION Pin Name Pin Number Type Description IN A2, B2 POWER Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as close as possible to the IC. GND C1 POWER Ground connection. EN C2 INPUT OUT A1, B1 OUTPUT Enable input, logic high turns on power switch. Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as possible to the IC is recommended. BLOCK DIAGRAM IN: Pin A2, B2 OUT: Pin A1, B1 Gate driver and soft start control Control logic EN: Pin C2 EN block GND: Pin C1 Figure 2. Block Diagram MAXIMUM RATINGS Rating IN, OUT, EN, Pins Symbol Value Unit VEN , VIN , VOUT −0.3 to + 4.0 V From IN to OUT Pins: Input/Output VIN , VOUT 0 to + 4.0 V TJ −40 to + 125 °C TSTG −40 to + 150 °C Human Body Model (HBM) ESD Rating are (Note 1 and 2) ESD HBM 6000 V Machine Model (MM) ESD Rating are (Note 1 and 2) ESD MM 250 V MSL Level 1 Maximum Junction Temperature Storage Temperature Range Moisture Sensitivity (Note 3) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. According to JEDEC standard JESD22−A108. 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins. 3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. http://onsemi.com 2 NCP338 OPERATING CONDITIONS Symbol Parameter VIN Operational Power Supply VEN Enable Voltage Conditions Min Max Unit 1.0 Typ 3.6 V 0 3.6 TA Ambient Temperature Range −40 25 +85 °C TJ Junction Temperature Range −40 25 +125 °C CIN Decoupling input capacitor 1 mF COUT Decoupling output capacitor 1 mF RqJA Thermal Resistance Junction to Air IOUT Maximum DC current PD Power Dissipation Rating (Note 6) WLCSP package (Note 5) 100 °C/W 2 A TA ≤ 25°C WLCSP package 1 W TA = 85°C WLCSP package 0.4 W 4. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II. 5. The RqJA is dependent of the PCB heat dissipation and thermal via. 6. The maximum power dissipation (PD) is given by the following formula: PD + TJMAX * TA R qJA ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C for VIN between 1.0 V to 3.6 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 3.6 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max 16 27 Unit POWER SWITCH VIN = 3.6 V TA = 25°C −40°C < TA < 85°C VIN = 2.5 V RDS(on) Static drain−source on−state resistance at −200 mA 30 TA = 25°C 21 −40°C < TA < 85°C VIN = 1.8 V 40 TA = 25°C 27 −40°C < TA < 85°C VIN = 1.2 V Rdis Output discharge path VIH High−level input voltage 52 VIL Low−level input voltage IEN EN leakage current mW 87 99 VIN = 1.1 V TA = 25°C 67 EN = low Vin = 3.3 V 65 Vin = 1.8 V 40 45 TA = 25 °C −40°C < TA < 85°C Static drain−source on−state resistance at −100 mA 36 90 0.95 W V 0.5 20 V nA CURRENT CONSUMPTION Istd Iq Standby current Quiescent current VOUT = open, EN = low, VIN = 3.6 V 20 VOUT = open, EN = low, VIN = 1.8 V 4 VOUT = open, EN = high, VIN = 3.6 V 200 600 VOUT = open, EN = high, VIN = 1.8 V 80 300 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground. 8. Guaranteed by design and characterization. http://onsemi.com 3 300 nA NCP338 ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C for VIN between 1.0 V to 3.6 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 3.6 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit TIMINGS TON TR Turn on time VOUT rise time VIN = 1.2 V TOFF TFALL Turn off time VOUT fall time CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) 40 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 40 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) 20 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 25 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) 10 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 10 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) 20 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 200 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) 40 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 40 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) 30 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 35 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) 10 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 10 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) 15 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 150 ms TIMINGS TON TR Turn on time VOUT rise time VIN = 1.8 V TOFF TFALL Turn off time VOUT fall time 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground. 8. Guaranteed by design and characterization. http://onsemi.com 4 ms NCP338 ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C for VIN between 1.0 V to 3.6 V (Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 3.6 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit TIMINGS TON TR CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) Turn on time CLOAD = 1 mF, RLOAD = 500 W (Note 7) TFALL 0 32 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) VOUT rise time CLOAD = 1 mF, RLOAD = 500 W (Note 7) VIN = 3.6 V TOFF 30 20 0 20 CLOAD = 1 mF, RLOAD = 500 W (Note 7) 10 0 10 CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) VOUT fall time CLOAD = 1 mF, RLOAD = 500 W (Note 7) 0 100 TIMINGS VIN EN VOUT TR TOFF Figure 3. Enable, Rise and Fall Time http://onsemi.com 5 40 10 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground. 8. Guaranteed by design and characterization. TON 50 ms CLOAD = 0.1 mF, RLOAD = 500 W (Note 7) Turn off time 80 TF 300 NCP338 TYPICAL CHARACTERISTICS Figure 4. RDS(on) (mW) vs. Vin (V) in Temperature Figure 5. RDS(on) (mW) vs. Iload at Different Input Voltage Figure 6. Standby Current (mA) vs. Vin (V) Figure 7. Quiescent Current (mA) vs. Vin (V) http://onsemi.com 6 NCP338 FUNCTIONAL DESCRIPTION Overview The auto−discharge is activated when EN pin is set to low level (disable state). The discharge path ( Pull down NMOS) stays activated as long as EN pin is set at low level and VIN > 1.0 V. In order to limit the current across the internal discharge N−MOSFET, the typical value is set at 65 W. The NCP338 is a high side P channel MOSFET power distribution switch designed to isolate ICs connected on the battery in order to save energy. The part can be turned on, with a wide range of battery from 1.0 V to 3.6 V. Enable Input Enable pin is an active high. The path is opened when EN pin is tied low (disable), forcing P−MOS switch off. The IN/OUT path is activated with a minimum of Vin of 1.2 V and EN forced to high level. CIN and COUT Capacitors IN and OUT, 1 mF, at least, capacitors must be placed as close as possible the part to for stability improvement. Auto Discharge N−MOSFET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. APPLICATION INFORMATION Power Dissipation TJ + PD Main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: P D + R DS(on) PD RDS(on) IOUT ǒI OUTǓ TJ RqJA TA R qJA ) T A = Junction temperature (°C) = Package thermal resistance (°C/W) = Ambient temperature (°C) PCB Recommendations 2 The NCP338 integrates an up to 2 A rated PMOS FET, and the PCB design rules must be respected to properly evacuate the heat out of the silicon. By increasing PCB area, especially around IN and OUT pins, the RqJA of the package can be decreased, allowing higher power dissipation. = Power dissipation (W) = Power MOSFET on resistance (W) = Output current (A) ORDERING INFORMATION Device NCP338FCCT2G Marking Autodischarge Package Shipping† AM Yes WLCSP 0.8 x 1.2 mm (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NCP338 PACKAGE DIMENSIONS WLCSP6, 0.80x1.20 CASE 567FY ISSUE A ÈÈ ÈÈ D PIN A1 REFERENCE 2X A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. E 0.05 C 2X A3 DIE COAT 0.05 C DIM A A1 A2 A3 b D E e TOP VIEW A2 DETAIL A A2 DETAIL A 0.05 C RECOMMENDED SOLDERING FOOTPRINT* A 0.05 C NOTE 3 6X A1 0.03 C C SIDE VIEW b 0.05 C A B MILLIMETERS MIN MAX −−− 0.60 0.17 0.23 0.28 REF 0.04 REF 0.21 0.25 0.80 BSC 1.20 BSC 0.40 BSC PACKAGE OUTLINE 0.40 PITCH SEATING PLANE e e C A1 B 0.40 PITCH A 1 2 6X 0.229 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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