NC7SZ66 Low Voltage Single SPST Normally Open Bus Switch Features Description The NC7SZ66 is a ultra high-speed (UHS) CMOS compatible single-pole/single-throw (SPST) bus switch. The LOW on resistance of the switch allows inputs to be connected to out-puts with minimal propagation delay and without generating additional ground bounce noise. The device is organized as a 1- bit switch with a switch enable (OE) signal. When OE is HIGH, the switch is on and port A is connected to port B. When OE is LOW, the switch is open and a high-impedance state exists between the two ports.. Broad VCC Operating Range: 1.65V to 5.5V Rail-to-Rail Signal Handling Power Down High-Impedance Inputs/Outputs 5Ω Switch Connection between Two Ports Minimal Propagation Delay through the Switch Low ICC Zero Bounce in Flow-Through Mode Control Input Compatible with CMOS Input Levels Ultra-Small MicroPak™ Packages Space-Saving SOT23 and SC70 Packages Ordering Information Part Number Top Mark Package Packing Method NC7SZ66M5X 7Z66 5-Lead SOT23, JEDEC MO-178 1.6mm 3000 Units on Tape & Reel NC7SZ66P5X Z66 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel NC7SZ66L6X EE 6-Lead, MicroPak™, 1x1mm Wide 5000 Units on Tape & Reel © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 www.fairchildsemi.com NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch December 2010 Figure 1. Logic Symbol Pin Configurations Figure 2. SC70 and SOT23 (Top View) Figure 3. MicroPak™ (Top Through View) NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch Connection Diagrams Pin Definitions Pin # SC70 / SOT23 Pin # MicroPak™ Name Description 1 1 A Bus A I/O 2 2 B Bus B I/O 3 3 GND 4 4 OE Switch Enable Input 5 6 VCC Supply Voltage 5 NC No Connect Ground Function Table OE B0 Function L High Z-State Disconnected H A0 Connect H = HIGH Logic Level L = LOW Logic Level © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Supply Voltage (1) Min. Max. Unit -0.5 7.0 V -0.5 VCC to 0.5 V -0.5 7.0 V -50 mA VS DC Switch Voltage VIN DC Input Voltage IIK DC Input Diode Current IOUT DC Output Sink Current 128 mA DC VCC or Ground Current ±100 mA +150 °C +150 °C +260 °C ICC or IGND TSTG VIN < 0V Storage Temperature Range -65 TJ Junction Temperature Under Bias TL Junction Lead Temperature (Soldering, 10 Seconds) PD ESD Power Dissipation at +85°C SOT-23 200 SC70-5 150 Human Body Model, JEDEC:JESD22-A114 4000 Charge Device Model: JEDEC:JESD22-C101 1500 mW V Note: 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Conditions Min. Max. Unit 1.65 5.50 V VCC Supply Voltage Operating VIN Input Voltage 0 5.5 V VS Switch Input Voltage 0 VCC V Output Voltage 0 VCC V 0 10 VOUT VCC=2.3V - 3.6V tr , tf Input Rise and Fall Times TA Operating Temperature θJA Thermal Resistance VCC=4.5V – 5.5V 0 5 Switching I/O 0 DC -40 +85 SOT-23 300 SC70-5 425 NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch Absolute Maximum Ratings ns/V °C °C/W Note: 2. Unused inputs must be held HIGH or LOW; they may not float. © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 www.fairchildsemi.com 3 All typical values are at the specified VCC, and TA = 25°C. Symbol Parameter VIH HIGH Level Input Voltage VIL LOW Level Input Voltage IIN Control Input Leakage Current IOFF Off Leakage Current VCC 0.75VCC 2.30 to 5.50 0.7VCC TA=+25°C Min. Units Typ. V 2.30 to 5.50 0.3VCC V 0 ≤ VIN ≤ 5.5V ±0.05 ±1.00 µA 1.65 to 5.50 0 ≤ A, B ≤ VCC ±0.05 ±10.00 µA 0 to 5.5 3.0 Switch On (3) Resistance On Resistance (3,4,5) Flatness Quiescent Supply Current Max. 0.25VCC 1.8 ICC Typ. 1.65 to 1.95 2.30 Rflat Min. 1.65 to 1.95 4.5 RON TA=-40 to +85°C Conditions VIN=0V, IIN=30mA 3 7 VIN=2.4V, IIN=15mA 5 12 VIN=4.5V, IIN=30mA 7 15 VIN=0V, IIN=24mA 4 9 VIN=3V, IIN=24mA 10 20 VIN=0V, IIN=8mA 5 12 VIN=2.3V, IIN=8mA 13 30 VIN=0V, IIN=4mA 7 28 VIN=1.8V, IIN=4mA 25 60 Ω 5.0 IA=-30mA, 0 ≤ VBn ≤ VCC 6 3.3 IA=-24mA, 0 ≤ VBn ≤ VCC 12 2.5 IA=-8mA, 0 ≤ VBn ≤ VCC 128 1.8 IA=-4mA, 0 ≤ VBn ≤ VCC 125 1.65 to 5.50 NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch DC Electrical Characteristics Ω VIN= VCC or GND, IOUT=0 0.05 10.00 µA Notes: 3. Measured by the voltage drop between pins A and B at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins. 4. Parameter is characterized but not tested in production. 5. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 www.fairchildsemi.com 4 All typical values are at the specified VCC, and TA = 25°C. Symbol Parameter VCC Conditions TA=-40 to +85°C, CL=50Pf. RU=RD=500Ω Units Min. Typ. Max. 1.65 to 1.95 tPHL, tPLH Propagation Delay Bus-to-Bus(6) 2.3 to 2.7 3.0 to 3.6 4.3 1.2 VIN=0PEN 0.8 4.5 to 5.5 tPLZ, tPHZ Output Enable Time Output Disable Time 2.3 to 2.7 3.0 to 3.6 VIN=2 x VCC for tPZL, VIN=0V for tPZH 1.5 7.0 14.2 1.5 3.3 7.0 1.5 2.4 5.5 4.5 to 5.5 1.5 2.0 4.5 1.65 to 1.95 1.5 9.2 18.2 1.5 5.3 9.0 1.5 4.0 7.0 1.5 2.7 5.0 2.3 to 2.7 3.0 to 3.6 ns Figure 5 Figure 6 ns Figure 5 Figure 6 ns Figure 5 Figure 6 0.3 1.65 to 1.95 tPZL, tPZH Figure VIN=2 x VCC for tPLZ, VIN = 0V for tPHZ 4.5 to 5.5 CIN Control Pin Input Capacitance VCC=0 2 pF CI/O Input / Output Capacitance VCC=05.0V 6 pF Note: 6. This parameter is guaranteed by design but is not tested. The switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch AC Electrical Characteristics Notes: 7. Input driven by 50Ω; source terminated in 50Ω. 8. CL includes load and stray capacitance. 9. Input PRR=1.0MHz; tw=500ns. Figure 4. AC Test Circuit Figure 5. AC Waveforms © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 www.fairchildsemi.com 5 NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch Physical Dimensions 3.00 2.80 5 SYMM CL 0.95 0.95 A 4 B 3.00 2.60 1.70 1.50 1 2 2.60 3 (0.30) 1.00 0.50 0.30 0.95 0.20 1.90 C A B 0.70 TOP VIEW LAND PATTERN RECOMMENDATION SEE DETAIL A 1.30 0.90 1.45 MAX 0.15 0.05 0.22 0.08 C 0.10 C NOTES: UNLESS OTHEWISE SPECIFIED GAGE PLANE A) THIS PACKAGE CONFORMS TO JEDEC MO-178, ISSUE B, VARIATION AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) MA05Brev5 0.25 8° 0° 0.55 0.35 0.60 REF SEATING PLANE Figure 6. 5-Lead SOT23, JEDEC MO-178 1.6mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/SOT23-5L_tr.pdf. Package Designator M5X © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 6 NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch Physical Dimensions Figure 7. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf. Package Designator P5X © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 7 NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch Physical Dimensions 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X BOTTOM VIEW DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER (0.13) 4X Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 8. 6-Lead, MicroPak™, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 8 NC7SZ66 — Low Voltage Single SPST Normally Open Bus Switch © 1996 Fairchild Semiconductor Corporation NC7SZ66 • Rev. 1.0.4 www.fairchildsemi.com 9