TI SN105125_12

SLVS418 − JANUARY 2002
DBV PACKAGE
(TOP VIEW)
features
D
D
D
D
D
D
D
D
D
D
D
Low Dropout Voltage Regulator, 1.2-V
150-mA Load Current Capability
Power Okay (POK) Function
Load Independent, Low Ground
Current,150-µA
Current Limiting
Thermal Shutdown
Low Sleep State Current (Off Mode)
Fast Transient Response
Low Variation Due to Load and Line
Regulation
Output Stable With Low ESR Capacitors
TTL Logic Controlled Enable Input
VI
1
GND
2
EN
3
5
VO
4
POK
applications
D Processor Powerup Sequencing
D Palmtop Computers, Laptops, and
Notebooks
description
The SN105125 is a low dropout voltage regulator with an output tolerance of ±2% over the operating range. The
device is optimized for low noise applications and has a low quiescent current (enable <0.8 V). The device has
a low dropout voltage at full load (150 mA). The power okay function monitors the output voltage and indicates
when an error occurs in the system (active low). In the event of an output fault such as overcurrent, thermal
shutdown, or dropout, the power okay output is pulled low (open drain).
The SN105125 has a fast transient response recovery capability in the event of load transition from heavy load
to light load. The device also minimizes overshoot during this condition. During power down, the output
capacitor and load are de-energized through the internal active shutdown clamp, which is turned on when the
device is disabled.
The SN105125 requires a small output capacitor for stability with low ESR. An input capacitor is not required
unless the bulk ac capacitor is placed away from the device or the power supply is a battery. In this situation,
a 1-µF capacitor is recommended for the application. Low ESR ceramic capacitors may be used with the device
to reduce board space in power applications, a key concern in hand-held wireless devices.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
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1
SLVS418 − JANUARY 2002
functional block diagram
VI
EN
Voltage
Reference
Enable/Disable
Control
Fault
Gate Drive Control
and
Current Amplifier
Error
Amplifier
Thermal
Sensor
VO
Active
Shutdown
Undervoltage
Lockout
Voltage Supervisor
With
Delay Timer
POK
Fault
Overcurrent
Detection and
Dropout Voltage
Detection
Power Okay
Control
GND
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
EN
3
I
Enable/shutdown input (active high)
GND
2
I
Ground
POK
4
I
Power okay indicator
VI
VO
1
I
Input supply voltage
5
O
Output voltage
2
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Main input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
Enable input voltage range, V(EN) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V − VI
Power okay output voltage range V(POK), (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V − VI
Regulated output current limit, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA
Continuous power dissipation, PD, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
Electrostatic discharge susceptibility, V(HBMESD), (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Junction temperature, TJ, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Lead temperature (soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Absolute negative voltage on these terminals should not go below –0.5 V.
3. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each terminal. Devices are ESD sensitive.
Handling precautions are recommended.
recommended operating conditions
MIN
TYP
MAX
UNIT
Main input voltage, VI (see Notes 1 and 2)
3
5.25
V
Enable input voltage, V(EN) (see Notes 1 and 2)
0
V
Power okay voltage, V(POK) (see Notes 1 and 2)
0
VI
VI
0
70
°C
Operating ambient temperature, TA
NOTES: 1. All voltage values are with respect to GND.
2. Absolute negative voltage on these terminals should not go below –0.5 V.
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V
3
SLVS418 − JANUARY 2002
electrical characteristics, TA= 25°C, VI =5 V, V(EN) = VI, IO = 100 µA, CL = 1 µF(unless otherwise noted)
regulator VO
PARAMETER
TEST CONDITIONS
Output voltage
VO
IO = 25 mA
IO = 0
Output voltage accuracy
Quiescent supply current
I(GND)
Ground terminal current (see Note 5)
IL
I(Limit)
Output load current
∆V(LNR)
∆V(LDR)
Line regulation
CL
Load capacitance
I(REV)
NOTES: 4.
5.
6.
−1%
V
2%
µA
1
150
µA
A
150
160
IO = 0.1 mA to150 mA, See Note 6
IO = 100 µA
UNITS
1%
−2%
IO = 0
IO = 150 mA
VO = 0
VI = 3 V to 5.25 V
Load regulation
Dropout voltage
MAX
150
Output current limit
VI − VO
TYP
1.2
IO = 50 mA, TA = 0°C to 70°C (see Note 4)
V(EN) ≤ 0.8 V
IQ
MIN
mA
300
mA
10
mV
2%
3%
1
IO = 150 mA
ESR and capacitance tradeoffs
V
1
µF
1
VI = GND, VO = regulated voltage
50
µA
Assured by design, not tested in production.
Ground terminal current is the regulator quiescent current drawn from the supply to support the load current.
Regulation is measured at constant junction temperature using low duty cycle pulse testing. Devices are tested for load regulation
in the load range from 0.1 mA to 150 mA.
Reverse output current on VI
enable input
PARAMETER
VIL
VIH
I(EN)
TEST CONDITIONS
Regulated shutdown
VI = 3 V to 5.25 V regulated shutdown
VI = 3 V to 5.25 V regulated enabled
Regulated enabled
Enable input current
Resistance discharge
MIN
TYP
MAX
0.8
2
UNITS
V
V
Shutdown, VIL ≤ 0.8 V
0.01
Enabled, VIH ≥ 2 V
0.01
V(EN) ≤ 0.8 V
500
µA
A
Ω
thermal protection (see Note 4)
PARAMETER
T(SD)
T(SDHYS)
TEST CONDITIONS
MIN
Thermal shutdown
Hysteresis
TYP
MAX
UNITS
165
°C
15
°C
NOTE 4: Assured by design, not tested in production.
power okay (see Note 7)
PARAMETER
TEST CONDITIONS
V(POKLO)
V(POKTH)
Low threshold
Output falls % of VO (power NOT okay)
High threshold
Output reaches % of VO, starts delay timer (power okay)
VOL
Ilkg
VO out of regulation
Leakage current
Fault condition, IOL = 100 µA
MIN
TYP
MAX
UNITS
85%
90%
0.4
V
VI = 5 V
1
µA
NOTE 7: Power okay is a function of the output voltage being 5% lower than the specified range. The function is a detection of one of the following:
over current, over temperature, or dropout.
4
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SLVS418 − JANUARY 2002
switching characteristics (see Note 4),TA = 25°C, VI = 5 V, V(EN) = VI, IO = 100 µA, CL = 1 µF(unless
otherwise noted)
PARAMETER
t(STEP)
TEST CONDITIONS
Power up overshoot
Maximum voltage overshoot allowed on output during
powerup
Output transient time limit
Time for output to return within specified regulation range
Output transient voltage limit
Voltage that load step can affect the nominal output voltage
I(SR)
tr
Load step current slew rate
IL = 0.1 mA to 150 mA
tf
td(POK)
Power down fall time
MIN
TYP
MAX
UNIT
1%
µs
5
1%
Power up rise time
Discharge resistance = 500 Ω, VO < 1.08 V
Power okay delay time
VI > V(POKTH) until POK↑
NOTE 4: Assured by design, not tested in production.
10
mA/µs
50
µs
60
µs
2.5
ms
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJC
Thermal impedance, junction-to-case
145
°C/W
RθJA
Thermal impedance, junction-to-ambient
235
°C/W
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SLVS418 − JANUARY 2002
PARAMETER MEASUREMENT INFORMATION
V(POKTH)
90%
VO
td(POK)
POK
Figure 1. Power Okay Timing During Power Up
EN
VI
85% min
90% max
VO
POK Delay 2.5 ms typ
POK
Figure 2. Power Okay Delay Timing and Output Voltage Supervisory
6
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SLVS418 − JANUARY 2002
TYPICAL CHARACTERISTICS
VO
IL
Figure 3. Load Regulation, 50-mA Dynamic Load Step (VI = 3 V)
VO
IL
Figure 4. Load Regulation, 150-mA Dynamic Load Step (VI = 3 V)
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SLVS418 − JANUARY 2002
TYPICAL CHARACTERISTICS
VO
IL
Figure 5. Load Regulation, 50-mA Dynamic Load Step (VI = 5 V)
VO
IL
Figure 6. Load Regulation, 150-mA Dynamic Load Step (VI = 5 V)
8
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SLVS418 − JANUARY 2002
TYPICAL CHARACTERISTICS
VO
POK
EN
Figure 7. Power Okay Delay During Power Up Condition
VO
POK
Figure 8. Power Okay Delay During Power Down Condition
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9
SLVS418 − JANUARY 2002
THERMAL INFORMATION
The SN105125 is designed to provide a continuous load current of 150 mA when the maximum power
dissipation of the package is not exceeded in the application. To determine the maximum power dissipation of
the package, use the junction-to-ambient thermal resistance of the device. The basic equation is as follows:
Maximum power dissipation (W)
PD(MAX) = (TJ(MAX) − TA) / RθJA (maximum power dissipation limit)
Where:
TJ(MAX) is the maximum junction temperature of the die (less than 150°C, minimum thermal shutdown)
TA is the operating ambient temperature
RθJA is the thermal resistance and is layout dependent
The recommended minimum footprint offers a RθJA of 235°C/W.
To determine the actual power dissipation of the regulator, use the following equation:
PD = (VI − VO) IO + VI I(GND) (Watts)
Power dissipation resulting from quiescent current is negligible. When the power dissipation is excessive, the
thermal protection circuit is triggered.
10
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SLVS418 − JANUARY 2002
APPLICATION INFORMATION
47 kΩ
1
VO 5
VI
SN105125
2
GND
Optional: EN May
Be Connected to VI
Enable
3
EN
POK
1.2 V
1 µF
4
Shutdown
Figure 9. Typical Application Schematic
VCC3_3
VCC1_2
1
VO 5
VI
SN105125
2
GND
3
EN
POK
10 kΩ
4
1 µF
1 µF
Figure 10. Typical Application For Processor VID Code Power Sequencing Schematic
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11
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SN105125DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN105125DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN105125DBVR
Package Package Pins
Type Drawing
SPQ
SOT-23
3000
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
178.0
9.0
Pack Materials-Page 1
3.23
B0
(mm)
K0
(mm)
P1
(mm)
3.17
1.37
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN105125DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
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