MC10198 Monostable Multivibrator The MC10198 is a retriggerable monostable multivibrator. Two enable inputs permit triggering on any combination of positive or negative edges as shown in the accompanying table. The trigger input is buffered by Schmitt triggers making it insensitive to input rise and fall times. The pulse width is controlled by an external capacitor and resistor. The resistor sets a current which is the linear discharge rate of the capacitor. Also, the pulse width can be controlled by an external current source or voltage (see applications information). For high–speed response with minimum delay, a hi–speed input is also provided. This input bypasses the internal Schmitt triggers and the output responds within 2 nanoseconds typically. Output logic and threshold levels are standard MECL 10,000. Test conditions are per Table 2. Each “Precondition” referred to in Table 2 is per the sequence of Table 1. • PD = 415 mW typ/pkg (No Load) • tpd = 4.0 ns typ Trigger Input to Q • 2.0 ns typ Hi–Speed Input to Q • Min Timing Pulse Width PWQmin 10 ns typ1 • Max Timing Pulse Width PWQmax >10 ms typ2 • Min Trigger Pulse Width PWT 2.0 ns typ • Min Hi–Speed PWHS 3.0 ns typ Trigger Pulse Width • Enable Setup Time tset 1.0 ns typ • Enable Hold Time thold 1.0 ns typ • 1 CExt = 0 (Pin 4 open), RExt = 0 (Pin 6 to VEE) • 2 CExt = 10 mF, RExt = 2.7 kW http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 MC10198L AWLYYWW 1 16 PDIP–16 P SUFFIX CASE 648 MC10198P AWLYYWW 1 1 PLCC–20 FN SUFFIX CASE 775 A WL YY WW 10198 AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Package Shipping MC10198L CDIP–16 25 Units / Rail MC10198P PDIP–16 25 Units / Rail MC10198FN PLCC–20 46 Units / Rail Publication Order Number: MC10198/D MC10198 LOGIC DIAGRAM VEE VCC 6 4 REXT CEXT Q 5 E pos 7 EXTERNAL PULSE WIDTH CONTROL ENEG 10 DIP PIN ASSIGNMENT 13 TRIGGER INPUT 15 HI-SPEED INPUT 3 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 Q INPUT L L H H L H L H 16 VCC2 Q 2 15 HIGH-SPEED INPUT Q 3 14 N/C CEXT 4 13 TRIGGER INPUT EPOS 5 12 N/C REXT 6 11 N/C 7 10 ENEG VEE 8 9 N/C Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). OUTPUT Triggers on both positive & negative input slopes Triggers on positive input slope Triggers on negative input slope Trigger is disabled TABLE 1 — PRECONDITION SEQUENCE 1. At t = 0 10 ns a.) b.) c.) 2. At t 10 ns Apply VIHmax to Pin 5 and 10. Apply VILmin to Pin 15. Ground Pin 4. a.) Open Pin 1. b.) Apply –3.0 Vdc to Pin 4. Hold these conditions for 10 ns. 3. Return Pin 4 to Ground and perform test as indicated in Table 2. 10 ns 0(Gnd) Pin 4 Voltage (Vdc) ENeg 1 EXT.PULSE WIDTH CONTROL 2 TRUTH TABLE EPos VCC1 -1.0 -2.0 -3.0 Pin 1 open -4.0 -5.0 0 10 20 30 t(ns) TABLE 2 — CONDITIONS FOR TESTING OUTPUT LEVELS (See Table 1 for Precondition Sequence) VIH max VIHA max VILA max P1 VIL min VIL min P2 Pins 1, 16 = VCC = Ground Pins 6, 8 = VEE = –5.2 Vdc Outputs loaded 50 Ω to –2.0 Vdc http://onsemi.com 2 P3 VIL min MC10198 Pin Conditions Test P.U.T. Precondition VOH 2 VOH 3 Precondition VOL 3 VOL 2 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 Precondition VOHA 2 VOHA 3 5 10 13 Pin Conditions 15 Test VIL min P1 VIL min P1 VILA max VIHA min VIL min P3 P2 P3 VIH max VIH max P2 P3 VIH max VIH max P1 P1 P.U.T. Precondition VOHA 2 VOHA 3 Precondition VOLA 3 VOLA 2 Precondition VOLA 2 VOLA 3 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2 Precondition VOLA 3 VOLA 2 http://onsemi.com 3 5 10 13 VIHA min VILA max P1 P1 15 VILA max VIHA min VIL min VIL min P2 P3 VIH max VIH max P2 P3 VIHA min VILA max VIH max VIH max P1 P1 VIH max VIH max VIHA min VILA max P1 P1 MC10198 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Symbol Pin Under Test Power Supply Drain Current IE 8 110 IinH 5, 10 13 15 415 350 560 Input Current –30°C Min +25°C Max Min +85°C Typ Max Max Unit 80 100 110 mAdc 260 220 350 260 220 350 µAdc 0.5 Min µAdc IinL 5 0.5 Output Voltage Logic 1 VOH 2 3 –1.060 –1.060 –0.890 –0.890 –0.960 –0.960 –0.810 –0.810 –0.890 –0.890 0.3 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 2 3 –1.890 –1.890 –1.675 –1.675 –1.850 –1.850 –1.650 –1.650 –1.825 –1.825 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2 3 –1.080 –1.080 Threshold Voltage Logic 0 VOLA 2 3 tT+Q+ tT–Q+ 3 3 2.5 2.5 6.5 6.5 2.5 2.5 High Speed Trigger Input tHS+Q+ 3 1.5 3.2 1.5 Minimum Timing Pulse Width PWQmin 3 10.0 ns Maximum Timing Pulse Width PWQmax 3 >10 ms Min Trigger Pulse Width PWT 3 2.0 ns PWHS 3 –0.980 –0.980 –0.910 –0.910 –1.655 –1.655 –1.630 –1.630 Vdc –1.595 –1.595 Vdc Switching Times (50Ω Load) Trigger Input Min Hi–Spd Trig Pulse Width 4.0 4.0 5.5 5.5 2.5 2.5 6.5 6.5 ns 2.0 2.8 1.5 3.2 ns 3.0 ns Rise Time (20 to 80%) 3 1.5 4.0 1.5 3.5 1.5 4.0 ns Fall Time (20 to 80%) 3 1.5 4.0 1.5 3.5 1.5 4.0 ns Enable Setup Time tsetup (E) 3 1.0 ns Enable Hold Time thold (E) 3 1.0 ns 1. The monostable is in the timing mode at the time of this test. 2. CEXT = 0 (Pin 4 Open); REXT = 0 (Pin 6 tied to VEE). 3. CEXT = 10µF (Pin); REXT = 2.7k (Pin 6). VIHmax 4. P1 VILmin http://onsemi.com 4 MC10198 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) Characteristic Power Supply Drain Current Input Current Output Voltage Logic 1 Output Voltage Logic 0 Threshold Voltage Logic 1 Threshold Voltage Logic 0 Switching Times @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 8 IinH 5, 10 13 15 IinL 5 VOH 2 3 VOL VOHA VOLA VIHmax VEE (VCC) Gnd 6, 8 1, 4, 16 6, 8 6, 8 6, 8 1, 4, 16 1, 4, 16 1, 4, 16 5 6, 8 1, 4, 16 13 6, 8 6, 8 1, 4, 16 1, 4, 16 6, 8 6, 8 1, 4, 16 1, 4, 16 6, 8 6, 8 1, 16, 4 1, 16, 4 15 6, 8 6, 8 1, 16, 4 1, 16, 4 VILmin VIHAmin VILAmax 5,10 13 15 13 (4.) 2 3 13 (4.) 13 2 3 15 15 2 3 15 (50Ω Load) Trigger Input TEST VOLTAGE APPLIED TO PINS LISTED BELOW +1.11V Pulse In Pulse Out –3.2 V +2.0 V 10 5 13 13 3 3 6, 8 6, 8 1, 16, 4 1, 16, 4 tT+Q+ tT–Q+ 3 3 High Speed Trigger Input tHS+Q+ 3 3 6, 8 1, 16, 4 Minimum Timing Pulse Width PWQmin 3 Note 2. 6, 8 1, 16, 4 Maximum Timing Pulse Width PWQmax 3 Note 3. 6, 8 1, 16, 4 PWT 3 13 3 6, 8 1, 16, 4 PWHS 3 15 3 6, 8 1, 16, 4 Minimum Trigger Pulse Width Minimum Hi–Spd Trigger Pulse Width 15 Rise Time (20 to 80%) 3 6, 8 1, 16, 4 Fall Time (20 to 80%) 3 6, 8 1, 16, 4 Enable Setup Time tsetup (E) 3 5 3 6, 8 1, 16, 4 Enable Hold Time thold (E) 3 5 3 6, 8 1, 16, 4 1. The monostable is in the timing mode at the time of this test. 2. CEXT = 0 (Pin 4 Open); REXT = 0 (Pin 6 tied to VEE). 3. CEXT = 10µF (Pin); REXT = 2.7k (Pin 6). VIHmax 4. P1 VILmin Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. http://onsemi.com 5 MC10198 SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25°C VCC1 = VCC2 = +2.0 Vdc Vin Vout 0.1 µF 25 µF Coax Coax 5 Input EPos 7 TPin External Pulse Width Control 10 Pulse Generator +1.11 V TPout Trigger Input 0.1 µF 15 Hi-Speed Input Input Pulse 6 Q RExt 4 2 CExt 50–ohm termination to ground located in each scope channel input. 0.1 µF All input and output cables to the scope are equal lengths of 50–ohm coaxial cable. Wire length should be < 1/4 inch from TPin to input pin and TPout to output pin. Unused outputs are tied to a 50–ohm resistor to ground. VEE = -3.2 Vdc 50% EPos tsetup (E) Trigger Input Q 3 ENeg 13 t+ = t- = 2.0 ± 0.2 ns (20 to 80%) Q 50% tT+Q+ PWT tHold(E) tT-Q+ 50% 50% PWQ High-Speed Trigger Input tHS+Q+ PWHS Q PWQ http://onsemi.com 6 MC10198 5. The MC10198 can be made non–retriggerable. The Q output is fed back to disable the trigger input during the triggered state (Logic Diagram). Figure 7 shows a positive triggered configuration; a similar configuration can be made for negative triggering. FIGURE 7 — VCC VEE RExt 6 CExt 4 Q E Pos External Pulse Width Control -0.9 V ENeg Trigger Input Hi-Speed Input Q http://onsemi.com 9 MC10198 PACKAGE DIMENSIONS PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) B Y BRK –N– M T L-M 0.007 (0.180) U M N S T L-M S G1 0.010 (0.250) S N S D –L– –M– Z W 20 D 1 X V S T L-M S N S VIEW D–D A 0.007 (0.180) M T L-M S N S R 0.007 (0.180) M T L-M S N S Z 0.007 (0.180) H M T L-M S N S K1 K C E F 0.004 (0.100) G J –T– VIEW S G1 0.010 (0.250) S T L-M S N S 0.007 (0.180) M T L-M S VIEW S SEATING PLANE NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). http://onsemi.com 10 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2 10 0.310 0.330 0.040 --- MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2 10 7.88 8.38 1.02 --- N S MC10198 PACKAGE DIMENSIONS –A– 16 9 1 8 –B– CDIP–16 L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE T C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S PDIP–16 P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R –A– 16 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M S T A M http://onsemi.com 11 INCHES MIN MAX 0.750 0.785 0.240 0.295 --0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0 15 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 MC10198 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 12 MC10198/D