CXP5076/5078
CMOS 4-bit Single Chip Microcomputer
For the availability of this product, please contact the sales office.
Description
CXP5076/5078 is a CMOS 4-bit microcomputer
which consists of 4-bit CPU, ROM, RAM, I/O port,
8-bit timer, 8-bit timer/counter, 18-bit time base
timer, 8-bit serial I/O, vector interruption, power on
reset function, liquid crystal displayer (LCD)
controller/driver, D/A conversion 14-bit PWM output
port, a remote control reception circuit with noise
eliminating circuit, 3-bit A/D converters, a 32kHz
timer/event counter and a power supply voltage
detection reset function. They are integrated into a
single chip with the standby function, etc. which are
to be operated at a low power consumption.
80 pin QFP (Plastic)
Features
• Instruction cycle
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.9µs/4.19MHz
122 µs/32kHz
(Possible to select with the program)
ROM capacity
8192 × 8 bits (CXP5078)
6144 × 8 bits (CXP5076)
RAM capacity
448 × 4 bits (Including stack, display area)
43 general purpose I/O ports
8 high current output ports
LCD controller/driver (Possible to direct drive)
— Possible to select with the program the segment output of 16 to 32
— Possible to select with the program the duty of static, 1/2, 1/3 and 1/4
— Possible to select with the program the bias of 1/2, 1/3
14-bit PWM output for D/A conversion
Remote control reception circuit
3-bit A/D converter (8 channels per circuit)
32kHz timer/event counter
Power supply voltage detection reset function
Low voltage operation (2.5V) ..... when operating in 122µs/32kHz
Rich wake-up function
8-bit/4-bit variable serial I/O
Arithmetic and logical operations possible between the entire ROM area, I/O area and the accumulator by
means of the memory mapped I/O
8-bit timer, 8-bit timer/event counter and 18-bit time base timer, independently controlled
2 kinds of power down modes of sleep and stop
Power on reset circuit (mask option)
Provided with 80 pin plastic QFP
Provided with 80 pin piggyback QFP (CXP5070)
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E88037A78-PS
CXP5076/5078
(Common with segment
output S23 to S20)
(Input and output is
possible by port unit)
(Common with A/D
converter analog input)
PORT B
(Common with segment
output S19 to S16)
PORT A
(Common with segment
output S31 to S28)
(Input and output is
possible by bit unit)
(Common with segment
output S27 to S24)
(Common with A/D
converter analog input)
Block Diagram
4
4
4
4
4
4
4
PORT C
PORT D
PORT E
PORT F
PORT G
PORT H
PORT I
(Input and output is
possible by port unit)
Resister
Program
counter (13)
ALU
Accumulator
Data memory
Flag
448 × 4
bits
Program
memory
8192 × 8 bits
(CXP5078)
8144 × 8 bits
(CXP5076)
Timer (8)
Sub time (8)
Stack
Timer/Counter (8)
Serial I/O (8)
Data memory
Interrupt control
PWM (14)
Instruction control
Time base timer (18)
A/D Converter
LCD controller/
driver
Clock control
EXTAL
XTAL
32kHz timer/
event counter
TEX
TX
Remote control
receiving
(Common with serial I/O)
(Common with
port C, port D,
port G, port H)
–2–
RMC
RST
VREF
VSS
VDD
INT
PY0
PY3/EC
COM0 to COM3
Port Y
PX0/SC
SEG0 to SEG15
PX1/SO
4
PX2/SI
16
SEG16 to SEG31
Port X
16
PY1/PWM
VLC1
VLC2
VLC3
PY2/WP
VL
CXP5076/5078
PD2/SEG29
PD3/SEG28
PC0/SEG27
PC1/SEG26
PC2/SEG25
PC3/SEG24
VSS
TX
NC
TEX
VREF
PH0/SEG23
PH1/SEG22
PH2/SEG21
PH3/SEG20
PG0/SEG19
Pin Configuration (Top View)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PG1/SEG18
1
64
PD1/SEG30
PG2/SEG17
2
63
PD0/SEG31
PG3/SEG16
3
62
PY3/EC
SEG15
4
61
PY2/WP
SEG14
5
60
PY1/PWM
SEG13
6
59
PY0
SEG12
7
58
PE3
SEG11
8
57
PE2
SEG10
9
56
PE1
SEG9
10
55
PE0
SEG8
11
54
PF3
SEG7
12
53
PF2
SEG6
13
52
PF1
SEG5
14
51
PF0
SEG4
15
50
PA3
SEG3
16
49
PA2
SEG2
17
48
PA1
SEG1
18
47
PA0
SEG0
19
46
PX2/SI
COM3
20
45
PX1/SO
COM2
21
44
PX0/SC
COM1
22
43
NC
COM0
23
42
PB3/AD7
VLC1
24
41
PB2/AD6
–3–
AD5/PB1
AD3/PI3
Note) Do not make any connections to NC pins.
AD4/PB0
AD2/PI2
AD1/PI1
AD0/PI0
NC
VDD
RST
EXTAL
INT
XTAL
VL
RMC
VLC3
VLC2
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
CXP5076/5078
Pin Description
Symbol
Name
I/O
Equivalent Circuit
Description
VDD
Supply voltage
—
Positive voltage supply pin
VSS
Grounding
voltage
—
GND pin
P
EXTAL
Clock input
I
EXTAL
N
N P
XTAL
XTAL
Clock output
Clock oscillation circuit input pin.
Connect the crystal oscillator or
ceramic resonator between the EXTAL
and XTAL. When using as the
external clock input, connect the clock
oscillation source to the EXTAL pin
and open the XTAL pin.
Clock oscillation circuit output pin
O
P
Mask option E
I/O
RST
Reset
INT
External
interrupt
I
RMC
Remote control
input
I
Port X2
Serial input
I
PX2/SI
Serves as the incorporated power-on
reset circuit output pin.
N
When inputting a reset signal from the
outside, provide 2 instruction cycles or
Output pull-up resistor (P-ch Tr) longer of an "L" level (0V).
N-ch Tr output
Schmitt inverter input
Serves the interrupt input pin.
Permits the selection with a program
of the edge and the level modes.
Remote control receiver input pin
Schmitt inverter input
Doubles as a serial interface (8 bits)
input pin and as bit "2" (input) of port X.
Data
Output Select
Disable
Standby
(Note 2)
(Only during
tri-state output)
PX1/SO
Port X1
Serial output
P
I/O
N
See Note 2) for the output
circuit format.
Inverter input
–4–
Doubles as a serial interface (8 bits)
output pin and as bit "1" (input) of
port X. (SO output possible to inhibit
with the program.)
CXP5076/5078
Symbol
Name
I/O
Equivalent Circuit
Data
Output Select
Disable
Standby
PX0/SC
Port X0
Serial clock
Description
(Note 2)
(Only during
tri-state output)
Doubles as shift clock input/output pin
for the serial interface and as bit "0"
(input) of port X.
I/O
See Note 2) for the output
circuit format.
Schmitt inverter input
PY3/EC
Port Y3
Event count
input
I
Doubles as event counter (8 bits) input
pin and as bit "3" (input) of port Y.
PY2/WP
Port Y2
Wake-up
input
I
Doubles as wake-up input pin to
release the standby state and as bit
"2" (input) of port Y.
PY1/PWM
Port Y1
PWM
generator
output
O
Port Y0
O
PY0
PA0
to
PA3
PB0/AD4
to
PB3/AD7
PE0
to
PE3
Port A
Port B
Analog voltage
input
Port E
PF0
to
PF3
Port F
PI0/AD0
to
PI3/AD3
Port I
Analog voltage
input
Schmitt inverter input
Data
(Note 1)
Output Select
Disable
See Note 1) for the output
circuit format.
I/O
Data
Output Select
Disable
Standby
I/O
I/O
I/O
(Note 2)
(Only during
tri-state output)
P
N
See Note 2) for the output
circuit format.
Inverter input
Doubles as PWM generator (14 bits)
output pin and as bit "1" (output) of
port Y.
Output pin for bit "0" of port Y.
This 4-bit input/output port permits its
each individual bit to be programmed
to serve either as input or output. For
the output format, a tri-state and pullup resistor possible to be programmed,
and it is also used as the standby
resetting pin.
This 4-bit input/output port has the
functions that are equivalent to those
of port A. It is also used for A/D
converter input.
This 4-bit input/output port permits its
each individual port to be programmed
to serve either as input or output. For
the output format, a tri-state and pullup resistor possible to be programmed.
This 4-bit input/output port has the
functions that are equivalent to those
of port E.
This 4-bit input/output port has the
functions that are equivalent to those
of port E.
It is also used for A/D converter input.
I/O
–5–
CXP5076/5078
Symbol
Name
PD3/
SEG31
to
PD0/
SEG28
Port D
Segment
output
PC3/
SEG27
to
PC0/
SEG24
Port C
Segment
output
PH3/
SEG23
to
PH0/
SEG20
Port H
Segment
output
PG3/
SEG19
to
PG0/
SEG16
I/O
Equivalent Circuit
O
Segment
P
Port G
Segment
output
O
O
N
The transfer gate input signal
is controlled based on 1/2, 1/3
bias method in advance.
Data
Output Select
Standby
LCD/PORT
select
Port C, D, G, H
(Note 3)
See Note 3) for the output
circuit format.
O
P
SEG0
to
SEG15
Segment
output
Description
Doubles as a 4-bit output port (For the
output format, the inverter and pull-up
resistor possible to be programmed.)
and as the segment signal output pin
for LCD.
Doubles as a 4-bit output port (The
output format is equivalent to port D.)
and as the segment signal output pin
for LCD.
Doubles as a 4-bit output port (The
output format is equivalent to port D.)
and as the segment signal output pin
for LCD. (Possible to designate in bit
units.)
Doubles as a 4-bit output port (The
output format is equivalent to port D.)
and as the segment signal output pin
for LCD.
N
O
Segment signal output pin for LCD
The transfer gate input signal
is controlled based on 1/2, 1/3
bias methods in advance.
P
COM0
to
COM3
Common
output
O
Common signal output pin for LCD
N
Transfer gate output
VLC1
to
VLC3
Power supply
for LCD
—
VL
Cut-off
output
O
Bias power supply pin for LCD
N
–6–
Control pin which cuts off the current
input to the bias resistor for the
external LCD during standby.
CXP5076/5078
Symbol
WP
Name
Wake-up
input
I/O
Equivalent Circuit
It is the input pin to release the
standby mode, and release by "1".
I
Schmitt inverter input
Mask option
TEX
32kHz T/C
clock input
I
TEX
P
N
N P
TX
32kHz T/C
clock output
O
VREF
Reference
voltage input
I
Description
Input pin for 32kHz timer clock
generation circuit. Connect the
32.768kHz crystal oscillator between
TEX and TX. When using as the
event clock input, connect the clock
oscillation source to the TEX pin,
open the TX pin.
Output of clock generation circuit
TX
Reference voltage input for power
supply voltage resetting circuit.
Connect the zener diode normally.
For all output ports, the output states of ports during standby possible to be programmed to the state holding
before standby or the change to the high impedance.
When the pull-up resistor output is selected, it becomes a pulled-up state even it is input port.
During standby, it is impossible to change to the high impedance of PY0 and PY1 in the inverter output state. To
change to the high impedance, select the pull-up resistor output, and then set to the high level output ("1" state).
–7–
CXP5076/5078
Note 1) Possible to select out of the following two ways for the output circuit format.
(port units: programmable)
(a) Inverter output
(b) Pull-up resistor output
Standby
Output Select
Data
P∗
P
P
N
Note 2) Possible to select out of the following two ways for the output circuit format.
(port units: programmable)
(a) Tri-state output
(b) Pull-up resistor output
Standby
Output Select
P∗
P
Disable
P
Data
N
Note 3) Possible to select out of the following two ways for the output circuit format.
(port units: programmable)
(a) Inverter output
(b) Pull-up resistor output
LCD/PORT
Select
Standby
P∗
P
Output Select
P
Data
N
∗ As the output pull-up resistor is CMOS pull-up output of about 10kΩ, the pull-up resistor becomes OFF state
during "L" output.
–8–
CXP5076/5078
Absolute Maximum Ratings
(Ta = –20 to +75°C, VSS = 0V)
Item
Symbol
Rating
Unit
Remarks
Power supply voltage
VDD
–0.3 to +7.0
V
LCD bias voltage
VCL1,
VCL2,
VCL3
–0.3 to +7.0∗1
V
Input voltage
VIN
Output voltage
VOUT
High level output current
IOH
–5
mA
General purpose port∗2: per pin
High level total output current
∑IOH
–50
mA
Entire pins total
IOL
15
mA
IOLC
20
mA
General purpose port∗2: per pin
High current port∗3: per pin
Low level total output current
∑IOL
100
mA
Entire pins total
Operating temperature
Topr
–20 to +75
°C
Storage tamperature
Tstg
–55 to +150
°C
Allowable power dissipation
PD
600
mW
Low level output current
–0.3 to +7.0∗1
–0.3 to +7.0∗1
V
V
∗1 VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V.
∗2 Specifies the output current of the general purpose I/O port PA to PI, SO, SC, PY0 and PY1.
∗3 The high current operation transistors are the N-ch transistors of the PC and PD ports.
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
better take place under the recommended operation conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.
Recommended Operating Condition
Item
Power supply voltage
LCD bias voltage
High level input voltage
Min.
Max.
Unit
Remarks
4.5
5.5
V
Guaranteed range of operation by
EXTAL clock
2.5
5.5
V
Guaranteed range of operation by
TEX clock, guaranteed range of
data hold during STOP.
VSS
VDD
V
Liquid crystal power supply range∗1
VIH
0.7VDD
VDD
V
VIHS
0.8VDD
VDD
V
Symbol
VDD
VCL1, VCL2,
VCL3
VIHEX
Low level input voltage
Operating temperature
(Vss = 0V)
VDD – 0.4 VDD + 0.3
V
VIL
0
0.3VDD
V
VILS
0
0.2VDD
V
VILEX
–0.3
0.4
V
Topr
–20
+75
°C
Hysteresis input∗2
EXTAL pin∗3
Hysteresis input∗2
EXTAL pin∗3
∗1 The optimum value is determined by the characteristics of the liquid crystal display element used.
∗2 The TEX pin when the counter mode is selected by each of INT, RMC, PX0, PX2, PY2, PY3, RST pins and
mask option.
∗3 Specified only during external clock input.
–9–
CXP5076/5078
Electrical Characteristics
DC characteristics
Item
High level
output voltage
Low level
output voltage
Symbol
VOH
VOL
IIHE
IILE
Input current
(Ta = –20 to +75°C, Vss = 0V)
IIHT
IILT
IILR
IIL
High impedance
I/O leakage
IIZ
current
PA to PI∗1
PX0, PX1
PY0, PY1
VL (VOL only)
RST (VOL only)
PC∗1, PD∗1
EXTAL
TEX∗4
VDD = 4.5V, IOH = –0.5mA∗2
VDD = 4.5V, IOH = –1.0mA∗2
VDD = 4.5V, IOH = –10µA∗3
VDD = 4.5V, IOH = –200µA∗3
COM0 to COM3
Segment output
impedance
SEG0 to SEG15
SEG16 to SEG31∗1
Min. Typ. Max. Unit
4.0
V
3.5
V
4.0
V
2.4
V
VDD = 4.5V, IOL = 1.8mA
0.4
V
VDD = 4.5V, IOL = 3.6mA
0.6
V
VDD = 4.5V, IOL = 12mA
1.5
V
VDD = 5.5V, VIH = 5.5V
0.5
40
µA
VDD = 5.5V, VIL = 0.4V
–0.5
–40
µA
VDD = 5.5V, VIH = 5.5V
0.1
10
µA
–0.1
–10
µA
–1.5
–400 µA
RST∗5
VDD = 5.5V, VIL = 0.4V
PA∗6, PB∗6, PE∗6,
PF∗6, PI∗6, PX0∗6,
PX1∗6, PX2∗8, PY0∗7,
PY1∗7, PY2∗8, PY3∗8,
VDD = 5.5V, VI = 0, 5.5V
INT∗8, RMC∗8,
∗
5
∗
4
RST , TEX
Common output
RCOM
impedance
RSEG
Condition
Pin
±10
µA
±10
µA
3
5
kΩ
5
15
kΩ
7
20
mA
50
250
µA
VDD = 5.5V,
4.19MHz oscillation
5
12
mA
VDD = 3V, 32kHz oscillation
40
200
µA
7
40
µA
10
µA
20
pF
VDD = 5V
VLC1 = 3.75V
VLC2 = 2.5V
VLC3 = 1.25V
Entire output pins open
Crystal oscillation
(C1 = C2 = 22pF)
of VDD = 5.5V, 4.19MHz
IDD1
Crystal oscillation
(C1 = C2 = 47pF)
of VDD = 3V, 32kHz
IDD2
Sleep mode
Supply current
IDDSP1
IDDSP2
IDDS1
IDDS2
Input capacity
CIN
VDD
Stop mode
VDD = 3V, 32kHz with T/C
VDD = 5.5V, 32kHz without T/C
(For mask option select
counter, Pin is fixed.)
Other than VLC1 to
VLC3, COM0 to COM3, Clock 1MHz
SEG0 to SEG15,
0V other than the measured pins
SEG16 to SEG31∗1,
VSS, VDD pins
– 10 –
10
CXP5076/5078
∗1 The PC, PD, PG and PH show when the combined pins are selected as the port, and SEG16 to SEG31
show when the combined pins are selected as the segment output.
∗2 It is when the respective pins of PA to PI, PX0 and PX1 select the tri-state output circuit, and PY0 and PY1
are when the inverter output circuit is selected.
∗3 It is when the respective pins of PA to PI, PX0, PX1, PY0 and PY1 select the pull-up resistor.
∗4 The TEX pin specifies the input current when the crystal oscillation is selected by the mask option, and
specifies the leakage current when the schmitt input is selected.
∗5 The RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current
when non-resistor is selected.
∗6 The respective pins of PA, PB, PE, PF, PI, PX0 and PX1 specify the input current when the pull-up resistor
is selected, and specify the leakage current when the port state during using the tri-state output circuit or
standby is selected at high impedance.
∗7 The respective pins of PY0 and PY1 specify the input current when the pull-up resistor is selected, and
specify the leakage current when the port state during standby is selected at high impedance.
∗8 The respective pins of PX2, PY2, PY3, INT and RMC only specify the leakage current.
AC characteristics
(1) Clock timing
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Pin
Condition
XTAL
EXTAL
Fig. 1, Fig. 2
EXTAL
Fig. 1, Fig. 2
(External clock drive)
System clock frequency
fc
System clock input pulse
width
tXL
tXH
System clock input rising
and falling times
tCR
tCF
System clock frequency
fCS
TEX∗2
TX
VDD = 2.5 to 5.5V
Fig. 3
Event count clock input
pulse width
tEL
tEH
EC
Fig. 4
Event count clock input
rising and falling times
tER
tEF
EC
Fig. 4
Event count input clock
input pulse width
tTL
tTH
TEX∗3
Fig. 4
Event count input clock
rising and falling times
tTR
tTF
TEX∗3
Fig. 4
Min.
Typ.
1
Max. Unit
5
90
ns
200
32.768
ns
kHz
tsys∗1
+ 0.05
µs
20
10
ms
µs
20
∗1 tsys in the EXTAL input clock is 8/fc.
tsys in the TEX input clock is 4/fcs.
∗2 Specified when the crystal oscillation mode is selected by the mask option.
∗3 Specified when the counter mode is selected by the mask option.
Note) When adjusting the frequency accurately, there may be cases in which they may differ from Fig. 2.
– 11 –
MHz
ms
CXP5076/5078
1/fc
VDD – 0.4V
EXTAL
0.4V
tCF
tXH
tXL
tCR
Fig. 1. Clock timing
AAAAA
AAAA
AAAAA
AAAA
AAAAAAAAA
Crystal oscillation
Ceramic oscillation
EXTAL
External clock
EXTAL
XTAL
C1
XTAL
OPEN
C2
Fig. 2. Clock applying condition
AAAA
AAAA
AAAA
Crystal oscillation
TEX
TX
C1
C2
Fig. 3. 32kHz clock applying condition
0.8VDD
EC
TEX
0.2VDD
tEH
tTH
tEF
tTF
tEL
tTL
Fig. 4. Event count clock timing
– 12 –
tER
tTR
CXP5076/5078
(2) Serial transfer
Item
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Symbol
Serial transfer clock (SC) tKCY
cycle time
Pin
Condition
Input mode
SC
Unit
µs
2tsys
µs
tsys/8 + 0.7
µs
tsys – 0.1
µs
tsys – 1.6
µs
SC input mode
0.1
µs
SC output mode
0.2
µs
tsys/8 + 0.5
µs
0.1
µs
Output mode
Output mode∗1
Output mode∗2
SC
Max.
tsys/4 + 1.42
Input mode
Serial transfer clock (SC) tKH
high and low level widths tKL
Min.
Serial data input setup
time (against SC ↑)
tSIK
SI
Serial data input hold
time (against SC ↑)
tKSI
SI
High data output delay
time from SC falling∗3
tKSO
SO
tsys/8 + 0.5
µs
High data output delay
time from SC falling∗4
tKSO
SO
tsys/8 + 1.6
µs
Low data output delay
time from SC falling
tKSO
SO
tsys/8 + 0.5
µs
SC input mode
SC output mode
Notes) 1. tsys in the EXTAL input clock is 8/fc. (It is impossible to use in TEX input clock.)
2. The load of data output delay is 50pF + 1TTL.
∗1 It is specified when PX0/SC pin is selected to the tri-state output by the program.
∗2 It is specified when PX0/SC pin is selected to the pull-up resistance by the program.
As the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock
frequency fc.
∗3 This item is specified when PX1/SO pin is selected to the tri-state output by the program.
∗4 This item is specified when PX1/SO pin is selected to the pull-up resistance by the program.
tKCY
tKL
tKH
0.8VDD
SC
0.2VDD
tSIK
tKSI
0.8VDD
Input data
SI
0.2VDD
tKSO
0.8VDD
SO
Output data
0.2VDD
Fig. 5. Serial transfer timing
– 13 –
CXP5076/5078
(3) A/D converter
(Ta = –20 to +75°C, Vss = 0V)
Analog input voltage
Pin
Condition
Digital conversion value
0.0 to 0.33V
000
0.82 to 1.29V
001
AD0
to
AD7
1.78 to 2.21V
2.69 to 3.06V
010
VDD = 5V
011
3.56 to 4.06V
100
4.62 to 5.0V
101
Note) The digital conversion value are the values when ABH address of the RAM file 1 in the program are read.
(4) Power Supply Voltage Detection Reset Function
(Ta = –20 to + 75°C, Vss = 0V)
Item
Symbol
Pin
Condition
Min.
Power supply voltage
detection reset function of
operation voltage range
VLPOP
VDD
Voltage range allowing system
operation (32kHz system
operation below VDD = 4.5V)
2.5
Power supply voltage drop
detection function
VPOP
VDD
When VREF pin voltage is 3.3V
Flag set when voltage drops
System reset when voltage rises
3.8
Typ.
4.0
Max.
Unit
5.5
V
4.2
V
The graph in Fig. 6 shows the relationship between the power supply voltage VDD and reference voltage VREF
of the power supply voltage detection reset function.
Note) The graph in Fig. 6 serves as guide to the function operation area obtained using average devices.
Individual adjustment is needed when Zener diodes, etc., are connected to the VREF pin.
VDD [V]
5.5
2.5
0
AAAA
AAAA
AAAA
1.6
5.0
VREF [V]
Fig. 6. Power supply voltage detection reset function chart
– 14 –
CXP5076/5078
(5) Others
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)
Item
Symbol
Pin
External interruption high and
low level widths
tI1H, tI1L
INT
Reset input low level width
tRSL
RST
Wake-up input high level width
tWPH
WP
Wake-up input low level width
tWPL
PA0 to
PA3
Condition
Min.
During edge
detection mode
Max.
Unit
tsys + 0.05
µs
2tsys∗1
µs
Stop mode
500
ns
Sleep mode
tsys + 0.05
µs
Stop mode
500
ns
Sleep mode
tsys + 0.05
µs
Note) tsys in the EXTAL input clock is 8/fc.
tsys in the TEX input clock is 4/fcs.
∗1 For resetting when operating in TEX input clock, hold the low level more than the oscillation stabilizing time
of EXTAL input clock.
tI1L
tI1H
0.8VDD
INT
(Rising edge)
0.2VDD
tI1H
tI1L
0.8VDD
INT
(Falling edge)
0.2VDD
Fig. 7. Interruption input timing
tRSL
RST
0.2VDD
Fig. 8. Reset input timing
tWPH
0.8VDD
WP
Fig. 9. Wake-up input timing
tWPL
PA0 to PA3
0.2VDD
Fig. 10. Wake-up input timing
– 15 –
CXP5076/5078
Power on reset∗
(Ta = –20 to +75°C, Vss = 0V)
Item
Symbol
Power supply rising time
tR
Power supply cut-off time
tOFF
Pin
VDD
Condition
Power on reset
Repetitive power on reset
∗ Specifies only when power on reset function is selected.
4.5V
VDD
0.2V
0.2V
tR
tOFF
The power supply should rise smoothly.
Fig. 11. Power on reset
– 16 –
Min.
Max.
Unit
0.05
50
ms
1
ms
CXP5076/5078
Notes on Application
See Fig. 11, Additive capacity calculation chart, when using the crystal oscillator and select the appropriate
capacity.
C – Additive capacity [pF]
Ta = –20 to +75°C, VDD = 4.5 to 5.5V
AAA
AAA
AAA
AAA
AAA
200
150
100
50
0.1
1
EXTAL XTAL
C1
C2
C1 = C2 = C
5
10
100
f – Crystal oscillation frequency [MHz]
Fig. 12. Crystal oscillation circuit additive capacity calculation chart
Note) The above chart shows a range in which the average quartz resonator has a relatively fast oscillation
rising edge and stable characteristics. The capacity should be selected to correspond to the
appropriate constant for each quartz resonator, should the frequency of the quartz resonator be
accurately adjusted.
Fig. 13 shows an example of a circuit which can accurately adjust the frequency. Used here a trimmer
capacitor.
VDD
EXTAL
XTAL
Rd
C2
C1
Fig. 13. Frequency adjustment circuit
When using the A/D converter as the key input, it is recommended that the circuit structure shown in Fig. 14
be used.
VDD
AD
4.7k
1.2k
SW1
1.8k
SW2
3.3k
SW3
8.2k
SW4
SW5
VSS
(Resistance is all E12 series)
Fig. 14. Recommended example of key circuit by A/D converter
– 17 –
CXP5076/5078
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
17.9 ± 0.4
+ 0.4
14.0 – 0.1
40
A
+ 0.2
0.1 – 0.05
25
1
24
0.8
0.12
M
+ 0.15
0.35 – 0.1
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP080-P-1420
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
1.6g
JEDEC CODE
– 18 –
0.8 ± 0.2
80