TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 5V/12V eFuse with Over Voltage Protection and Blocking FET Control Check for Samples: TPS2592Ax, TPS2592Bx FEATURES DESCRIPTION • • • • • • • • • • • The TPS2592xx family of eFuses are highly integrated circuit protection and power management solutions in a tiny package. With few external components and multiple protection modes, they are a robust defense against overloads, shorts circuits, voltage surges, excessive inrush current, and reverse current. Only one external resistor is required for setting the current limit level, which has a typical accuracy of ±15%. Over voltage events are limited by internal clamping circuits to a safe fixed maximum, with no external components required. TPS2592Ax devices provide over voltage protection (OVP) for 12V systems and TPS2592Bx devices for 5V systems. In cases with particular voltage ramp requirements, a dV/dT pin is provided that can be programmed with a single capacitor to ensure proper output ramp rates. Many systems, such as SSDs, must not allow holdup capacitance energy to dump back through the FET body diode onto a drooping or shorted bus. The BFET pin is for such systems. An external NFET can be connected “back to back” with the TPS2592xx output and the gate driven by BFET. When the TPS2592xx is disabled, then current flow is stopped in both directions. TPS2592xL parts will latch off after a fault and TPS2592xA parts will attempt to restart after the thermal shutoff resets. 1 • 12V Protection – TPS2592Ax 5V Protection – TPS2592Bx Integrated 28mΩ Pass MOSFET Absolute Maximum Voltage of 20V Programmable Current Limit (±15% Accuracy) Blocking FET Driver Fixed Over Voltage Setting Programmable OUT Slew Rate, UVLO Built-in Thermal Shutdown UL Recognition Pending Safe during Single Point Failure Test (UL60950) Small Foot Print – 10L (3mm x 3mm) VSON APPLICATIONS • • • • • • HDD and SSD Drives Set Top Boxes Servers / AUX Supplies Fan Control PCI/PCIe Cards Switches/Routers Transient: Output Short Circuit Application Schematic PRODUCT INFORMATION PART NUMBER UVLO OVERVOLTAGE CLAMP (TYP) FAULT RESPONSE STATUS TPS2592AA 4.3 V 15.0 V Auto Retry Active TPS2592BA 4.3 V 6.1 V Auto Retry Preview TPS2592AL 4.3 V 15.0 V Latched Preview TPS2592BL 4.3 V 6.1 V Latched Active 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com ORDERING INFORMATION (1) PART NUMBER (1) PART MARKING PACKAGE TPS2592ALDRC 2592AL 10-pin DRC TPS2592AADRC 2592AA 10-pin DRC TPS2592BLDRC 2592BL 10-pin DRC TPS2592BADRC 2592BA 10-pin DRC For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE (2) Supply voltage range (3) Output voltage VIN MIN MAX –0.3 20 VIN (10ms Transient) 22 V –0.3 VIN + 0.3 V ILIM –0.3 7 V EN/UVLO –0.3 7 V dV/dT –0.3 7 V BFET –0.3 30 V ±2000 V ±500 V Electrostatic discharge OUT UNIT Human body model (4) Charged-device model (5) Continuous power dissipation (1) (2) (3) (4) (5) See Thermal Characteristics Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A Tested in accordance with JEDEC Standard 22, Test Method A115-A THERMAL CHARACTERISTICS (1) THERMAL METRIC TPS2592xx DRC (10) PINS θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance 21.2 ψJT Junction-to-top characterization parameter 1.2 ψJB Junction-to-board characterization parameter 21.4 θJCbot Junction-to-case (bottom) thermal resistance 5.9 (1) 2 UNIT 45.9 53 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) Input voltage range MIN TYP MAX VIN TPS2592Ax 4.5 12 13.8 VIN TPS2592Bx 4.5 5 UNIT 5.5 BFET 0 VIN+6 dV/dT, EN/UVLO 0 6 V ILIM 0 ILIM 40.2 100 162 kΩ OUT 0.1 1 1000 µF 1 1000 nF Operating junction temperature range, TJ –40 25 125 °C Operating Ambient temperature range, TA –40 25 85 °C Resistance External capacitance dV/dT 3.3 ELECTRICAL CHARACTERISTICS –40°C ≤ TJ ≤ 125°C, VIN = 12V for TPS2592Ax, VIN = 5V for TPS2592Bx, VEN/UVLO = 2V, RILIM = 100kΩ, CdVdT = OPEN. All voltages referenced to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.3 4.45 V VIN (INPUT SUPPLY) VUVR UVLO threshold, rising VUVhyst UVLO hysteresis IQON Supply current IQOFF VOVC 4.15 5.4% Enabled: EN/UVLO = 2V, TPS2592AX 0.2 0.42 0.65 mA Enabled: EN/UVLO = 2V, TPS2592Bx 0.4 0.62 0.80 mA 0.1 0.25 mA EN/UVLO = 0V Over-voltage clamp VIN > 16.5V, IOUT = 10mA, TPS2592Ax 13.8 15 16.5 TPS2592Bx, VIN > 6.75V, IOUT = 10 mA, –40℃ ≤ TJ ≤ 85℃ 5.5 6.1 6.75 TPS2592Bx, VIN > 6.75V, IOUT = 10 mA, –40℃ ≤ TJ ≤ 125℃ 5.25 6.1 6.75 1.37 1.4 1.44 1.32 1.35 1.39 V –100 0 100 nA V EN/UVLO (ENABLE/UVLO INPUT) VENR EN Threshold voltage, rising VENF EN Threshold voltage, falling IEN EN Input leakage current 0 V ≤ VEN ≤ 5V TOFFdly Turn Off delay EN↓ to BFET↓, CBFET = 0 0.4 V µs dV/dT (OUTPUT RAMP CONTROL) TdVdT Output ramp time TPS2592Ax, EN/UVLO → H to OUT = 11.7V, CdVdT = 0 0.7 1 1.3 TPS2592Bx, EN/UVLO → H to OUT = 4.9V, CdVdT = 0 0.28 0.4 0.52 TPS2592Ax, EN/UVLO → H to OUT = 11.7V, CdVdT = 1 nF 12 TPS2592Bx, EN/UVLO → H to OUT = 4.9V, CdVdT = 1 nF 5 IdVdT dV/dT Charging current VdVdT = 0 V RdVdT_disch dV/dT Discharging resistance EN/UVLO = 0 V, IdVdT = 10 mA sinking VdVdTmax dV/dT Max capacitor voltage GAINdVdT dV/dT to OUT gain ΔVdVdT ms 220 50 73 nA 100 V 4.85 V/V Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx Ω 5.5 3 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 125°C, VIN = 12V for TPS2592Ax, VIN = 5V for TPS2592Bx, VEN/UVLO = 2V, RILIM = 100kΩ, CdVdT = OPEN. All voltages referenced to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX RILIM = 45.3 kΩ, VVIN-OUT = 1 V 1.79 2.10 2.42 RILIM = 100 kΩ, VVIN-OUT = 1 V 3.46 3.75 4.03 RILIM = 150 kΩ, VVIN-OUT = 1 V 4.4 5.2 6 UNIT ILIM (CURRENT LIMIT PROGRAMMING) IILIM ILIM Bias current 10 IOL Overload current limit µA A IOL-R-Short RILIM = 0 Ω, Shorted Resistor Current Limit (Single Point Failure Test: UL60950) 0.7 A IOL-R-Open RILIM = OPEN, Open Resistor Current Limit (Single Point Failure Test: UL60950) 0.55 A ISCL Short-circuit current limit RILIM = 45.3 kΩ, VVIN-OUT = 5 V, TPS2592Bx 1.72 2.05 2.38 RILIM = 45.3 kΩ, VVIN-OUT = 12 V, TPS2592Ax 1.66 1.98 2.29 RILIM = 100 kΩ, VVIN-OUT = 5 V, TPS2592Bx 3.14 3.56 3.98 RILIM = 100 kΩ, VVIN-OUT = 12 V, TPS2592Ax 2.90 3.32 3.75 RILIM = 150 kΩ, VVIN-OUT = 5 V, TPS2592Bx 4.12 4.86 5.60 RILIM = 150 kΩ, VVIN-OUT = 12 V, TPS2592Ax 3.75 4.42 5.10 RATIOFASTRIP Fast-Trip comparator level w.r.t. overload current limit IFASTRIP : IOL TFastOffDly Fast-Trip comparator delay IOUT > IFASTRIP VOpenILIM ILIM Open resistor detect threshold VILIM Rising, RILIM = OPEN A 160% 3 µs 3.1 V OUT (PASS FET OUTPUT) TON Turn-on delay RDSon FET ON resistance IOUT-OFF-LKG IOUT-OFF-SINK OUT Bias current in off state EN/UVLO → H to IVIN = 100mA, 1A resistive load at OUT TJ = 25°C 220 21 TJ = 125°C (1) µs 28 33 39 46 VEN/UVLO = 0 V, VOUT = 0 V (Sourcing) –5 0 1 VEN/UVLO = 0V, VOUT = 300 mV (Sinking) 10 15 20 mΩ µA BFET (BLOCKING FET GATE DRIVER) IBFET BFET Charging current VBFETmax BFET Clamp voltage RBFETdisch BFET Discharging resistance TBFET-ON BFET Turn-on duration TBFET-OFF BFET Turn-off duration VBFET = VOUT 2 µA VVIN+6.4 VEN/UVLO = 0 V, IBFET = 100 A 15 26 EN/UVLO → H to VBFET = 12 V, CBFET = 1 nF 4.2 EN/UVLO → H to VBFET = 12 V, CBFET = 10 nF 42 EN/UVLO → L to VBFET = 1 V, CBFET = 1 nF 0.4 EN/UVLO → L to VBFET = 1 V, CBFET = 10 nF 1.4 V 36 Ω ms µs TSD (THERMAL SHUT DOWN) TSHDN TSD Threshold, rising (1) TSHDNhyst TSD Hysteresis (1) Thermal fault: latched or autoretry (1) 4 160 °C 10 °C TPS2592xL LATCHED TPS2592xA AUTORETRY The limits for these parameters are specified based on characterization data, and are not tested during production. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS TJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF, CdVdT = OPEN (unless stated otherwise) 4.35 0.25 0.2 4.25 IVIN-OFF (mA) VUVLO (Rising, Falling) (V) 4.3 4.2 4.15 0.15 0.1 4.1 125 °C 85 °C 25 °C -40 °C 0.05 4.05 4 0 -50 0 50 100 150 Temperature (ƒC) 0 10 15 20 VIN (V) Figure 1. VUVLO vs TEMPERATURE C002 Figure 2. IVIN-OFF vs VIN ACROSS TEMPERATURE 0.6 1 0.5 0.8 0.4 IVIN-ON (mA) IVIN-ON (mA) 5 C001 0.3 0.6 0.4 0.2 125 °C 85 °C 25 °C -40 °C 0.1 0 0 5 10 15 VIN (V) 0 20 0 5 10 15 20 VIN (V) C003 Figure 3. IVIN-ON vs VIN ACROSS TEMPERATURE (TPS2592Ax) 16 125 °C 85 °C 25 °C -40 °C 0.2 C004 Figure 4. IVIN-ON vs VIN ACROSS TEMPERATURE (TPS2592Bx) 6.6 10 mA 100 mA 500 mA 6.4 15.5 VOVC (V) VOVC (v) 6.2 15 6 5.8 5.6 14.5 10 mA 5.4 -50 0 50 100 Temperature (ƒC) 150 -50 0 C005 Figure 5. VOVC vs TEMPERATURE ACROSS IOUT (TPS2592Ax) 50 Temperature (oC) 100 150 Figure 6. VOVC vs TEMPERATURE (TPS2592Bx) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx 5 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF, CdVdT = OPEN (unless stated otherwise) Figure 8. TRANSIENT: OVER-VOLTAGE CLAMP: TPS2592Bx 250 230 230 225 210 220 IdVdT (nA) TON (PS) Figure 7. TRANSIENT: OVER-VOLTAGE CLAMP: TPS2592Ax 190 215 210 170 205 150 -50 0 50 100 -50 150 0 Temperature (oC) 50 100 Temperature (ƒC) Figure 9. TON vs TEMPERATURE 150 C010 Figure 10. IdVdT vs TEMPERATURE 1.07 0.45 0.445 1.06 TdVdT (nA) TdVdT (nA) 0.44 1.05 1.04 0.435 0.43 0.425 1.03 0.42 1.02 0.415 -50 0 50 100 Temperature (ƒC) -50 0 50 100 Temperature (ƒC) C011 Figure 11. TdVdT vs TEMPERATURE (TPS2592Ax) 6 150 150 C012 Figure 12. TdVdT vs TEMPERATURE (TPS2592Bx) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF, CdVdT = OPEN (unless stated otherwise) 150 60 50 100 TdVdT (mS) TdVdT (mS) 40 50 30 20 125 °C 85 °C 25 °C -40 °C 0 0 2 4 6 8 125 °C 85 °C 25 °C -40 °C 10 0 10 CdVdT (nF) 0 2 4 6 8 10 CdVdT (nF) C013 Figure 13. TdVdT vs CdVdT (TPS2592Ax) C014 Figure 14. TdVdT vs CdVdT (TPS2592Bx) 100 1.41 1.39 10 Rising IEN (nA) VEN-VIH VEN-VIL (V) 1.4 1.38 Falling 1.37 125ƒC 85ƒC 25ƒC -40ƒC 1 1.36 1.35 0.1 1.34 -50 0 50 100 150 0 1 Tiemperature (oC) 2 3 4 5 VEN (V) Figure 15. VEN_VIH, VEN_VIL vs TEMPERATURE Figure 16. IEN (Leakage Current) vs VEN Figure 17. TRANSIENT: OUTPUT RAMP (CdVdT = OPEN): TPS2592Ax Figure 18. TRANSIENT: OUTPUT RAMP (CdVdT = 1 nF): TPS2592Ax Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx 7 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF, CdVdT = OPEN (unless stated otherwise) 8 Figure 19. TRANSIENT: OUTPUT RAMP (CdVdT = OPEN): TPS2592Bx Figure 20. Transient Output Ramp (CdVdT = 1 nF, COUT=10 µF, ROUT= 2.5 Ω) : TPS2592Bx Figure 21. TRANSIENT: TURN OFF DELAY (EN ↓) Figure 22. TURN OFF DELAY TO BFET (EN↓) Figure 23. TURN OFF DELAY TO BFET (VIN↓) Figure 24. TRANSIENT: TURN OFF DELAY TO BFET (VIN↓) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF, CdVdT = OPEN (unless stated otherwise) 0.02 45 40 RDSON (m:) VOUT-OFF (V) 0.015 0.01 0.005 35 30 25 0 20 -40 10 60 110 -50 0 Temperature (oC) 50 Figure 25. VOUT-OFF vs TEMPERATURE 150 Figure 26. RDSON vs TEMPERATURE 6 4 RILIM = 150 k: 3.5 5 IVOUT (A) 3 IVOUT (A) 100 Temperature (oC) 4 3 RILIM = 100 k: 2.5 2 125ƒC 85ƒC 25ƒC -40ƒC 2 1 0 0.5 1 1.5 125ƒC 85ƒC 25ƒC -40ƒC 1.5 1 2 0 0.5 VVIN-VOUT (V) 1 1.5 2 VVIN-VOUT (V) Figure 27. IOUT vs VVIN-OUT ACROSS TEMPERATURE (150kΩ) Figure 28. IOUT vs VVIN-OUT ACROSS TEMPERATURE (100kΩ) 2 2.2 0 IVOUT (A) 1.8 IOL, ISC (% Normalized) 2 RILIM = 45.3 k: 1.6 1.4 125ƒC 85ƒC 25ƒC -40ƒC 1.2 1 0 0.5 1 1.5 -2 -4 -6 IOL-150k ISC-150K-92B_ ISC-150K-92A_ -8 -10 -12 -14 -16 2 -50 0 50 100 150 Temperature (oC) VVIN-VOUT (V) Figure 29. IOUT vs VVIN-OUT ACROSS TEMPERATURE (45.3kΩ) Figure 30. IOL, ISC vs TEMPERATURE (150kΩ) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx 9 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 2 1 0 0 IOL, ISC (% Normalized) IOL, ISC (% Normalized) TJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF, CdVdT = OPEN (unless stated otherwise) -2 -4 IOL-100K ISC-100K-92B_ ISC-100K-92A_ -6 -8 -10 -1 -2 IOL-45.3k ISC-45.3K-92B_ ISC-45.3K-92A_ -3 -4 -5 -12 -6 -50 0 50 100 150 -50 0 Temperature (oC) Figure 31. IOL, ISC vs TEMPERATURE (100kΩ) 100 150 Figure 32. IOL, ISC vs TEMPERATURE (45.3kΩ) 0.9 0.58 0.85 0.57 0.8 0.56 IOL-R-OPEN (A) IOL-R-SHORT (A) 50 Temperature (oC) 0.75 0.7 0.65 0.55 0.54 0.53 0.6 0.52 0.55 0.51 0.5 0.5 -50 0 50 100 150 -50 Temperature (oC) 0 50 100 150 Temperature (oC) Figure 33. IOL-R-Short vs TEMPERATURE (RILIM = 0) Figure 34. IOL-R-Open vs TEMPERATURE (RILIM = OPEN) ILIM Open Detect Threshold (V) 3.1 3.09 3.08 3.07 3.06 3.05 -50 0 50 100 150 Temperature (oC) Figure 35. VOpenILIM vs TEMPERATURE 10 Figure 36. TRANSIENT: OUTPUT SHORT CIRCUIT Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) TJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF, CdVdT = OPEN (unless stated otherwise) Figure 37. SHORT CIRCUIT (Zoom): FAST-TRIP COMPARATOR Figure 38. TRANSIENT: RECOVERY FROM SHORT CIRCUIT Figure 39. TRANSIENT: WAKE UP TO SHORT CIRCUIT Figure 40. TRANSIENT: OVERLOAD CURRENT LIMIT: (ILOAD stepped from 50% to 120%, back to 50%) Figure 41. TRANSIENT: THERMAL FAULT AUTO-RETRY (TPS2592xA) Figure 42. TRANSIENT: THERMAL FAULT LATCHED (TPS2592xL) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx 11 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM OUT VIN 3, 4, 5 + EN/ UVLO 28mW Charge Pump + 2 Current Sense UVLO 4.3V 4.08V 6, 7, 8 2mA EN 1.4V 1.35V BFET Over Voltage 9 SWEN 6V SWEN Thermal ShutDown GATE CONTROL 22W TSD 6V VIN 220nA 10mA + ILIMIT dV/dT ILIM 4.8x 1 + + 70pF GND 80W EP 10 SWEN Fast Trip Comp 1.6*ILIMIT DRC PACKAGE (TOP VIEW) dV/dT 1 EN/UVLO VIN VIN VIN 5 GND 10 ILIM BFET OUT OUT 6 OUT PIN DESCRIPTIONS PIN NAME DESCRIPTION NO. SUPPLY PINS VIN 3-5 GND Power Pad Input Supply Voltage GND CONTROL PINS dV/dT 1 Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on. 2 This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal pass MOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET. EN/UVLO As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider. BFET 9 Connect this pin to the gate of a blocking NFET. See detailed pin description and application note in this datasheet. ILIM 10 A resistor from this pin to GND will set the overload and short circuit limit. 6-8 Output of the device LOAD PINS OUT 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 DEVICE OPERATION The TPS2592xx is a hot-swap controller with integrated power switch that is used to manage current/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VIN bus. When VIN exceeds the undervoltage threshold (VUVLO), the device samples the EN/UVLO pin. A high level on this pin will enable the internal MOSFET and also start charging the gate of external blocking FET (if connected) via the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected) will start conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (i.e., below VENF), the internal MOSFET is turned off and BFET pin is discharged, thereby blocking the flow of current from VIN to OUT. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dT pin and GND. Having successfully completed its start-up sequence, the device now actively monitors its load current and input voltage, ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safely clamped to VOVC level at the output. This keeps the output device safe from harmful voltage and current transients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds TSHDN , typically 160°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting the load from the supply. In the TPS2592xL, the output will remain disconnected (MOSFET open) until power to device is recycled or EN/UVLO is toggled (pulled low and then high). The TPS2592xA device will remain off during a cooling period until device temperature falls below TSHDN – 10°C, after which it will attempt to restart. This ON and OFF cycle will continue until fault is cleared. DETAILED PIN DESCRIPTION GND: This is the most negative voltage in the circuit and is used as a reference for all voltage measurements unless otherwise specified. VIN: Input voltage to the TPS2592xx. A ceramic bypass capacitor close to the device from VIN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 4.5V – 13.8V for TPS2592Ax and 4.5V – 5.5V for TPS2592Bx. The device can continuously sustain a voltage of 20V on VIN pin. However, above the recommended maximum bus voltage, the device will be in over-voltage protection (OVP) mode, limiting the output voltage to VOVC. The power dissipation in OVP mode is PD_OVP = (VVIN - VOVC)*IOUT, which can potentially heat up the device and cause thermal shutdown. dV/dT: Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. This pin can be left floating to obtain a predetermined slew rate (minimum TdVdT) on the output. Equation governing slew rate at start-up is shown below: æ dVOUT ö ç dT ÷ ø IdVdT = (CEXT + CINT )´ è GAINdVdT (1) Where: IdVdT = 220 nA (TYP) CINT = 70pF (TYP) GAINdVdT = 4.85 dVOUT = Desired output slew rate dT The total ramp time (TdVdT) for 0 to VIN can be calculated using the following equation: TdVdT =1 06 ´ VIN ´ (CEXT + 70 pF ) (2) For details on how to select an appropriate charging time/rate, refer to the applications section: "INRUSH CURRENT AND POWER DISSIPATION DURING START-UP". BFET: Connect this pin to an external NFET that can be used to disconnect input supply from rest of the system in the event of power failure at VIN. BFET pin is controlled by either UVLO event or EN/UVLO (see table below). BFET can source charging current of 2µA (TYP) and sink (discharge) current from the gate of the external FET via a 26Ω internal discharge resistor to initiate fast turn-off, typically <1 µs. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx 13 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com EN/UVLO > VENR VIN>VUVR BFET Mode H H Charge X L Discharge L X Discharge EN/UVLO: As an input pin, it controls both the ON/OFF state of the internal MOSFET and that of the external blocking FET. In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET. A low on this pin will turn off the internal MOSFET and pull the gate of the external FET to GND via the built-in discharge resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pin is also used to clear a thermal shutdown latch in the TPS2592xL by toggling this pin (H→L). The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1us typical) for quick detection of power failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection on EN/UVLO helps in quick turn-off of the BFET driver, thereby stopping the flow of reverse current (see typical application diagram, Figure 47). For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND ILIM: The device continuously monitors the load current and keeps it limited to the value programmed by RILIM. After start-up event and during normal operation, current limit is set to IOL (over-load current limit). ( IOL = 0.7 + 3 ´ 10-5 ´ RILIM ) (3) When power dissipation in the internal MOSFET [PD = (VVIN -VOUT) × IOUT] exceeds 10W, there is a 2% – 12% thermal foldback in the current limit value so that IOL drops to ISC. In each of the two modes, MOSFET gate voltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shuts down due to over temperature. 0 Foldback (ISC - IOL)/IOL (%) -2 -4 -6 -8 -10 -12 -14 0 10 20 30 Power (W) 40 50 60 Figure 43. Thermal Foldback in Current Limit During a transient short circuit event, the current through the device increases very rapidly. The current-limit amplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS2592 incorporates a fast-trip comparator, which shuts down the pass device very quickly when IOUT > IFASTRIP, and terminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed overload current limit (IFASTRIP = 1.6 x IOL). After the transient short-circuit peak current has been terminated by the fast-trip comparator, the current limit amplifier smoothly regulates the output current to IOL (see figure below). 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 Figure 44. Fast-Trip Current Figure 45. Fast-Trip and Current Limit Amplifier Response for Short Circuit Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx 15 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com TYPICAL APPLICATIONS Figure 46. Simple e-Fuse (Current-Limiter): Application with Output Ramp-Rate Control Figure 47. Reverse Current Protection (e.g., SSD) Application with Blocking FET CHOLD-UP (TPS2592 UVLO is used as power fail comparator) Figure 48. Reverse Current Protection Application with External Blocking Controller (TPS2413 is used as reverse current comparator) 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 APPLICATION INFORMATION INRUSH CURRENT AND POWER DISSIPATION DURING START-UP A successful design needs to keep the junction temperature of TPS2592 well below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up. During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and the power dissipated decreases as well. Typical ramp-up of output voltage VOUT with inrush current limit is shown in Figure 49 and variation of power dissipation with ramp-up time is plotted in Figure 50. The average power dissipated in the device during start-up is equal to area of triangular plot as highlighted. Figure 49. Start-Up Waveform Figure 50. PDISS During Start-Up For the TPS2592, the inrush current is determined as: I = C´ V dv => IINRUSH = COUT ´ VIN dt Tdvdt (4) Power dissipation during start-up will be: PINRUSH = 0.5 ´ VVIN ´ IINRUSH (5) The above calculation assumes that load does not draw any current until the output voltage has reached its final value. If the load draws current during the turn-on sequence, there will be additional power dissipated during the startup phase. Considering a resistive load RL, load current ramps up proportionally with increase in output voltage during Tdvdt time. Typical ramp-up of output voltage VOUT and Load current is shown in Figure 51 and variation of power dissipation with ramp-up time is plotted in Figure 52. The additional power dissipation during start-up phase is represented and calculated as follows: æ t ö VDS (t) = VVIN ´ ç 1 ÷ Tdvdt ø è (6) æV ö t ILOAD (t ) = ç VIN ÷ ´ è RL ø Tdvdt (7) Average energy loss due in FET during charging time due to resistive load is given by: Tdvdt WTdvdt = ò VVIN ´ (1 - æV t ö ) ´ ç VIN ´ ÷ dt Tdvdt è RL Tdvdt ø t (8) 0 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx 17 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com Figure 51. Start-up Waveform with Load (2.5W) Figure 52. PDISS During Due to Load Current Linearizing the parabolic equation and representing as triangle, the average power loss is: 2 æ 1ö V PDISS _ LOAD = ç ÷ ´ VIN è 6 ø RL (9) Total power dissipated in the device during startup is: PSTARTUP = PINRUSH + PDISS _ LOAD (10) Total current during startup is given by: ISTARTUP = IINRUSH + ILOAD (t) (11) If ISTARTUP > ILIM, the device limits the current to ILIM and the minimum charging time is determined by: V Tdvdt _ min = COUT ´ VIN ILIM (12) Power dissipation for a selected start-up time should not exceed the limits shown in below plots as shaded area. Typical curves for no load and load are shown in Figure 53 and Figure 54. Figure 53. IINRUSH SOA Variation with COUT and Tdvdt (NO Load) 18 Figure 54. IINRUSH SOA Variation with COUT and Tdvdt (with Load) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx TPS2592Ax TPS2592Bx www.ti.com SLVSC11A – JUNE 2013 – REVISED JUNE 2013 Example: VVIN = 12V, COUT = 470uF, and Load: RL = 12Ω As a first choice, let CEXT = CdVdT = 3.3nF: Tdvdt =1 06 ´ 12 ´ (100pF + 70pF ) = 2.04 ms ( (13) ) 12 æ ö = 2.764 A IINRUSH = 470 ´ 10-6 ´ ç -3 ÷ è 2.04 ´ 10 ø PINRUSH = 0.5 ´ 12 ´ 2.764 = 16.584 W (14) (15) æ 1 ö æ (12 ´ 12 ) ö PDISS _ LOAD = ç ÷ ´ ç ÷ = 2.00 W ÷ 3 è 6 ø çè ø (16) PSTARTUP = (16.584 +2.00) = 18.84 W (17) The power dissipated is well above the shaded area of power dissipation graph; to have safe operating power area, increase the capacitance As a second choice, let CEXT = CdVdT = 0.47 nF: Tdvdt =1 06 ´ 12 ´ (470pF + 70pF ) = 6.48 ms ( ) 12 æ IINRUSH = 470 ´ 10( -6) ´ ç è 6.48 ´ 10( -3) PINRUSH = 0.5 ´ 12 ´ 0.87 = 5.22 W (18) ö ÷ = 0.87A ø (19) (20) æ 1 ö æ (12 ´ 12 ) ö PDISS _ LOAD = ç ÷ ´ ç ÷ = 2.00 W ÷ è 6 ø çè 12 ø (21) PSTARTUP = (5.22 +2.00) = 7.22 W (22) The power dissipated is well below the shaded area of the power dissipation graph. The following table illustrates the acceptability for different CdVdT capacitances. Capacitance CdVdT (nF) 0.10 0.47 3.30 Charging Time Tdvdt (ms) 2.0 6.5 40.5 325 18.84 7.22 2.84 2.10 Not OK OK OK Not OK Power Dissipation (W) Limits 27.0 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx 19 TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013 – REVISED JUNE 2013 www.ti.com REVISION HISTORY Changes from Original (June 2013) to Revision A • 20 Page Changed from Product Preview to Production Data ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPS2592Ax TPS2592Bx PACKAGE OPTION ADDENDUM www.ti.com 28-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPS2592AADRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2592AA TPS2592AADRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2592AA TPS2592BLDRCR ACTIVE SON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2592BL TPS2592BLDRCT ACTIVE SON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2592BL (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS2592AADRCR SON DRC 10 TPS2592AADRCT SON DRC TPS2592BLDRCR SON DRC TPS2592BLDRCT SON DRC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2592AADRCR SON DRC 10 3000 367.0 367.0 35.0 TPS2592AADRCT SON DRC 10 250 210.0 185.0 35.0 TPS2592BLDRCR SON DRC 10 3000 367.0 367.0 35.0 TPS2592BLDRCT SON DRC 10 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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