TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 www.ti.com SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 200-mA LOW-IQ LOW-DROPOUT REGULATOR FOR PORTABLE DEVICES Check for Samples: TLV70012A-Q1, TLV70025-Q1, TLV70030-Q1, TLV70033-Q1 FEATURES APPLICATIONS 1 • • • • • • • • • • Automotive Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B 2% Accuracy Low IQ: 31 μA Fixed Output Voltage of 3.3 V High PSRR: 68 dB at 1 kHz Stable With Effective Capacitance of 0.1 μF Thermal Shutdown and Overcurrent Protection Latch-Up Performance Meets 100 mA Per AEC-Q100, Level I Available in the SOT23-5 (DDC) and SC70-5 (DCK) Packages TLV700xx-Q1 DDC SOT23-5 PACKAGE (TOP VIEW) IN 1 GND 2 EN 3 5 OUT 4 N/C (1) TLV700xx-Q1 DCK SC70-5 PACKAGE (TOP VIEW) IN 1 GND 2 EN 3 5 OUT 4 N/C (1) DESCRIPTION The TLV700xx-Q1 family of low-dropout (LDO) linear regulators are low-quiescent-current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision band-gap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. All device versions have thermal shutdown and current limit for safety. Furthermore, these devices are stable with an effective output capacitance of only 0.1 μF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices regulate to specified accuracy with no output load. The TLV700xx-Q1 LDOs are available in the SOT23-5 (DDC) and the SC70-5 (DCK) packages. VIN IN OUT CIN COUT VOUT 1 µF Ceramic TLV700xx-Q1 On Off EN GND Typical Application Circuit (Fixed-Voltage Versions) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2012, Texas Instruments Incorporated TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C SOT23 – DDC Reel of 3000 –40°C to 125°C SC70-5 – DCK Reel of 3000 (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING TLV70033QDDCRQ1 OFL TLV70025QDDCRQ1 QVC TLV70012QDCKRQ1 SDX TLV70030QDCKRQ1 SDW For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS (1) At TA = –40°C to 125°C (unless otherwise noted). All voltages are with respect to GND. VIN Input voltage range –0.3 V to 6 V VEN Enable voltage range –0.3 V to 6 V VOUT Output voltage range IOUT Maximum output current –0.3 V to 6 V Internally limited Output short-circuit duration Indefinite TA Operating ambient temperature range –55°C to 150°C Tstg Storage temperature range –55°C to 150°C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. THERMAL INFORMATION THERMAL METRIC (1) TLV700xx-Q1 TLV700xx-Q1 DCK (5 PINS) DDC (5 PINS) θJA Junction-to-ambient thermal resistance 307.6 262.8 θJCtop Junction-to-case (top) thermal resistance 79.1 68.2 θJB Junction-to-board thermal resistance 93.7 81.6 ψJT Junction-to-top characterization parameter 1.3 101 ψJB Junction-to-board characterization parameter 92.8 80.9 θJCbot Junction-to-case (bottom) thermal resistance n/a n/a (1) 2 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 www.ti.com SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS VIN = VOUT(TYP) + 0.3 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to 125°C (unless otherwise noted). Typical values are at TA = 25°C. space TLV700xx-Q1 PARAMETER TEST CONDITIONS VIN Input voltage range VOUT DC output accuracy –40°C ≤ TA ≤ 125°C ΔVO/ΔVIN Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA ΔVO/ΔIOUT Load regulation TYP 2 MAX UNIT 5.5 V VOUT ≥ 1 V –2 2 % VOUT < 1 V –20 20 mV 5 mV 1 0 mA ≤ IOUT ≤ 200 mA, TLV70025Q1,TLV70030-Q1,TLV70033-Q1 15 0 mA ≤ IOUT ≤ 200 mA, TLV70012A-Q1 20 VDO Dropout voltage (1) VIN = 0.98 × VOUT(NOM), IOUT = 200 mA ICL Output current limit VOUT = 0.9 × VOUT(NOM) 220 IOUT = 0 mA mV 175 250 mV 350 550 mA 31 55 μA IGND Ground pin current ISHDN Ground pin current (shutdown) VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V Power-supply rejection ratio VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz 68 dB Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA 48 μVRMS 100 μs PSRR VN tSTR Startup time (2) IOUT = 200 mA, VIN = VOUT + 0.5 V μA 270 1 COUT = 1 μF, IOUT = 200 mA μA 2 VEN(HI) Enable pin high (enabled) 0.9 VIN VEN(LO) Enable pin low (disabled) 0 0.4 V 0.5 μA IEN UVLO (1) (2) MIN V Enable pin current VEN = 5.5 V , IOUT = 10 μA Undervoltage lockout VIN rising 1.9 V Shutdown, temperature increasing 160 °C Reset, temperature decreasing 140 TSD Thermal shutdown temperature TA Operating ambient temperature 0.04 –40 °C 125 °C VDO is measured for devices with VOUT(NOM) ≥ 2.35 V. Startup time = time from EN assertion to 0.98 × VOUT(NOM). Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 3 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM IN OUT Current Limit Thermal Shutdown UVLO Bandgap EN LOGIC TLV700xx-Q1 Series GND PIN CONFIGURATIONS TLV700xx-Q1 DDC SOT23-5 PACKAGE (TOP VIEW) IN 1 GND 2 EN 3 TLV700xx-Q1 DCK SC70-5 PACKAGE (TOP VIEW) 5 OUT 4 N/C IN 1 GND 2 EN 3 5 OUT 4 N/C (1) (1) PIN DESCRIPTIONS NAME 4 NO. DESCRIPTION IN 1 Input pin. A small 1-μF ceramic capacitor is recommended from this pin to ground to assure stability and good transient performance. See Input and Output Capacitor Requirements in the Application Information section for more details. GND 2 Ground pin EN 3 Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode and reduces operating current to 1 μA, nominal. NC 4 No connection. This pin can be tied to ground to improve thermal dissipation. OUT 5 Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 www.ti.com SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless otherwise noted). Typical values are at TJ = 25°C. TLV70018 LINE REGULATION 1.90 TLV70018 LINE REGULATION 1.90 IOUT = 10 mA 1.88 1.88 1.86 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 Output Voltage (V) Output Voltage (V) 1.86 IOUT = 200 mA 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 1.70 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 2.1 2.6 3.1 Input Voltage (V) TLV70048 DROPOUT VOLTAGE vs INPUT VOLTAGE 1.84 1.82 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 Dropout Voltage (mV) Output Voltage (V) 1.86 60 80 5.6 100 120 140 160 IOUT = 200 mA 200 150 100 +125°C +85°C +25°C -40°C 50 0 2.25 1.70 180 200 2.75 3.25 3.75 4.75 4.25 Input Voltage (V) Output Current (mA) Figure 3. Figure 4. TLV70048 DROPOUT VOLTAGE vs OUTPUT CURRENT TLV70018 OUTPUT VOLTAGE vs TEMPERATURE 180 1.90 160 1.88 140 1.86 120 100 80 60 +125°C +85°C +25°C -40°C 40 20 Output Voltage (V) Dropout Voltage (V) 5.1 TLV70018 LOAD REGULATION 250 40 4.6 Figure 2. 1.88 20 4.1 Figure 1. 1.90 0 3.6 Input Voltage (V) 1.84 1.82 1.80 1.78 1.76 IOUT = 200 mA IOUT = 10 mA IOUT = 150 mA 1.74 1.72 1.70 0 0 30 60 90 120 150 Output Current (mA) Figure 5. Copyright © 2010–2012, Texas Instruments Incorporated 180 210 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 6. Submit Documentation Feedback Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 5 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless otherwise noted). Typical values are at TJ = 25°C. TLV70018 GROUND PIN CURRENT vs INPUT VOLTAGE 50 300 40 35 30 25 20 15 +125°C +85°C +25°C -40°C 10 5 Ground Pin Current (mA) IOUT = 0 mA 45 Ground Pin Current (mA) TLV70018 GROUND PIN CURRENT vs LOAD 250 200 150 100 +125°C +85°C +25°C -40°C 50 0 0 2.1 2.6 3.1 3.6 4.1 4.6 5.1 0 5.6 20 40 60 Figure 8. TLV70018 GROUND PIN CURRENT vs TEMPERATURE TLV70018 SHUTDOWN CURRENT vs INPUT VOLTAGE 40 2.0 35 1.8 30 25 20 15 10 5 1.6 1.4 1.2 1.0 0.8 0.6 +125°C +85°C +25°C 0.4 0.2 IOUT = 0 mA 0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6 Input Voltage (V) Figure 9. Figure 10. TLV70018 CURRENT LIMIT vs INPUT VOLTAGE TLV70018 POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 440 100 430 90 420 80 IOUT = 10 mA IOUT = 150 mA 70 410 PSRR (dB) Current Limit (mA) Temperature (°C) 400 390 380 60 50 40 30 370 20 360 TA = +25°C 350 2.0 2.5 3.0 3.5 Input Voltage (V) Figure 11. 6 100 120 140 160 180 200 Figure 7. Shutdown Current (mA) Ground Pin Current (mA) 80 Output Current (mA) Input Voltage (V) Submit Documentation Feedback 4.0 4..5 10 VIN - VOUT = 0.5 V 0 10 100 1k 10 k 100 k 1M 10 M Frequency (Hz) Figure 12. Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 www.ti.com SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless otherwise noted). Typical values are at TJ = 25°C. TLV70018 OUTPUT SPECTRAL NOISE DENSITY vs OUTPUT VOLTAGE TLV70018 POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE 1 kHz 70 60 PSRR (dB) Output Spectral Noise Density (mV/ÖHz) 80 10 kHz 50 100 kHz 40 30 20 10 0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 10 1 0.1 0.01 IOUT = 10 mA CIN = COUT = 1 mF 0 10 2.8 100 100 k TLV70018 LOAD TRANSIENT RESPONSE TLV70018 LOAD TRANSIENT RESPONSE IOUT 0 mA 5 mV/div VOUT 10 mA 0 mA IOUT VOUT VIN = 2.3 V 10 ms/div 10 ms/div Figure 15. Figure 16. TLV70018 LOAD TRANSIENT RESPONSE TLV70018 LINE TRANSIENT RESPONSE Slew Rate = 1 V/ms tR = tF = 1 ms IOUT 0 mA 1 V/div 50 mA VIN 2.9 V 2.3 V 5 mV/div 50 mA/div 10 M tR = tF = 1 ms 200 mA VIN = 2.1 V 20 mV/div 1M Figure 14. 20 mA/div 100 mA/div 10 k Figure 13. tR = tF = 1 ms 50 mV/div 1k Frequency (Hz) Input Voltage (V) VOUT VIN = 2.3 V VOUT IOUT = 200 mA 10 ms/div 1 ms/div Figure 17. Figure 18. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 7 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF (unless otherwise noted). Typical values are at TJ = 25°C. VIN TLV70018 LINE TRANSIENT RESPONSE Slew Rate = 1 V/ms Slew Rate = 1 V/ms 2.7 V 1 V/div 1 V/div TLV70018 LINE TRANSIENT RESPONSE 2.3 V VIN 5.5 V 10 mV/div 5 mV/div 2.1 V VOUT VOUT IOUT = 200 mA IOUT = 1 mA 1 ms/div 1 ms/div Figure 19. Figure 20. TLV70018 VIN RAMP UP, RAMP DOWN RESPONSE IOUT = 1 mA 1 V/div VIN VOUT 200 ms/div Figure 21. 8 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 www.ti.com SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 APPLICATION INFORMATION The TLV700xx-Q1 belongs to a new family of next-generation value LDO regulators. It consumes low quiescent current and delivers excellent line and load transient performance. These characteristics, combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this device ideal for RF portable applications. This family of regulators offers subband-gap output voltages down to 0.7 V, current limit, and thermal protection, and is specified from –40°C to 125°C. Input and Output Capacitor Requirements 1.0-μF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. However, the TLV700xx-Q1 is designed to be stable with an effective capacitance of 0.1 μF or larger at the output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of cheaper dielectrics, this capability of being stable with 0.1-μF effective capacitance also enables the use of smaller-footprint capacitors that have higher derating in size- and space-constrained applications. Note that using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions would be less than 0.1 μF. Maximum ESR should be less than 200 mΩ. Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1μF, low-ESR capacitor across the IN pin and GND in of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability. Board Layout Recommendations to Improve PSRR and Noise Performance Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High-ESR capacitors may degrade PSRR performance. Internal Current Limit The TLV700xx-Q1 internal current limit helps to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the internal thermal-shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section for more details. The PMOS pass element in the TLV700xx-Q1 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. Shutdown The enable pin (EN) is active-high and is compatible with standard and low-voltage TTL-CMOS levels. When shutdown capability is not required, EN can be connected to the IN pin. Dropout Voltage The TLV700xx-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the rDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves as a resistor in dropout. Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 9 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 www.ti.com As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 13 in the Typical Characteristics section. Transient Response As with any regulator, increasing the size of the output capacitor reduces over-/undershoot magnitude but increases the duration of the transient response. Undervoltage Lockout (UVLO) The TLV700xx-Q1 uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating properly. Thermal Information Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TLV700xx-Q1 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV700xx-Q1 into thermal shutdown degrades device reliability. 10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 TLV70012A-Q1, TLV70025-Q1 TLV70030-Q1, TLV70033-Q1 www.ti.com SLVSA61D – FEBRUARY 2010 – REVISED AUGUST 2012 REVISION HISTORY Changes from Revision C (June 2012) to Revision D • Page Changed mF to µF in Typical Application Circuit diagram ................................................................................................... 1 Changes from Revision B (May, 2012) to Revision C • Page Device went from Preview to Production. ............................................................................................................................. 1 Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TLV70012A-Q1 TLV70025-Q1 TLV70030-Q1 TLV70033-Q1 11 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TLV70012QDCKRQ1 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70025QDDCRQ1 ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TLV70030QDCKRQ1 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70033QDDCRQ1 ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF TLV70025-Q1, TLV70030-Q1, TLV70033-Q1 : Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2012 • Catalog: TLV70025, TLV70030, TLV70033 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV70012QDCKRQ1 SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70025QDDCRQ1 SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70033QDDCRQ1 SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70012QDCKRQ1 SC70 DCK 5 3000 180.0 180.0 18.0 TLV70025QDDCRQ1 SOT DDC 5 3000 195.0 200.0 45.0 TLV70033QDDCRQ1 SOT DDC 5 3000 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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