TI LMZ14203EXTTZ

LMZ14203EXT
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SNVS666E – JUNE 2010 – REVISED APRIL 2013
LMZ14203EXT 3A SIMPLE SWITCHER® Power Module with 42V Maximum Input Voltage
for Military and Rugged Applications
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FEATURES
1
•
•
•
•
2
•
•
•
•
•
•
– 55°C to 125°C Junction Temperature Range
Integrated Shielded Inductor
Simple PCB Layout
Flexible Startup Sequencing Using External
Soft-Start and Precision Enable
Protection Against Inrush Currents and Faults
such as Input UVLO and Output Short Circuit
Single Exposed Pad and Standard Pinout for
Easy Mounting and Manufacturing
Fast Transient Response for Powering FPGAs
and ASICs
Low output Voltage Ripple
Pin-to-pin Compatible Family:
– LMZ14203EXT/2EXT/1EXT
(42V Max 3A, 2A, 1A)
– LMZ12003/2/1 (20V Max 3A, 2A, 1A)
– LMZ14203/2/1 (42V Max 3A, 2A, 1A)
Fully Enabled for Webench® Power Designer
DESCRIPTION
The LMZ14203EXT SIMPLE SWITCHER power
module is an easy-to-use step-down DC-DC solution
capable of driving up to 3A load with exceptional
power conversion efficiency, line and load regulation,
and output accuracy. The LMZ14203EXT is available
in an innovative package that enhances thermal
performance and allows for hand or machine
soldering.
The LMZ14203EXT can accept an input voltage rail
between 6V and 42V and deliver an adjustable and
highly accurate output voltage as low as 0.8V. The
LMZ14203EXT only requires three external resistors
and four external capacitors to complete the power
solution. The LMZ14203EXT is a reliable and robust
design with the following protection features: thermal
shutdown, input under-voltage lockout, output overvoltage protection, short-circuit protection, output
current limit, and allows startup into a pre-biased
output. A single resistor adjusts the switching
frequency up to 1 MHz.
ELECTRICAL SPECIFICATIONS
APPLICATIONS
•
•
•
•
Point of Load Conversions from 12V and 24V
Input Rail
Time Critical Projects
Space Constrained / High Thermal
Requirement Applications
Negative Output Voltage Applications (See AN2027 SNVA425)
•
•
•
•
•
18W Maximum Total Output Power
Up to 3A Output Current
Input Voltage Range 6V to 42V
Output Voltage Range 0.8V to 6V
Efficiency up to 90%
PERFORMANCE BENEFITS
•
•
•
Low Radiated Emissions / High Radiated
Immunity
Passes vibration Standard MIL-STD-883
Method 2007.2 Condition A JESD22–B103B
Condition 1
Passes Drop Standard MIL-STD-883 Method
2002.3 Condition B JESD22–B110 Condition B
Figure 1. Easy To Use 7 Pin Package
PFM 7 Pin Package
10.16 x 13.77 x 4.57 mm (0.4 x 0.542 x 0.18 in)
θJA = 20°C/W, θJC = 1.9°C/W
RoHS Compliant
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
LMZ14203EXT
SNVS666E – JUNE 2010 – REVISED APRIL 2013
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System Performance
Efficiency VIN = 24V VOUT = 5.0V
100
95
EFFICIENCY (%)
90
85
80
75
70
65
60
55
25°C
50
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT(A)
Thermal Derating Curve
VIN = 24V, VOUT = 5.0V
3.5
OUTPUT CURRENT (A)
3
2.5
2
1.5
1
0.5
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Radiated Emissions (EN 55022 Class B)
from Evaluation Board
2
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Simplified Application Schematic
VOUT
FB
SS
GND
EN
VIN
VIN
RON
LMZ14203EXT
VOUT @ 3A
CFF
RON
RFBT
Enable
CIN
CSS
COUT
RFBB
Connection Diagram
Exposed Pad
Connect to GND
7
6
5
4
3
2
1
VOUT
FB
SS
GND
EN
RON
VIN
Figure 2. Top View
7-Lead PFM
PIN DESCRIPTIONS
Pin
Name
Description
1
VIN
Supply input — Nominal operating range is 6V to 42V . A small amount of internal capacitance is contained within the
package assembly. Additional external input capacitance is required between this pin and exposed pad.
2
RON
On Time Resistor — An external resistor from VIN to this pin sets the on-time of the application. Typical values range from
25k to 124k ohms.
3
EN
4
GND
5
SS
Soft-Start — An internal 8 µA current source charges an external capacitor to produce the soft-start function. This node is
discharged at 200 µA during disable, over-current, thermal shutdown and internal UVLO conditions.
6
FB
Feedback — Internally connected to the regulation, over-voltage, and short-circuit comparators. The regulation reference
point is 0.8V at this input pin. Connected the feedback resistor divider between the output and ground to set the output
voltage.
7
VOUT
EP
EP
Enable — Input to the precision enable comparator. Rising threshold is 1.18V nominal; 90 mV hysteresis nominal.
Maximum recommended input level is 6.5V.
Ground — Reference point for all stated voltages. Must be externally connected to EP.
Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and exposed pad.
Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be
electrically connected to pin 4 external to the package.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1)
VIN, RON to GND
-0.3V to 43.5V
EN, FB, SS to GND
-0.3V to 7V
Junction Temperature
150°C
Storage Temperature Range
-65°C to 150°C
ESD Susceptibility (2)
± 2 kV
Peak Reflow Case Temperature (30 sec)
245°C
For soldering specifications, refer to the following document: www.ti.com/lit/snoa549c
(1)
(2)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.
Operating Ratings (1)
VIN
6V to 42V
EN
0V to 6.5V
−55°C to 125°C
Operation Junction Temperature
(1)
4
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
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Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -55°C
to +125°C. Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 24V, Vout = 3.3V
Symbol
Parameter
SYSTEM PARAMETERS
Conditions
Min
Typ
Max
1.1
1.18
1.26
(1)
(2)
(1)
Units
(3)
Enable Control
VEN
VEN-HYS
EN threshold trip point
VEN rising
EN threshold hysteresis
VEN falling
SS source current
VSS = 0V
90
V
mV
Soft-Start
ISS
ISS-DIS
4.9
SS discharge current
8
11
-200
µA
µA
Current Limit
ICL
Current limit threshold
d.c. average
VIN= 12V to 24V
3.15
4.2
5.3
A
ON/OFF Timer
tON-MIN
tOFF
ON timer minimum pulse width
150
ns
OFF timer pulse width
260
ns
Regulation and Over-Voltage Comparator
VFB
VFB-OV
In-regulation feedback voltage
VSS >+ 0.8V
TJ = -55°C to 125°C
IO = 3A
0.784
0.804
0.825
V
VSS >+ 0.8V
TJ = 25°C
IO = 10 mA
0.786
0.802
0.818
V
Feedback over-voltage protection
threshold
0.92
V
5
nA
IFB
Feedback input bias current
IQ
Non Switching Input Current
VFB= 0.86V
1
mA
ISD
Shut Down Quiescent Current
VEN= 0V
25
μA
Thermal Shutdown
Rising
165
°C
Thermal shutdown hysteresis
Falling
15
°C
Junction to Ambient (4)
4 layer JEDEC Printed Circuit Board,
100 vias, No air flow
19.3
°C/W
2 layer JEDEC Printed Circuit Board, No
air flow
21.5
°C/W
No air flow
1.9
°C/W
Thermal Characteristics
TSD
TSD-HYST
θJA
θJC
Junction to Case
PERFORMANCE PARAMETERS
ΔVO
(1)
(2)
(3)
(4)
Output Voltage Ripple
8
mV
PP
ΔVO/ΔVIN
Line Regulation
VIN = 12V to 42V, IO= 3A
.01
%
ΔVO/IOUT
Load Regulation
VIN = 24V
1.5
mV/A
η
Efficiency
VIN = 24V VO = 3.3V IO = 1A
92
%
η
Efficiency
VIN = 24V VO = 3.3V IO = 3A
85
%
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric normal.
EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 SNVA422 and layout for information on device under test.
θJA measured on a 1.705” x 3.0” four layer board, with one ounce copper, thirty five 12 mil thermal vias, no air flow, and 1W power
dissipation. Refer to PCB layout diagrams
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Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 100uF X7R Ceramic;
Tambient = 25 C for efficiency curves and waveforms.
Efficiency 6V Input @ 25°C
Dissipation 6V Input @ 25°C
2.5
100
95
2
3.3
2.5
1.8
1.5
1.2
85
80
75
DISSIPATION (W)
EFFICIENCY (%)
90
70
0.8
65
60
3.3
2.5
1.8
1.5
1
1.5
1.2
0.8
0.5
25°C
55
25°C
50
0
0.5
1.5
1
2
2.5
0
3
0
0.5
OUTPUT CURRENT (A)
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
Figure 3.
Figure 4.
Efficiency 12V Input @ 25°C
Dissipation 12V Input @ 25°C
100
2.5
95
2
5.0
3.3
2.5
85
80
DISSIPATION (W)
EFFICIENCY (%)
90
1.8
1.5
1.2
75
70
0.8
65
60
5.0
3.3
2.5
1.5
1.8
1
1.5
1.2
0.8
0.5
25° C
55
25°C
50
0
0
0.5
1
1.5
2
2.5
3
0.5
0
OUTPUT CURRENT (A)
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
Figure 5.
Figure 6.
Efficiency 24V Input @ 25°C
Dissipation 24V Input @ 25°C
2.5
100
95
5.0
2
5.0
85
80
3.3
2.5
75
1.8
3.3
DISSIPATION (W)
EFFICIENCY (%)
90
70
65
60
1.5
2.5
1
0.5
25°C
55
25°C
50
0
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT(A)
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
Figure 7.
6
1.8
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 100uF X7R Ceramic;
Tambient = 25 C for efficiency curves and waveforms.
Efficiency 36V Input @ 25°C
Dissipation 36V Input @ 25°C
2.5
100
95
5.0
2
3.3
5.0
85
DISSIPATION (W)
EFFICIENCY (%)
90
3.3
80
75
70
65
60
1.5
1
0.5
25°C
55
25°C
50
0
0
0.5
1
1.5
2
2.5
3
0
0.5
OUTPUT CURRENT (A)
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
Figure 9.
Figure 10.
Efficiency 6V Input @ 85°C
Dissipation 6V input @ 85°C
100
3
95
2.5
85
DISSIPATION (W)
EFFICIENCY (%)
90
3.3
2.5
80
75
1.8
1.5
1.2
70
65
60
2
1.8
1.5
1.5
1.2
1
0.8
0.5
0.8
55
3.3
2.5
85°C
85°C
0
50
0
0.5
1
1.5
2
0
3
2.5
0.5
1
Figure 11.
2
2.5
3
Figure 12.
Efficiency 8V input 85°C
100
1.5
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Dissipation 8V input 85°C
3
95
85
5.0
80
3.3
2.5
75
DISSIPATION (W)
EFFICIENCY (%)
5.0
2.5
90
1.8
1.5
70
1.2
65
60
0.8
3.3
2.5
2
1.8
1.5
1.5
1.2
1
0.8
0.5
55
85°C
85°C
50
0
0.5
1
1.5
2
2.5
3
0
OUTPUT CURRENT (A)
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 100uF X7R Ceramic;
Tambient = 25 C for efficiency curves and waveforms.
Efficiency 12V input@ 85°C
Dissipation 12V input @ 85°C
3
100
95
2.5
5.0
3.3
5.0
85
DISSIPATION (W)
EFFICIENCY (%)
90
3.3
80
2.5
1.8
1.5
75
70
1.2
65
2
2.5
1.8
1.5
1.5
1.2
1
0.8
0.8
60
0.5
85°C
55
85°C
50
0
0.5
1
1.5
2
2.5
0
3
0
0.5
OUTPUT CURRENT (A)
1
1.5
2
Figure 16.
Efficiency 24V input @ 85°C
Dissipation 24V input @ 85°C
3
100
95
5.0
2.5
90
3.3
DISSIPATION (W)
5.0
85
3.3
80
2.5
75
1.8
70
65
60
2
1.5
2.5
1.8
1
0.5
85°C
55
85°C
50
0
0.5
0
1
1.5
2
2.5
3
0
0.5
OUTPUT CURRENT (A)
1
1.5
2
2.5
Figure 18.
Efficiency 36V input @ 85°C
Dissipation 36V input @ 85°C
100
3
5.0
95
2.5
85
5.0
80
3.3
DISSIPATION (W)
90
EFFICIENCY (%)
3
OUTPUT CURRENT (A)
Figure 17.
75
70
65
60
3.3
2
1.5
1
0.5
55
85°C
85°C
0
50
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
Figure 19.
8
3
OUTPUT CURRENT (A)
Figure 15.
EFFICIENCY (%)
2.5
Figure 20.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 100uF X7R Ceramic;
Tambient = 25 C for efficiency curves and waveforms.
Line and Load Regulation @ 25°C
Line and Load Regulation @ 85C
3.36
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.36
3.34
15 20
36
42
3.32
8
12
25°C
3.34
42
36
20
12
8
3.32
15
3.30
6
3.28
6
85°C
3.30
0
0.5
1
1.5
2
2.5
3.26
3
0
0.5
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
3.32
2
2.5
3
OUTPUT CURRENT (A)
Figure 21.
Figure 22.
Line and Load Regulation @ –55°C
Output Ripple
24VIN 3.3VO 3A, BW = 200 MHz
3.36
3.34
1.5
1
42
36
20
15
12
8
3.30
3.28
-55°C
3.26
0.5
0
6
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
Figure .
Figure 23.
Transient Response
24VIN 3.3VO 0.6A to 3A Step
Thermal Derating VOUT = 3.3V
3.5
12Vin
OUTPUT CURRENT (A)
3
2.5
36VIN
6Vin
2
24Vin
6Vin
1.5
1
12Vin
JA = 19.6°C/W
0.5
VOUT = 3.3V
0
50
60
70
80
90
100 110 120
AMBIENT TEMPERATURE (°C)
Figure 24.
Figure 25.
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Typical Performance Characteristics (continued)
Unless otherwise specified, the following conditions apply: VIN = 24V; Cin = 10uF X7R Ceramic; CO = 100uF X7R Ceramic;
Tambient = 25 C for efficiency curves and waveforms.
Current Limit 3.3VOUT @ 25°C
5
Current Limit 3.3VOUT @ 85C
5
SHORT CIRCUIT
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
SHORT CIRCUIT
4.5
ONSET
4
3.5
4.5
ONSET
4
3.5
85°C
25°C
3
3
0
5
10
15
20
25 30
35
40
45
0
5
10
15
20
25
30
35
40
45
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 26.
Figure 27.
Current Limit 3.3VOUT @ -55°C
5
OUTPUT CURRENT (A)
SHORT CIRCUIT
4.5
ONSET
4
3.5
3
-55°C
0
5
10
15
20
25
30 35
40
45
INPUT VOLTAGE (V)
Figure 28.
10
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APPLICATION BLOCK DIAGRAM
Vin
VIN 1
Linear reg
CIN
Cvcc
5
SS
Css
CBST
3
EN
RON
2
VOUT 7
RON
Timer
CFF
6
6.8 éH
VO
Co
FB
RFBT
RFBB
0.47 éF
Regulator IC
Internal
Passives
GND
4
COT Control Circuit Overview
Constant On Time control is based on a comparator and an on-time one shot, with the output voltage feedback
compared with an internal 0.8V reference. If the feedback voltage is below the reference, the main MOSFET is
turned on for a fixed on-time determined by a programming resistor RON. RON is connected to VIN such that ontime is reduced with increasing input supply voltage. Following this on-time, the main MOSFET remains off for a
minimum of 260 ns. If the voltage on the feedback pin falls below the reference level again the on-time cycle is
repeated. Regulation is achieved in this manner.
Design Steps for the LMZ14203EXT Application
The LMZ14203EXT is fully supported by Webench® and offers the following: Component selection, electrical and
thermal simulations as well as the build-it board for a reduction in design time. The following list of steps can be
used to manually design the LMZ14203EXT application.
• Select minimum operating VIN with enable divider resistors
• Program VO with divider resistor selection
• Program turn-on time with soft-start capacitor selection
• Select CO
• Select CIN
• Set operating frequency with RON
• Determine module dissipation
• Layout PCB for required thermal performance
ENABLE DIVIDER, RENT AND RENB SELECTION
The enable input provides a precise 1.18V band-gap rising threshold to allow direct logic drive or connection to a
voltage divider from a higher enable voltage such as VIN. The enable input also incorporates 90 mV (typ) of
hysteresis resulting in a falling threshold of 1.09V. The maximum recommended voltage into the EN pin is 6.5V.
For applications where the midpoint of the enable divider exceeds 6.5V, a small zener can be added to limit this
voltage.
The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit
will be disabled. This implements the feature of programmable under voltage lockout. This is often used in
battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for
sequencing of output rails or to prevent early turn-on of the supply as the main input voltage rail rises at powerup. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems
such as 24V AC/DC systems where a lower boundary of operation should be established. In the case of
sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the
LMZ14203EXT output rail. The two resistors should be chosen based on the following ratio:
RENT / RENB = (VIN UVLO/ 1.18V) – 1
(1)
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The LMZ14203EXT demonstration and evaluation boards use 11.8kΩ for RENB and 68.1kΩ for RENT resulting in a
rising UVLO of 8V. This divider presents 6.25V to the EN input when the divider input is raised to 42V.
OUTPUT VOLTAGE SELECTION
Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of
the divider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal
operation an on-time cycle is initiated when the voltage on the FB pin falls below 0.8V. The main MOSFET ontime cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8V. As long as the voltage at
FB is above 0.8V, on-time cycles will not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO = 0.8V * (1 + RFBT / RFBB)
(2)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO / 0.8V) - 1
These resistors should be chosen from values in the range of 1.0 kohm to 10.0 kohm.
For VO = 0.8V the FB pin can be connected to the output directly so long as an output preload resistor remains
that draws more than 20uA. Converter operation requires this minimum load to create a small inductor ripple
current and maintain proper regulation when no load is present.
A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is
usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for
best transient response and minimum output ripple.
A table of values for RFBT , RFBB , CFF and RON is included in the applications schematic.
SOFT-START CAPACITOR SELECTION
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to
prevent overshoot.
Upon turn-on, after all UVLO conditions have been passed, an internal 8uA current source begins charging the
external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula:
tSS = VREF * CSS / Iss = 0.8V * CSS / 8uA
(3)
This equation can be rearranged as follows:
CSS = tSS * 8 μA / 0.8V
Use of a 0.022μF capacitor results in 2.2 msec soft-start duration. This is recommended as a minimum value.
As the soft-start input exceeds 0.8V the output of the power stage will be in regulation. The soft-start capacitor
continues charging until it reaches approximately 3.8V on the SS pin. Voltage levels between 0.8V and 3.8V
have no effect on other circuit operation. Note that the following conditions will reset the soft-start capacitor by
discharging the SS input to ground with an internal 200 μA current sink.
• The enable input being “pulled low”
• Thermal shutdown condition
• Over-current fault
• Internal Vcc UVLO (Approx 4V input to VIN)
CO SELECTION
None of the required CO output capacitance is contained within the module. At a minimum, the output capacitor
must meet the worst case minimum ripple current rating of 0.5 * ILR P-P, as calculated in equation Equation 14
below. Beyond that, additional capacitance will reduce output ripple so long as the ESR is low enough to permit
it. A minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with
a minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 SNVA422 for
more detail.
The following equation provides a good first pass approximation of CO for load transient requirements:
CO≥ISTEP*VFB*L*VIN/ (4*VO*(VIN - VO)*VOUT-TRAN)
12
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Solving:
CO ≥ 3A*0.8V*6.8μH*24V / (4*3.3V*( 24V - 3.3V)*33mV)
≥ 43μF
The LMZ14203EXT demonstration and evaluation boards are populated with a 100 uF 6.3V X5R output
capacitor. Locations for extra output capacitors are provided.
CIN SELECTION
The LMZ14203EXT module contains an internal 0.47 µF input ceramic capacitor. Additional input capacitance is
required external to the module to handle the input ripple current of the application. This input capacitance should
be located in very close proximity to the module. Input capacitor selection is generally directed to satisfy the input
ripple current requirements rather than by capacitance value. Worst case input ripple current rating is dictated by
the equation:
I(CIN(RMS)) ≊ 1 /2 * IO * √ (D / 1-D)
where
•
D ≊ VO / VIN
(5)
(As a point of reference, the worst case ripple current will occur when the module is presented with full load
current and when VIN = 2 * VO).
Recommended minimum input capacitance is 10uF X7R ceramic with a voltage rating at least 25% higher than
the maximum applied input voltage for the application. It is also recommended that attention be paid to the
voltage and temperature deratings of the capacitor selected. It should be noted that ripple current rating of
ceramic capacitors may be missing from the capacitor data sheet and you may have to contact the capacitor
manufacturer for this rating.
If the system design requires a certain minimum value of input ripple voltage ΔVIN be maintained then the
following equation may be used.
CIN ≥ IO * D * (1–D) / fSW-CCM * ΔVIN
(6)
If ΔVIN is 1% of VIN for a 24V input to 3.3V output application this equals 240 mV and fSW = 400 kHz.
CIN≥ 3A * 3.3V/24V * (1– 3.3V/24V) / (400000 * 0.240 V)
≥ 3.7μF
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input
capacitance and parasitic inductance of the incoming supply lines.
RON RESISTOR SELECTION
Many designs will begin with a desired switching frequency in mind. For that purpose the following equation can
be used.
fSW(CCM) ≊ VO / (1.3 * 10-10 * RON)
(7)
This can be rearranged as
RON ≊ VO / (1.3 * 10 -10 * fSW(CCM))
(8)
The selection of RON and fSW(CCM) must be confined by limitations in the on-time and off-time for the COT
Control Circuit Overview section.
The on-time of the LMZ14203EXT timer is determined by the resistor RON and the input voltage VIN. It is
calculated as follows:
tON = (1.3 * 10-10 * RON) / VIN
(9)
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON should
be selected such that the on-time at maximum VIN is greater than 150 ns. The on-timer has a limiter to ensure a
minimum of 150 ns for tON. This limits the maximum operating frequency, which is governed by the following
equation:
fSW(MAX) = VO / (VIN(MAX) * 150 nsec)
(10)
This equation can be used to select RON if a certain operating frequency is desired so long as the minimum ontime of 150 ns is observed. The limit for RON can be calculated as follows:
RON ≥ VIN(MAX) * 150 nsec / (1.3 * 10 -10)
(11)
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If RON calculated in Equation 8 is less than the minimum value determined in Equation 11 a lower frequency
should be selected. Alternatively, VIN(MAX) can also be limited in order to keep the frequency unchanged.
Additionally note, the minimum off-time of 260 ns limits the maximum duty ratio. Larger RON (lower FSW) should
be selected in any application requiring large duty ratio.
Discontinuous Conduction and Continuous Conduction Modes
At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the
critical conduction point, it will operate in continuous conduction mode (CCM). When operating in DCM the
switching cycle begins at zero amps inductor current; increases up to a peak value, and then recedes back to
zero before the end of the off-time. Note that during the period of time that inductor current is zero, all load
current is supplied by the output capacitor. The next on-time period starts when the voltage on the at the FB pin
falls below the internal reference. The switching frequency is lower in DCM and varies more with load current as
compared to CCM. Conversion efficiency in DCM is maintained since conduction and switching losses are
reduced with the smaller load and lower switching frequency. Operating frequency in DCM can be calculated as
follows:
fSW(DCM)≊VO*(VIN-1)*6.8μH*1.18*1020*IO/(VIN–VO)*RON2
(12)
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the
off-time. The switching frequency remains relatively constant with load current and line voltage variations. The
CCM operating frequency can be calculated using Equation 7 above.
Following is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.
Figure 29. CCM and DCM Operating Modes
VIN = 24V, VO = 3.3V, IO = 3A/0.4A 2 μsec/div
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB ≊ VO*(VIN–VO)/(2*6.8 μH*fSW(CCM)*VIN)
(13)
Following is a typical waveform showing the boundary condition.
Figure 30. Transition Mode Operation
VIN = 24V, VO = 3.3V, IO = 0.5 A 2 μsec/div
The inductor internal to the module is 6.8 μH. This value was chosen as a good balance between low and high
input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple
current (ILR). ILR can be calculated with:
14
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ILR P-P = VO*(VIN- VO)/(6.8µH*fSW*VIN)
where
•
•
VIN is the maximum input voltage
fSW is determined from Equation 7
(14)
If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be
determined. Be aware that the lower peak of ILR must be positive if CCM operation is required.
POWER DISSIPATION AND BOARD THERMAL REQUIREMENTS
For the design case of VIN = 24V, VO = 3.3V, IO = 3A, TAMB(MAX) = 85°C , and TJUNCTION = 125°C, the device must
see a thermal resistance from case to ambient of:
θCA < (TJ-MAX — TAMB(MAX)) / PIC-LOSS - θJC
(15)
Given the typical thermal resistance from junction to case to be 1.9 °C/W. Use the 85°C power dissipation curves
in the Typical Performance Characteristics section to estimate the PIC-LOSS for the application being designed. In
this application it is 2.25W.
θCA < (125 — 85) / 2.25W — 1.9 = 15.8
To reach θCA = 15.8, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a
good estimate of the required board area covered by 1 oz. copper on both the top and bottom metal layers is:
Board Area_cm2 > 500°C x cm2/W / θCA
(16)
As a result, approximately 31.5 square cm of 1 oz copper on top and bottom layers is required for the PCB
design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty six, 10mils (254
μm) thermal vias spaced 59mils (1.5 mm) apart must connect the top copper to the bottom copper. For an
example of a high thermal performance PCB layout, refer to the Evaluation Board application note AN-2024
SNVA422.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
VIN
LMZ14203EXT
VIN
VO
VOUT
High
di/dt
Cin1
CO1
GND
Loop 2
Loop 1
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt paths during PC board layout. The
high current loops that do not overlap have high di/dt content that will cause observable high frequency noise on
the output pin if the input capacitor (Cin1) is placed at a distance away from the LMZ14203EXT. Therefore place
CIN1 as close as possible to the LMZ14203EXT VIN and GND exposed pad. This will minimize the high di/dt area
and reduce radiated EMI. Additionally, grounding for both the input and output capacitor should consist of a
localized top side plane that connects to the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of
the device. This prevents any switched or load currents from flowing in the analog ground traces. If not properly
handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide
the single point ground connection from pin 4 to EP.
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3. Minimize trace length to the FB pin.
Both feedback resistors, RFBT and RFBB, and the feed forward capacitor CFF, should be located close to the FB
pin. Since the FB node is high impedance, maintain the copper area as small as possible. The trace are from
RFBT, RFBB, and CFF should be routed away from the body of the LMZ14203EXT to minimize noise.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so
will correct for voltage drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If
the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner
layer heat-spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 10mils
(254 μm) thermal vias spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the
junction temperature below 125°C.
Additional Features
OUTPUT OVER-VOLTAGE COMPARATOR
The voltage at FB is compared to a 0.92V internal reference. If FB rises above 0.92V the on-time is immediately
terminated. This condition is known as over-voltage protection (OVP). It can occur if the input voltage is
increased very suddenly or if the output load is decreased very suddenly. Once OVP is activated, the top
MOSFET on-times will be inhibited until the condition clears. Additionally, the synchronous MOSFET will remain
on until inductor current falls to zero.
CURRENT LIMIT
Current limit detection is carried out during the off-time by monitoring the current in the synchronous MOSFET.
Referring to the Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows
through the load, the PGND pin and the internal synchronous MOSFET. If this current exceeds 4.2A (typical) the
current limit comparator disables the start of the next on-time period. The next switching cycle will occur only if
the FB input is less than 0.8V and the inductor current has decreased below 4.2A. Inductor current is monitored
during the period of time the synchronous MOSFET is conducting. So long as inductor current exceeds 4.2A,
further on-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due
to the longer off-time. It should also be noted that current limit is dependent on both duty cycle and temperature.
THERMAL PROTECTION
The junction temperature of the LMZ14203EXT should not be allowed to exceed its maximum ratings. Thermal
protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typ) causing the
device to enter a low power standby state. In this state the main MOSFET remains off causing VO to fall, and
additionally the CSS capacitor is discharged to ground. Thermal protection helps prevent catastrophic failures for
accidental device overheating. When the junction temperature falls back below 145 °C (typ Hyst = 20 °C) the SS
pin is released, VO rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require application
derating at elevated temperatures.
ZERO COIL CURRENT DETECTION
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which
inhibits the synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables the
DCM operating mode, which improves efficiency at light loads.
PRE-BIASED STARTUP
The LMZ14203EXT will properly start up into a pre-biased output. This startup situation is common in multiple rail
logic applications where current paths may exist between different power rails during the startup sequence. The
following scope capture shows proper behavior during this event.
16
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Figure 31. Pre-Biased Startup
Evaluation Board Schematic Diagram
U1
EP
Enable
VIN
VOUT
FB
SS
GND
3.3VO @ 3A
7
6
5
EN
4
3
2
1
VIN
RON
LMZ14203EXTTZ-ADJ
8V to 42V
RENT
68.1k
CFF
0.022 PF
RFBT
3.32k
RON
61.9k
RENB
11.8k
CIN2
10 PF
CIN1
1 PF
CSS
0.022 PF
RFBB
1.07k
CO1
1 PF
CO2
100 PF
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Ref Des
Description
Case Size
Manufacturer
Manufacturer P/N
U1
SIMPLE SWITCHER ®
PFM-7
Texas Instruments
LMZ14203EXTTZ-ADJ
Cin1
1 µF, 50V, X7R
1206
Taiyo Yuden
UMK316B7105KL-T
Cin2
10 µF, 50V, X7R
1210
Taiyo Yuden
UMK325BJ106MM-T
CO1
1 µF, 50V, X7R
1206
Taiyo Yuden
UMK316B7105KL-T
CO2
100 µF, 6.3V, X7R
1210
Taiyo Yuden
JMK325BJ107MM-T
RFBT
3.32 kΩ
0603
Vishay Dale
CRCW06033K32FKEA
RFBB
1.07 kΩ
0603
Vishay Dale
CRCW06031K07FKEA
RON
61.9 kΩ
0603
Vishay Dale
CRCW060361k9FKEA
RENT
68.1 kΩ
0603
Vishay Dale
CRCW060368k1FKEA
RENB
11.8 kΩ
0603
Vishay Dale
CRCW060311k8FKEA
CFF
22 nF, ±10%, X7R, 16V
0603
TDK
C1608X7R1H223K
CSS
22 nF, ±10%, X7R, 16V
0603
TDK
C1608X7R1H223K
Figure 32. PCB Layout Example
18
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 18
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PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LMZ14203EXTTZ/NOPB
ACTIVE
PFM
NDW
7
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14203
EXT
LMZ14203EXTTZE/NOPB
ACTIVE
PFM
NDW
7
45
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14203
EXT
LMZ14203EXTTZX/NOPB
ACTIVE
PFM
NDW
7
500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 125
LMZ14203
EXT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMZ14203EXTTZ/NOPB
PFM
NDW
7
250
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
LMZ14203EXTTZX/NOPB
PFM
NDW
7
500
330.0
24.4
10.6
14.22
5.0
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMZ14203EXTTZ/NOPB
PFM
NDW
7
250
367.0
367.0
45.0
LMZ14203EXTTZX/NOPB
PFM
NDW
7
500
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
NDW0007A
BOTTOM SIDE OF PACKAGE
TOP SIDE OF PACKAGE
TZA07A (Rev D)
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