Data Sheet HN58C256AI Series 256k EEPROM (32-kword × 8-bit) R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Description Renesas Electronics' HN58C256AI are electrically erasable and programmable ROMs organized as 32768-word × 8-bit. They have realized high speed low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster. Features • Single 5 V supply: 5 V ±10% • Access time: 85 ns/100 ns (max) • Power dissipation ⎯ Active: 20 mW/MHz, (typ) ⎯ Standby: 110 μW (max) • On-chip latches: address, data, CE, OE, WE • Automatic byte write: 10 ms max • Automatic page write (64 bytes): 10 ms max • Data polling and Toggle bit • Data protection circuit on power on/off • Conforms to JEDEC byte-wide standard • Reliable CMOS with MNOS cell technology • 105 erase/write cycles (in page mode) • 10 years data retention • Software data protection • There are lead free products R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 1 of 16 HN58C256AI Series Ordering Information Orderable Part Name HN85C256API85E HN85C256API10E HN85C256AFPI85E HN85C256AFPI10E HN85C256AFPI85EZ HN85C256AFPI10EZ HN85C256ATI85E HN85C256ATI10E Access time 85ns 100ns 85ns 100ns 85ns 100ns 85ns 100ns Shipping Container Package Quantity 600mil 28-pin plastic DIP PRDP0028AB-A (DP-28V) Tube Max. 13 pcs/tube Max. 325 pcs/inner box 400mil 28-pin plastic SOP PRSP0028DC-A (FP-28DV) Tube Max. 25 pcs/tube Max. 1,000 pcs/inner box Tape and reel 28-pin plastic TSOP PTSA0028ZB-A (TFP-28DBV) Tray 1,000 pcs/reel Max. 60 pcs/tray Max. 600 pcs/inner box Pin Arrangement HN58C256API/AFPI Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 HN58C256ATI Series A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE (Top view) (Top view) R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 2 of 16 HN58C256AI Series Pin Description Pin Name Function A0 to A14 I/O0 to I/O7 OE CE WE VCC VSS NC Address input Data input/output Output enable Chip enable Write enable Power supply Ground No connection Block Diagram VCC I/O0 to I/O7 High voltage generator VSS I/O buffer and input latch OE CE Control logic and timing WE A0 Y decoder to Y gating A5 Address buffer and latch X decoder Memory array A6 to A14 Data latch R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 3 of 16 HN58C256AI Series Operation Table CE Operation Read Standby Write Deselect Write inhibit VIL VIH VIL VIL × × VIL × Data polling Program reset Note: OE VIL ×*1 VIH VIH × VIL VIL × WE VIH × VIL VIH VIH × VIH × I/O Dout High-Z Din High-Z — — Dout (I/O7) High-Z 1. Don’t care Absolute Maximum Ratings Parameter Power supply voltage relative to VSS Input voltage relative to VSS Operating temperature range*2 Storage temperature range Symbol Value –0.6 to +7.0 –0.5*1 to +7.0*3 –40 to +85 –55 to +125 VCC Vin Topr Tstg Unit V V °C °C Notes: 1. Vin min: –3.0 V for pulse width ≤ 50 ns 2. Including electrical characteristics and data retention 3. Should not exceed VCC + 1 V. Recommended DC Operating Conditions Parameter Supply voltage Input voltage Operating temperature Symbol VCC VSS VIL VIH Topr Min 4.5 0 –0.3*1 3.0 –40 Typ 5.0 0 — — — Max 5.5 0 0.6 VCC + 0.3*2 +85 Unit V V V V °C Notes: 1. VIL min: –1.0 V for pulse width ≤ 50 ns 2. VIH max: VCC + 1.0 V for pulse width ≤ 50 ns R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 4 of 16 HN58C256AI Series DC Characteristics (Ta = –40 to +85°C, VCC = 5.0 V ±10%) Parameter Input leakage current Output leakage current Standby VCC current Operating VCC current Output low voltage Output high voltage Symbol ILI ILO ICC1 ICC2 ICC3 VOL VOH Min — — — — — Typ — — — — — Max 2 2 20 1 12 Unit μA μA μA mA mA Test conditions VCC = 5.5 V, Vin = 5.5 V VCC = 5.5 V, Vout = 5.5/0.4 V CE = VCC CE = VIH — — 30 mA — VCC × 0.8 — — 0.4 — V V Iout = 0 mA, Duty = 100%, Cycle = 85 ns, VCC = 5.5 V IOL = 2.1 mA IOH = –400 μA Min — Typ — Max 6 Unit pF — — 12 pF Iout = 0 mA, Duty = 100%, Cycle = 1 μs, VCC = 5.5 V Capacitance (Ta = +25°C, f = 1 MHz) Parameter Input capacitance*1 Symbol Cin Output capacitance*1 Cout Note: Test conditions Vin = 0 V Vout = 0 V 1. This parameter is periodically sampled and not 100% tested. R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 5 of 16 HN58C256AI Series AC Characteristics (Ta = –40 to +85°C, VCC = 5.0 V ±10%) Test Conditions • • • • • Input pulse levels: 0.4 V to 3.0 V Input rise and fall time: ≤ 5 ns Input timing reference levels: 0.8, 2.0 V Output load: 1TTL Gate +100 pF Output reference levels: 1.5 V, 1.5 V Read Cycle Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float*1 Symbol tACC tCE tOE tOH tDF HN58C256API/AFPI/ATI -85 -10 Min Max Min Max — 85 — 100 — 85 — 100 10 40 10 50 0 — 0 — 0 40 0 40 Unit ns ns ns ns ns Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH Write Cycle Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Symbol tAS tAH tCS tCH tWS tWH tOES tOEH tDS tDH tWP tCW tDL tBLC tBL tWC tDB tDW Min*2 0 50 0 0 0 0 0 0 50 0 100 100 50 0.2 100 — 120 0*4 Typ — — — — — — — — — — — — — — — — — — Max — — — — — — — — — — — — — 30 — 10*3 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns μs μs ms ns ns Test conditions Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. Use this device in longer cycle than this value. 3. tWC must be longer than this value unless polling techniques are used. This device automatically completes the internal write operation within this value. 4. Next read or write operation can be initiated after tDW if polling techniques are used. 5. A6 through A14 are page address and these addresses are latched at the first falling edge of WE. 6. A6 through A14 are page address and these addresses are latched at the first falling edge of CE. 7. See AC read characteristics. R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 6 of 16 HN58C256AI Series Timing Waveforms Read Timing Waveform Address tACC CE tOH tCE OE tDF tOE WE Data Out R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 High Data out valid Page 7 of 16 HN58C256AI Series Byte Write Timing Waveform (1) (WE Controlled) tWC Address tCS tAH tCH CE tAS tBL tWP WE tOES tOEH OE tDS tDH Din VCC Byte Write Timing Waveform (2) (CE Controlled) Address tWS tAH tBL tWC tCW CE tAS tWH WE tOES tOEH OE tDS tDH Din VCC R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 8 of 16 HN58C256AI Series Page Write Timing Waveform (1) (WE Controlled) *7 Address A0 to A14 tAS tAH tBL tWP WE tDL tCS tBLC tWC tCH CE tOEH tOES tDH OE tDS Din VCC Page Write Timing Waveform (2) (CE Controlled) *8 Address A0 to A14 tAS CE tAH tBL tCW tDL tWS tBLC tWC tWH WE tOEH tOES OE tDH tDS Din VCC R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 9 of 16 HN58C256AI Series Data Polling Timing Waveform Address An An An CE WE tOEH tCE *9 tOES OE tDW tOE*9 Dout X Din X I/O7 Dout X tWC Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Toggle bit Waveform Notes: 1. 2. 3. 4. I/O6 beginning state is "1". I/O6 ending state will vary. See AC read characteristics. Any address location can be used, but the address must be fixed. Next mode *4 Address tCE *3 CE WE *3 tOE OE tOES tOEH *1 I/O6 Din Dout Dout tWC R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 *2 *2 Dout Dout tDW Page 10 of 16 HN58C256AI Series Software Data Protection Timing Waveform (1) (in protection mode) VCC CE WE tBLC Address Data 5555 AA 2AAA 55 5555 A0 tWC Write address Write data Software Data Protection Timing Waveform (2) (in non-protection mode) VCC tWC Normal active mode CE WE Address Data R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 5555 2AAA 5555 5555 2AAA 5555 AA 55 80 AA 55 20 Page 11 of 16 HN58C256AI Series Functional Description Automatic Page Write Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 μs from the preceding falling edge of WE or CE. When CE or WE is high for 100 μs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is performing a write operation. WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Data Protection To prevent this phenomenon, this device has a noise cancelation function that cuts noise if its width is 20 ns or less. 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the control pins. WE CE VIH 0V VIH OE 0V 20 ns max R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 12 of 16 HN58C256AI Series 2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM shoud be kept in unprogrammable state during VCC on/off by using CPU RESET signal. VCC CPU RESET * Unprogrammable * Unprogrammable 2.1 Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below. CE VCC OE WE × × × VSS × × × VCC ×: Don’t care VCC: Pull-up to VCC level VSS: Pull-down to VSS level 3. Software data protection To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data. Address Data 5555 AA ↓ ↓ 2AAA 55 ↓ ↓ 5555 A0 ↓ ↓ Write address Write data } Normal data input The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP disable cycle, data can not be written. Address Data 5555 ↓ 2AAA ↓ 5555 ↓ 5555 ↓ 2AAA ↓ 5555 AA ↓ 55 ↓ 80 ↓ AA ↓ 55 ↓ 20 The software data protection is not enabled at the shipment. Note: There are some differences between Renesas Electronics' and other company’s for enable/disable sequence of software data protection. If there are any questions, please contact with Renesas Electronics' sales offices. R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 Page 13 of 16 HN58C256AI Series Package Dimensions HN58C256API Series (PRDP0028AB-A / Previous Code: DP-28V) JEITA Package Code P-DIP28-13.4x35.6-2.54 RENESAS Code PRDP0028AB-A Previous Code DP-28/DP-28V MASS[Typ.] 4.6g D 15 E 28 1 14 b3 A Reference Symbol L A1 Z e bp θ c e1 R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 e1 D E A A1 bp b3 c θ e Z L Dimension in Millimeters Min Nom Max 15.24 35.6 36.5 13.4 14.6 5.70 0.51 0.38 0.48 0.58 1.2 0.20 0.25 0.36 0° 15° 2.29 2.54 2.79 1.9 2.54 Page 14 of 16 HN58C256AI Series HN58C256AFPI Series (PRSP0028DC-A / Previous Code: FP-28DV) JEITA Package Code P-SOP28-8.4x18.3-1.27 RENESAS Code PRSP0028DC-A Previous Code FP-28D MASS[Typ.] 0.7g D F 28 NOTE) 1. DIMENSION"*1" DOES NOT INCLUDE MOLD FLASH. 2. DIMENSION"*2"DOES NOT INCLUDE TRIM OFFSET. 15 bp c c1 HE *1 E b1 Index mark Terminal cross section 1 Reference Symbol 14 e *2 bp x M L1 A Z A1 q y L Detail F R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 18.3 18.8 8.4 0.10 0.20 0.30 2.50 0.32 0.40 0.48 0.38 0.12 0.17 0.22 0.15 0° 8° 11.5 11.8 12.1 1.27 0.20 0.15 1.12 0.8 1.0 1.2 1.7 Page 15 of 16 HN58C256AI Series HN58C256ATI Series (PTSA0028ZB-A / Previous Code: TFP-28DBV) JEITA Package Code P-TSOP(1)28-8x11.8-0.55 RENESAS Code PTSA0028ZB-A Previous Code TFP-28DB/TFP-28DBV MASS[Typ.] 0.23g y NOTE) 1. DIMENSION"*1"AND"*2(Nom)" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD D 28 bp *3 1 bp x Index mark A M *1 15 Terminal cross section Z 14 c c1 e *2 E b1 Reference Dimension in Millimeters Symbol F L1 q A1 L Detail F R10DS0218EJ0100 Rev.1.00 Oct 07, 2013 D E A2 A1 A bp b1 c c1 θ HD e x y Z L L1 Min Nom Max 11.80 8.00 8.20 0.05 0.13 0.14 0.22 0.20 0.17 0.15 0.12 0.20 1.20 0.30 0.22 0° 5° 13.10 13.40 13.70 0.55 0.10 0.10 0.45 0.40 0.50 0.60 0.80 Page 16 of 16 Revision History HN58C256AI Series Data Sheet Description Rev. Rev.1.00 Date Oct 07, 2013 Page — Summary Initial issue All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. 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