Datasheet R1RW0416DI Series Wide Temperature Range Version 4M High Speed SRAM (256-kword × 16-bit) REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Description The R1RW0416DI is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The R1RW0416DI is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting. Features • Single 3.3 V supply: 3.3 V ± 0.3 V • Access time: 10ns/12 ns (max) • Completely static memory No clock or timing strobe required • Equal access and cycle times • Directly TTL compatible All inputs and outputs • Operating current: 145/130 mA (max) • TTL standby current: 40 mA (max) • CMOS standby current: 5 mA (max) • Center VCC and VSS type pin out • Temperature range: −40 to +85°C Ordering Information Type No. Access time R1RW0416DGE-0PI 10ns R1RW0416DGE-2PI 12 ns R1RW0416DSB-0PI 10 ns R1RW0416DSB-2PI 12 ns REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Package 400-mil 44-pin plastic SOJ (44P0K) 400-mil 44-pin plastic TSOPII (44P3W-H) Page 1 of 11 R1RW0416DI Series Pin Arrangement Pin Description Pin name Function A0 to A17 Address input I/O1 to I/O16 Data input/output CS# OE# Chip select Output enable WE# UB# Write enable Upper byte select LB# VCC Lower byte select Power supply VSS NC Ground No connection REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 2 of 11 R1RW0416DI Series Block Diagram REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 3 of 11 R1RW0416DI Series Operation Table CS# OE# WE# LB# UB# H × L H L L L L L L L L L L L L Note: Mode VCC current I/O1− −I/O8 I/O9− −I/O16 High-Z Ref. Cycle × × Standby ISB, ISB1 High-Z H × × Output disable ICC High-Z High-Z H H L L L H Read ICC Lower byte read ICC Output Output Output High-Z Read cycle Read cycle H H H H L H Upper byte read ICC ICC High-Z High-Z Output High-Z Read cycle × × L L L L L H Write ICC Lower byte write ICC Input Input Input High-Z Write cycle Write cycle × × L L H H L H Upper byte write ICC ICC High-Z High-Z Input High-Z Write cycle × H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Supply voltage relative to VSS VCC −0.5 to +4.6 Voltage on any pin relative to VSS Power dissipation VT PT −0.5* to VCC + 0.5* 1.0 V W Operating temperature Storage temperature Topr Tstg −40 to +85 −55 to +125 °C °C Storage temperature under bias Tbias −40 to +85 °C 1 V 2 Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns 2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 4 of 11 R1RW0416DI Series Recommended DC Operating Conditions (Ta = −40 to +85°C) Parameter Symbol Supply voltage Typ Max Unit 3 3.0 3.3 3.6 VSS* 4 0 0 0 VIH VIL 2.0 1 −0.5* VCC + 0.5* 0.8 VCC* Input voltage Notes: 1. 2. 3. 4. Min V V 2 V V VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. DC Characteristics (Ta = −40 to +85°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) Parameter Symbol Min Max Unit Test conditions Input leakage current Output leakage current |ILI| |ILO| 2 2 µA µA VIN = VSS to VCC VIN = VSS to VCC Operating power supply current ICC 130 mA Standby power supply current ISB 40 mA Min cycle CS# = VIL, IOUT = 0 mA Other inputs = VIH/VIL Min cycle, CS# = VIH, Other inputs = VIH/VIL ISB1 5 mA VOL 0.4 V f = 0 MHz VCC ≥ CS# ≥ VCC − 0.2 V, (1) 0 V ≤ VIN ≤ 0.2 V or (2) VCC ≥ VIN ≥ VCC − 0.2 V IOL = 8 mA VOH 2.4 V IOH = −4 mA Output voltage Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol 1 Input capacitance* 1 Input/output capacitance* Note: Min Max Unit Test conditions CIN 6 pF VIN = 0 V CI/O 8 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 5 of 11 R1RW0416DI Series AC Characteristics (Ta = −40 to +85°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.) Test Conditions • Input pulse levels: 3.0 V/0.0 V • Input rise and fall time: 3 ns • Input and output timing reference levels: 1.5 V • Output load: See figures (Including scope and jig) Read Cycle R1RW0416DI Parameter Symbol 10ns Version 12ns Version Min Min Max Max Unit Notes Read cycle time Address access time tRC tAA 10 10 12 12 ns ns Chip select access time Output enable to output valid tACS tOE 10 5 12 6 ns ns Byte select to output valid Output hold from address change tBA tOH 3 5 3 6 ns ns Chip select to output in low-Z Output enable to output in low-Z tCLZ tOLZ 3 0 3 0 ns ns 1 1 Byte select to output in low-Z Chip deselect to output in high-Z tBLZ tCHZ 0 5 0 6 ns ns 1 1 Output disable to output in high-Z Byte deselect to output in high-Z tOHZ tBHZ 5 5 6 6 ns ns 1 1 REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 6 of 11 R1RW0416DI Series Write Cycle R1RW0416DI Parameter Symbol 10ns Version 12ns Version Min Min Max Max Unit Notes Write cycle time Address valid to end of write tWC tAW 10 7 12 8 ns ns Chip select to end of write Write pulse width tCW tWP 7 7 8 8 ns ns 8 7 Byte select to end of write Address setup time tBW tAS 7 0 8 0 ns ns 5 Write recovery time Data to write time overlap tWR tDW 0 5 0 6 ns ns Data hold from write time Write disable to output in low-Z tDH tOW 0 3 0 3 ns ns 1 Output disable to output in high-Z Write enable to output in high-Z tOHZ tWHZ 5 5 6 6 ns ns 1 1 6 Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is sampled and not 100% tested. 2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or after the WE# transition, output remains a high impedance state. 3. WE# and/or CS# must be high during address transition time. 4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 5. tAS is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going low. 6. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address transition. 7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (tWP). A write begins at the latest transition among CS# going low, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS# going high, WE# going high and LB# going high or UB# going high. 8. tCW is measured from the later of CS# going low to the end of write. REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 7 of 11 R1RW0416DI Series Timing Waveforms Read Timing Waveform (1) (WE# = VIH) Read Timing Waveform (2) (WE# = VIH, LB# = VIL, UB# = VIL) REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 8 of 11 R1RW0416DI Series Write Timing Waveform (1) (WE# Controlled) REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 9 of 11 R1RW0416DI Series Write Timing Waveform (2) (CS# Controlled) REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 10 of 11 R1RW0416DI Series Write Timing Waveform (3) (LB#, UB# Controlled, OE# = VIH) REJ03C0109-0201 Rev.2.01 Jun 16, 2010 Page 11 of 11 Revision History R1RW0416DI Series data sheet Rev. Date Page 0.01 1.00 Sep. 30, 2003 Mar. 12, 2004 − −- 2.00 May. 01, 2009 − P1 P5 P6/P7 Description Summary Initial issue Deletion of Preliminary Addition of access grade 10ns version. The product lineup :R1RW0416DSB-0PI/DGE-0PI is added. Operating power supply current of 10ns cycle version is described to the DC characteristic. The timing standard of 10ns version is described at the read cycle The timing standard of 10ns version is described at the write cycle 2.01 Jun. 16, 2010 − Change the format, ‘Renesas Electronics Corporation’, All documents should contain the following section break and paragraph as the last item. The footers of this document refer to the paragraph in order to reference the last page of the document. All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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