HN58V1001 Series 1M EEPROM (128-kword × 8-bit) Ready/Busy and RES function REJ03C0146-0800Z (Previous ADE-203-314G (Z) Rev. 7.0) Rev. 8.00 Nov. 28. 2003 Description Renesas Technology's HN58V1001 is an electrically erasable and programmable ROM organized as 131072word × 8-bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming function to make the write operations faster. Features • Single 3 V supply: 2.7 V to 5.5 V • Access time: 250 ns (max) • Power dissipation Active: 20 mW/MHz, (typ) Standby: 110 µW (max) • On-chip latches: address, data, CE, OE, WE • Automatic byte write: 15 ms (max) • Automatic page write (128 bytes): 15 ms (max) • Data polling and RDY/Busy • Data protection circuit on power on/off • Conforms to JEDEC byte-wide standard • Reliable CMOS with MNOS cell technology • 10 erase/write cycles (in page mode) 4 • 10 years data retention • Software data protection • Write protection by RES pin • There are also lead free products. Rev.8.00, Nov. 28. 2003, page 1 of 21 HN58V1001 Series Ordering Information Type No. Access time Package HN58V1001FP-25 250 ns 525 mil 32-pin plastic SOP (FP-32D) HN58V1001T-25 250 ns 32-pin plastic TSOP (TFP-32DA) HN58V1001FP-25E 250 ns 525 mil 32-pin plastic SOP (FP-32DV) Lead free HN58V1001T-25E 250 ns 32-pin plastic TSOP (TFP-32DAV) Lead free Pin Arrangement HN58V1001FP Series RDY/Busy A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 RES A3 WE A2 A1 A13 A0 I/O0 A8 I/O1 A9 I/O2 A11 VSS OE I/O3 A10 I/O4 I/O5 CE I/O6 I/O7 I/O7 I/O6 CE A10 I/O5 OE I/O4 I/O3 (Top view) Rev.8.00, Nov. 28. 2003, page 2 of 21 HN58V1001T Series 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (Top view) A4 A5 A6 A7 A12 A14 A16 RDY/Busy VCC A15 RES WE A13 A8 A9 A11 HN58V1001 Series Pin Description Pin name Function A0 to A16 Address input I/O0 to I/O7 Data input/output OE Output enable CE Chip enable WE Write enable VCC Power supply VSS Ground RDY/Busy Ready busy RES Reset Block Diagram VCC VSS I/O0 to I/O7 High voltage generator RES OE I/O buffer and input latch CE WE RES Control logic and timing A0 to Y decoder Y gating X decoder Memory array A6 Address buffer and latch A7 to A16 Data latch Rev.8.00, Nov. 28. 2003, page 3 of 21 RDY/Busy HN58V1001 Series Operation Table Operation CE OE WE RES Read VIL VIL VIH VH* RDY/Busy Busy I/O High-Z Dout Standby VIH ×* × × High-Z High-Z Write VIL VIH VIL VH High-Z to VOL Din Deselect VIL VIH VIH VH High-Z High-Z Write Inhibit × × VIH × Data Polling × VIL × × VIL VIL VIH VH VOL Dout (I/O7) Program reset × × × VIL High-Z High-Z 2 1 Notes: 1. Refer to the recommended DC operating conditions. 2. × : Don’t care Absolute Maximum Ratings Parameter Symbol Supply voltage relative to VSS VCC −0.6 to +7.0 V Input voltage relative to VSS Vin −0.5* to +7.0 V Topr 0 to +70 °C Tstg –55 to +125 °C Operating temperature range* 2 Storage temperature range Value Unit 1 Notes: 1. Vin min = −3.0 V for pulse width ≤ 50 ns 2. Including electrical characteristics and data retention Recommended DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.7 3.0 5.5 V VSS 0 0 0 V VIL −0.3* Input voltage Operating temperature 0.8 V VIH 1.9* 2 VCC + 0.3 V VH VCC − 0.5 VCC + 1.0 V Topr 0 +70 °C Notes: 1. VIL (min): −1.0 V for pulse width ≤ 50 ns 2. VIH (min): 2.2 V for VCC = 3.6 to 5.5 V Rev.8.00, Nov. 28. 2003, page 4 of 21 1 HN58V1001 Series DC Characteristics (Ta = 0 to +70°C, VCC = 2.7 V to 5.5 V) Parameter Symbol Min Typ Input leakage current ILI 2* Output leakage current ILO 2 Standby VCC current ICC1 ICC2 ICC3 Operating VCC current Max Unit Test conditions µA VCC = 3.6 V, Vin =3.6 V µA VCC = 3.6 V, Vout = 3.6/0.4 V 20 µA CE = VCC 1 mA CE = VIH 6 mA Iout = 0 mA, Duty = 100%, Cycle = 1 µs, VCC = 3.3 V 15 mA Iout = 0 mA, Duty = 100%, Cycle = 250 ns, VCC = 3.3 V 1 Output low voltage VOL 0.4 V IOL = 2.1 mA Output high voltage VOH VCC × 0.8 V IOH = −400 µA Notes: 1. ILI on RES: 100 µA (max) Capacitance (Ta = +25°C, f = 1 MHz) Parameter Input capacitance* 1 Output capacitance* Note: 1 Symbol Min Typ Max Unit Test conditions Cin 6 pF Vin = 0 V Cout 12 pF Vout = 0 V 1. This parameter is periodically sampled and not 100% tested. Rev.8.00, Nov. 28. 2003, page 5 of 21 HN58V1001 Series AC Characteristics (Ta = 0 to +70°C, VCC = 2.7 V to 5.5 V) Test Conditions • Input pulse levels: 0.4 V to 2.4 V 0 V to VCC (RES pin) • Input rise and fall time: ≤ 20 ns • Output load: 1TTL Gate +100 pF • Reference levels for measuring timing: 0.8 V, 1.8 V Read Cycle HN58V1001-25 Parameter Symbol Min Max Unit Test conditions Address to output delay tACC 250 ns CE = OE = VIL, WE = VIH CE to output delay tCE 250 ns OE = VIL, WE = VIH OE to output delay tOE 10 120 ns CE = VIL, WE = VIH Address to output hold OE (CE) high to output float* RES low to output float RES to output delay *1 1 tOH 0 ns CE = OE = VIL, WE = VIH tDF 0 50 ns CE = VIL, WE = VIH tDFR 0 350 ns CE = OE = VIL, WE = VIH tRR 0 600 ns CE = OE = VIL, WE = VIH Rev.8.00, Nov. 28. 2003, page 6 of 21 HN58V1001 Series Write Cycle 2 Parameter Symbol Min* Typ Max Unit Address setup time tAS 0 ns Address hold time tAH 150 ns CE to write setup time (WE controlled) tCS 0 ns CE hold time (WE controlled) tCH 0 ns WE to write setup time (CE controlled) tWS 0 ns WE hold time (CE controlled) tWH 0 ns OE to write setup time tOES 0 ns OE hold time tOEH 0 ns Data setup time tDS 100 ns Data hold time tDH 10 ns WE pulse width (WE controlled) tWP 250 ns CE pulse width (CE controlled) tCW 250 ns Data latch time tDL 750 ns Byte load cycle tBLC 1.0 30 µs Byte load window tBL 100 Write cycle time tWC 15* Time to device busy tDB 120 ns Write start time tDW 250* ns tRP 100 µs tRES 1 µs Reset protect time Reset high time* 5 4 Test conditions µs 3 ms Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. Use this device in longer cycle than this value. 3. tWC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 4. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy are used. 5. This parameter is sampled and not 100% tested. 6. A7 to A16 are page addresses and must be same within the page write operation. 7. See AC read characteristics. Rev.8.00, Nov. 28. 2003, page 7 of 21 HN58V1001 Series Timing Waveforms Read Timing Waveform Address tACC CE tOH tCE OE tDF tOE WE High Data Out Data out valid tRR tDFR RES Rev.8.00, Nov. 28. 2003, page 8 of 21 HN58V1001 Series Byte Write Timing Waveform (1) (WE Controlled) tWC Address tCS tAH tCH CE tAS tBL tWP WE tOES tOEH OE tDS tDH Din tDW High-Z RDY/Busy tRP tRES RES VCC Rev.8.00, Nov. 28. 2003, page 9 of 21 tDB High-Z HN58V1001 Series Byte Write Timing Waveform (2) (CE Controlled) Address tWS tAH tBL tWC tCW CE tAS tWH WE tOES tOEH OE tDS tDH Din tDW RDY/Busy tDB High-Z tRP tRES RES VCC Rev.8.00, Nov. 28. 2003, page 10 of 21 High-Z HN58V1001 Series Page Write Timing Waveform (1) (WE Controlled) *6 Address A0 to A16 tAS tAH tBL tWP WE tDL tCS tBLC tWC tCH CE tOEH tOES OE tDH tDS Din RDY/Busy High-Z tDB tRP RES tRES VCC Rev.8.00, Nov. 28. 2003, page 11 of 21 tDW High-Z HN58V1001 Series Page Write Timing Waveform (2) (CE Controlled) *6 Address A0 to A16 tAS CE tAH tBL tCW tDL tWS tBLC tWC tWH WE tOEH tOES OE tDH tDS Din RDY/Busy High-Z tDB tRP RES tRES VCC Rev.8.00, Nov. 28. 2003, page 12 of 21 tDW High-Z HN58V1001 Series Data Polling Timing Waveform Address An An CE WE tOEH tCE *7 tOES OE tDW tOE*7 I/O7 Din X Rev.8.00, Nov. 28. 2003, page 13 of 21 Dout X Dout X tWC HN58V1001 Series Toggle bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from “1” to “0” (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Notes: 1. I/O6 beginning state is “1”. 2. I/O6 ending state will vary. 3. See AC read characteristics. 4. Any location can be used, but the address must be fixed. Toggle bit Waveform Next mode *4 Address tCE *3 CE WE *3 tOE OE tOEH tOES *1 I/O6 Din Dout Dout tWC Rev.8.00, Nov. 28. 2003, page 14 of 21 *2 *2 Dout Dout tDW HN58V1001 Series Software Data Protection Timing Waveform (1) (in protection mode) VCC CE WE tBLC Address 5555 Data AA 5555 AAAA or 2AAA 55 A0 tWC Write address Write data Software Data Protection Timing Waveform (2) (in non-protection mode) VCC tWC CE WE Address Data 5555 AAAA or 2AAA 5555 5555 AAAA or 2AAA 5555 AA 55 80 AA 55 20 Rev.8.00, Nov. 28. 2003, page 15 of 21 Normal active mode HN58V1001 Series Functional Description Automatic Page Write Page-mode write feature allows 1 to 128 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 127 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 µs from the preceding falling edge of WE or CE. When CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Busy Signal RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to VOL after the first write signal. At the end of write cycle, the RDY/Busy signal changes state to high impedance. RES Signal When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn’t provide a latch function. VCC Read inhibit Read inhibit RES Program inhibit Program inhibit WE, WE CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of WE or CE. Rev.8.00, Nov. 28. 2003, page 16 of 21 HN58V1001 Series Write/Erase Endurance and Data Retention Time 4 3 The endurance is 10 cycles in case of the page programming and 10 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page4 programmed less than 10 cycles. Data Protection To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 20 ns or less in program mode. 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. Be careful not to allow noise of a width of more than 20 ns on the control pins. WE CE VIH 0V VIH OE 0V 20 ns max Rev.8.00, Nov. 28. 2003, page 17 of 21 HN58V1001 Series 2. Data Protection at VCC On/Off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state. Note: The EEPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal. VCC CPU RESET * Unprogrammable * Unprogrammable 2.1 Protection by RES The unprogrammable state can be realized by that the CPU’s reset signal inputs directly to the EEPROM’s RES pin. RES should be kept VSS level during VCC on/off. The EEPROM brakes off programming operation when RES becomes low, programming operation doesn’t finish correctly in case that RES falls low during programming operation. RES should be kept high for 15 ms after the last data input. VCC RES Program inhibit WE or CE 1 µs min 100 µs min Rev.8.00, Nov. 28. 2003, page 18 of 21 Program inhibit 15 ms min HN58V1001 Series 3. Software data protection To prevent unintentional programming, this device has the software data protection (SDP) mode. The SDP is enabled by inputting the following 3 bytes code and write data. SDP is not enabled if only the 3 bytes code is input. To program data in the SDP enable mode, 3 bytes code must be input before write data. Address Data 5555 AA ↓ ↓ AAAA or 2AAA 55 ↓ ↓ 5555 A0 ↓ ↓ Write address Write data } Normal data input The SDP mode is disabled by inputting the following 6 bytes code. Note that, if data is input in the SDP disable cycle, data can not be written. Address Data 5555 ↓ AAAA or 2AAA ↓ 5555 ↓ 5555 ↓ AAAA or 2AAA ↓ 5555 AA ↓ 55 ↓ 80 ↓ AA ↓ 55 ↓ 20 The software data protection is not enabled at the shipment. Note: There are some differences between Renesas Technology’s and other company’s for enable/disable sequence of software data protection. If there are any questions , please contact with Rnesas Technology’s sales offices. Rev.8.00, Nov. 28. 2003, page 19 of 21 HN58V1001 Series Package Dimensions HN58V1001FP Series (FP-32D, FP-32DV) Unit: mm 20.45 20.95 Max 17 11.30 32 1 1.27 *0.40 ± 0.08 0.38 ± 0.06 0.10 0.15 M *Dimension including the plating thickness Base material dimension Rev.8.00, Nov. 28. 2003, page 20 of 21 0.12 0.15 +– 0.10 1.00 Max *0.22 ± 0.05 0.20 ± 0.04 3.00 Max 16 14.14 ± 0.30 1.42 0˚ – 8 ˚ 0.80 ± 0.20 Package Code JEDEC JEITA Mass (reference value) FP-32D, FP-32DV Conforms — 1.3 g HN58V1001 Series Package Dimensions (cont.) HN58V1001T Series (TFP-32DA, TFP-32DAV) Unit: mm 8.00 8.20 Max 17 1 16 12.40 32 0.50 0.08 M *Dimension including the plating thickness Base material dimension Rev.8.00, Nov. 28. 2003, page 21 of 21 *0.17 ± 0.05 0.125 ± 0.04 1.20 Max 0.10 0.80 14.00 ± 0.20 0.45 Max 0.13 ± 0.05 *0.22 ± 0.08 0.20 ± 0.06 0˚ – 5˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TFP-32DA, TFP-32DAV Conforms Conforms 0.26 g Revision History Rev. Date HN58V1001 Series Data Sheet Contents of Modification Page Description 0.0 Jul. 11. 1991 Initial issue 1.0 Jan. 30. 1992 HN58V1001P/FP/T/R-20 to HN58V1001P/FP/T/R-25 Low power dissipation 100 µW max (standby) to 110 µW max (standby) Pin Description VCC power: +5 V to +3V Recommended DC Operating Conditions VIH min: 1.9 V to 2.0 V VIH max: VCC+1 V to VCC+0.3 V VH min: VCC-1 V to VCC-0.5 V DC Characteristics ICC3 max: 10 mA to 6 mA 25 mA to 15 mA ICC3 test conditions: cycle = 1 µs/200 ns to cycle = 1 µs/250 ns at VCC = 3.3 V AC Characteristics tACC/tCE max: 200 ns to 250 ns tOE max: 90 ns to 120 ns tDF max: 70 ns to 50 ns tWC min: 10 ms to 15 ms tCS/tCH to tWS/tWH (CE Controlled) tDL min: 300 ns to 750 ns tBLC min: 0.55 µs to 1.0 µs tDW min: 150 ns to 250 ns Functional Description Deletion of Write Protection(2) Change of Data Protection 2 Software data protection Address: AAAA to AAAA or 2AAA Change of Read Timing Waveform 3 4 5 6 16 8 2.0 Feb. 20. 1993 5 6 16 3.0 Apr. 23. 1993 Mode Selection I/O (11-13, 15-19) to I/O (13-15, 17-21) DC Characteristics VIH min: 2.0 V to 1.9 V AC Characteristics tRR max: 450 ns to 600 ns tDH min: 0 ns to 10 ns Deletion of Mode Description Addition of Reset function 5 4 Change of erase/write cycles in page mode: 10 to10 4 3 Change of erase/write cycles in byte mode: 10 to10 Functional Description 10 ms to 15 ms Addition of Toggle Bit Revision Record (cont.) Rev. 4.0 Date Nov.25. 1994 Contents of Modification Page Description 5 Capacitance Addition of note: 1 AC Characteristics Write cycle: Addition of note 2,3 Addition of tDW min: 250 ns Page write timing waveform Addition of note: 1 6 9 5.0 May. 23. 1995 Deletion of HN58V1001R series (TFP-32DAR) 6.0 Apr. 30. 1997 6 Change of format AC Characteristics Addition of note.7 Timing Waveforms Toggle bit Addition of note.3, 4 Functional Description Addition of CPU Reset timing waveform Data protection 3: Addition of note Package Dimensions Change of FP-32D, TFP-32DA 8 16 20 7.0 Oct. 31. 1997 8 8.00 Nov. 28. 2003 2 Timing Waveforms Read Timing Waveform: Correct error Change format issued by Renesas Technology Corp. Ordering Information Deletion of HN58V1001P-25 Addition of HN58V1001FP-25E, HN58V1001T-25E 20-21 Package Dimensions Deletion of DP-32 FP-32D to FP-32D, FP-32DV TFP-32DA to TFP-32DA, TFP-32DAV Sales Strategic Planning Div. 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