12-Bit Serial Input Multiplying DAC AD5441 Preliminary Technical Data FEATURES FUNCTIONAL BLOCK DIAGRAM 3 V to 5 V supply operation True 12-bit accuracy 5 V operation @ <10 μA Fast 3-wire serial input Fast 1 μs settling time 2.4 MHz, 4-quadrant multiply BW Upgrade for DAC8043 and DAC8043A Standard and rotated pinout VDD VREF AD5441 RFB IOUT DAC 12 LD DAC REG 12 APPLICATIONS GND 12-BIT SHIFT REGISTER 06492-001 CLK SRI Figure 1. Ideal for PLC applications in industrial control Programmable amplifiers and attenuators Digitally controlled calibration and filters Motion control systems GENERAL DESCRIPTION TA = –40°C, +25°C, +85°C 0.4 VDD = +5V VREF = –10V 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 06492-002 The circuit consists of a 12-bit serial-in/parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC, and control logic. Serial data is clocked into the input register on the rising edge of the CLOCK pulse. When the new data-word is clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the DAC. 0.5 INL (LSB) The AD5441 is an improved high accuracy 12-bit multiplying digital-to-analog converter (DAC) in space-saving 8-lead packages. Featuring serial input, double buffering, and excellent analog performance, the AD5441 is ideal for applications where PC board space is at a premium. Improved linearity and gain error performance permit reduced part counts through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output. Figure 2. Integral Nonlinearity Error vs. Code Consuming only 10 μA from a single 5 V power supply, the AD5441 is the ideal low power, small size, high performance solution to many application problems. The AD5441 is specified over the extended industrial (−40°C to +125°C) temperature range. It is available in an 8-lead LFCSP and an 8-lead MSOP. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD5441 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications....................................................................................... 1 Terminology .................................................................................... 10 Functional Block Diagram .............................................................. 1 Parameter Definitions.................................................................... 11 General Description ......................................................................... 1 General Circuit Information..................................................... 11 Table of Contents .............................................................................. 2 Output Impedance ..................................................................... 11 Revision History ............................................................................... 2 Applications Information.......................................................... 11 Specifications..................................................................................... 3 Unipolar 2-Quadrant Multiplying ........................................... 11 Electrical Characteristics............................................................. 3 Bipolar 4-Quadrant Multiplying .............................................. 12 Absolute Maximum Ratings............................................................ 4 Interface Logic Information...................................................... 12 ESD Caution.................................................................................. 4 Digital Section ............................................................................ 12 Pin Configurations and Function Descriptions ........................... 5 Outline Dimensions ....................................................................... 13 REVISION HISTORY 3/07—Revision PrA: Preliminary Version Rev. PrA | Page 2 of 16 Preliminary Technical Data AD5441 SPECIFICATIONS ELECTRICAL CHARACTERISTICS @ VDD = 5 V, VREF = 10 V, −40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Temperature Coefficient1 Output Leakage Current N INL DNL GFSE TCGFS ILKG Zero-Scale Error IZSE REFERENCE INPUT Input Resistance Input Capacitance1 ANALOG OUTPUT Output Capacitance1 DIGITAL INPUTS Digital Input Low Digital Input High Input Leakage Current Input Capacitance1 INTERFACE TIMING1, 2 Data Setup Data Hold Clock Width High Clock Width Low Load Pulse Width LD DAC High to MSB CLK High LSB CLK to LD DAC AC CHARACTERISTICS1 Output Current Settling Time DAC Glitch Digital Feedthrough Feedthrough (VOUT/VREF) Total Harmonic Distortion Output Noise Density Multiplying Bandwidth Power Supply Range Positive Supply Current Power Dissipation Power Supply Sensitivity 1 2 Symbol RREF CREF Min tDS tDH tCH tCL tLD tLD1 tASB Max Unit Condition 12 ±1.0 ±1.0 ±2.0 ±5 ±5 ±25 0.03 0.15 Bits LSB LSB LSB ppm/°C nA nA LSB LSB All grades monotonic to 12 bits Data = FFFH IOUT pin measured Data = 000H, IOUT pin measured TA = –40°C, +125°C, Data = 000H, IOUT pin measured Data = 000H TA = −40°C, +125°C, Data = 000H 15 Absolute temperature coefficient < 50 ppm/°C 5 kΩ pF 25 30 pF pF Data = 000H Data = FFFH V V μA pF VLOGIC = 0 V to 5 V VLOGIC = 0 V 7 COUT VIL VIH IIL CIL Typ 0.8 2.4 1 10 10 5 25 25 25 0 0 ns ns ns ns ns ns ns tS Q FT THD en BW VDD RANGE IDD PDISS PSS 1 20 TBD 1 −85 17 2.4 3 5 10 50 0.002 μs nVs To ±0.01% of full-scale, external op amp OP42 Data = 000H to FFFH to 000H, VREF = 0 V mV p-p dB nV/√Hz MHz V μA μW %/% VREF = 20 V p-p, data = 000H, f = 10 kHz VREF = 6 V rms, data = FFFH, f = 1 kHz 10 Hz to 100 kHz between RFB and IOUT −3 dB, VOUT/VREF, VREF = 100 mV rms, data = FFFH VLOGIC = 0 V or VDD VLOGIC = 0 V or VDD ΔVDD = ±5% These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. Rev. PrA | Page 3 of 16 AD5441 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS The AD5441 contains 346 transistors. The die size measures 70.3 mm × 57.1 mm = 4014 square mm. Table 2. Parameter VDD to GND VREF to GND RFB to GND Logic Inputs to GND VIOUT to GND IOUT Short Circuit to GND Package Power Dissipation Thermal Resistance θJA: 8-Lead MSOP θJA: 8-Lead LFCSP1 θJC: 8-Lead MSOP θJC: 8-Lead LFCSP1 Maximum Junction Temperature (TJ max) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec) 1 Rating −0.3 V, +8 V ±18 V ±18 V −0.3 V, VDD + 0.3 V −0.3 V, VDD + 0.3 V 50 mA (TJ max − TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 142°C/W 75°C/W 44°C/W 18°C/W 150°C −40°C to +125°C −65°C to +150°C 300°C Exposed pad soldered to application board. Rev. PrA | Page 4 of 16 Preliminary Technical Data AD5441 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VREF RFB IOUT GND 8 VDD 1 2 3 AD5441 TOP VIEW (Not to Scale) 4 7 CLK 5 SRI VREF 1 8 VDD RFB 2 7 CLK AD5441 SRI TOP VIEW GND 4 (Not to Scale) 5 LD IOUT 3 5 LD 6 Figure 4. 8-Lead MSOP Pin Configuration Figure 3. 8-LeadLFCSP Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic VREF RFB IOUT GND LD 6 7 8 SRI CLK VDD Descriptions DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. Internal Matching Feedback Resistor. Connect to external op amp output. DAC Current Output, full-scale output 1 LSB less than reference input voltage −VREF. Analog and Digital Ground. Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low. See Table 4 for operation. 12-Bit Serial Register Input, data loads directly into the shift register MSB first. Extra leading bits are ignored. Clock Input, positive-edge clocks data into shift register. Positive Power Supply Input. Specified range of operation 5 V ± 10%. Rev. PrA | Page 5 of 16 AD5441 Preliminary Technical Data D11 SRI D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK tLD1 tASB LD DATA LOADED MSB(D11) FIRST Dxx SRI tDS CLK DAC REGISTER LOAD tDH tCL tCH tLD LD ±1LSB ERROR BAND VOUT ZS 06492-005 tS FS Figure 5. Timing Diagram Table 4. Control-Logic Truth Table CLK LD Serial Shift Register Function DAC Register Function ↑1 H or L L H Shift-register-data advanced one bit Latched No effect No effect Updated with current shift register contents Latched all 12 bits 1 ↑ L ↑ 1 equals positive logic transition. Rev. PrA | Page 6 of 16 Preliminary Technical Data AD5441 TYPICAL PERFORMANCE CHARACTERISTICS 35 10 SS = 200 UNITS TA = 25°C VDD = 5V VREF = 10V 30 1 25 FREQUENCY VDD = 5V VLOGIC = 0V OR VDD IDD (µA) 20 15 10 0.1 0.01 0.5 –0.5 0 TOTAL UNADJUSTED ERROR (LSB) 0.001 –55 06492-006 0 –1.0 1.0 –35 Figure 6. Total Unadjusted Error Histogram SS = 200 UNITS TA = –40°C TO +85°C VDD = 5V VREF = 10V 40 5 25 45 65 TEMPERATURE (°C) 85 105 125 Figure 9. Supply Current IDD vs. Temperature 3500 50 –15 06492-009 5 3000 VDD = 5V VREF = 10V TA = 25°C 2500 IDD (µA) FREQUENCY CODE = 0xF55 30 2000 1500 CODE = 0x800 20 1000 CODE = 0xFFF 10 1 FULL SCALE TEMPCO (ppm/°C) 2 100 10M 100M ΔVDD = 5V ± 10% TA = 25°C VDD = 5V 0.4 PSRR (dB) 80 0.3 60 0.2 40 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 LOGIC INPUT VOLTAGE (V) 4.0 4.5 5.0 20 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 11. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 8. Supply Current IDD vs. Logic Input Voltage Rev. PrA | Page 7 of 16 06492-011 0.1 06492-008 SUPPLY CURRENT I DD (mA) 100k 1M FREQUENCY (Hz) Figure 10. Supply Current IDD vs. Clock Frequency Figure 7. Full-Scale Output Temperature Coefficient Histogram 0.5 10k 06492-010 0 0 1k 06492-007 0 500 AD5441 0.5 Preliminary Technical Data VDD = 5V VREF = 10V SUPERIMPOSED: TA = –40°C, +25°C, +85°C 0.4 VDD = 5V VREF = 10V TA = 25°C 5V CLK (5V/DIV) 0.3 DNL (LSB) 0.2 0.1 0 –0.1 VOUT (5V/DIV) –0.2 –0.3 3072 3584 4096 TIME (1µs/DIV) Figure 12. Linearity Error vs. Digital Code 2 0 –2 12 24 36 48 60 72 84 96 –4 –2000 –1000 0 1000 OP AMP OFFSET VOS (µV) 2000 Figure 13. Linearity Error vs. External Op Amp Offset VOS VOUT (10mV/DIV) 06492-013 ALL BITS OFF 100 1k 10k 100k FREQUENCY (Hz) 1M 108 10M Figure 16. Reference Multiplying Bandwidth vs. Frequency and Code VDD = 5V VREF = 10V fCLK = 2.5MHz CODE: 0x7FF TO 0x800 VDD = 5V TA = 25°C 0.50 INL (LSB) 0.25 LD (5V/DIV) 0 –0.25 –0.50 20mV TIME (200ns/DIV) 06492-014 INL (LSB) 0 ALL BITS ON (MSB) B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 (LSB) B0 VDD = 5V VREF = 10V TA = 25°C DATA BITS ON (ALL OTHER DATA BITS OFF) 4 Figure 15. Large Signal Settling Time ATTENUATION (dB) 1536 2560 2048 CODE (Decimal) 0 5 |VREF | (V) Figure 17. Linearity Error vs. Reference Voltage Figure 14. Midscale Transition Performance Rev. PrA | Page 8 of 16 10 06492-016 1024 512 06492-017 0 06492-012 –0.5 06492-015 5V –0.4 Preliminary Technical Data THD (dB) CODE = 0xFFF 0.6 –75 0.0180 –80 0.0100 –85 0.0056 –90 0.0032 THD (%) VREF = 4V p-p OUTPUT OP AMP: OP42 1.0 0.8 0.0320 –70 SAMPLE SIZE = 50 CODE = 0x000 0.2 0 0 100 200 300 400 HOURS OF OPERATION AT 150°C 500 600 –95 10 Figure 18. Long-Term Drift Accelerated by Burn-In 100 1k 10k FREQUENCY (Hz) Figure 19. THD vs. Frequency Rev. PrA | Page 9 of 16 0.0018 100k 06492-019 0.4 06492-018 NOMINAL CHANGE IN VOLTAGE (mV) 1.2 AD5441 AD5441 Preliminary Technical Data TERMINOLOGY Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of the full-scale reading. Digital Feedthrough When the device is not selected, high frequency logic activity on the device’s digital inputs may be capacitively coupled through the device and produce noise on the IOUT pins. This noise is coupled from the outputs of the device onto follow-on circuitry. This noise is digital feedthrough. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded to the DAC. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF − 1 LSB. Gain error of the DACs is adjustable to zero with external resistance. Zero Scale Error Calculated from worst-case RREF: IZSE(LSB) = (RREF × ILKG × 4096)/VREF. Output Leakage Current Output leakage current is the current that flows into the DAC ladder switches when they are turned off. For the IOUT terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT current. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics, such as second to fifth, are included. THD = 20 log V2 2 + V32 + V4 2 + V5 2 V1 Compliance Voltage Range The maximum range of (output) terminal voltage for which the device will provide the specified characteristics. Output Noise Spectral Density Calculation from en = √4KTRB Output Capacitance Capacitance from IOUT1 to AGND. where: Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s, depending on whether the glitch is measured as a current or voltage signal. R = Resistance (Ω) K = Boltzmann Constant (J/°K) T = Resistor temperature (°K) B = 1 Hz bandwidth Rev. PrA | Page 10 of 16 Preliminary Technical Data AD5441 PARAMETER DEFINITIONS GENERAL CIRCUIT INFORMATION OUTPUT IMPEDANCE The AD5441 is a 12-bit multiplying DAC with a low temperature coefficient. It contains an R-2R resistor ladder network, data input and control logic, and two data registers. The AD5441’s output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT terminal, may be between 10 kΩ, the feedback resistor alone when all digital inputs are low, and 7.5 kΩ, the feedback resistor in parallel with approximate 30 kΩ of the R-2R ladder network resistance when any single bit logic is high. Static accuracy and dynamic performance will be affected by these variations. The digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift register and then transferred, in parallel, to the 12-bit DAC register. The analog portion of the AD5441 contains an inverted R-2R ladder network consisting of silicon-chrome, highly stable (50 ppm/°C), thin-film resistors, and 12 pairs of NMOS current-steering switches, see Figure 20. These switches steer binarily weighted currents into either IOUT or GND; this yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resistance at VREF equal to R. The VREF input may be driven by any reference voltage or current, ac or dc that is within the limits stated in the Absolute Maximum Ratings. VREF 10kΩ 10kΩ 10kΩ 20kΩ 20kΩ 20kΩ 20kΩ 20kΩ S1 S2 S3 S12 * APPLICATIONS INFORMATION In most applications, linearity depends upon the potential of the IOUT and GND pins being at the same voltage potential. The DAC is connected to an external precision op amp inverting input. The external amplifiers noninverting input should be tied directly to ground without the usual bias current compensating resistor (see Figure 21 and Figure 22). The selected amplifier should have a low input bias current and low drift over temperature. The amplifiers input offset voltage should be nulled to less than 200 mV (less than 10% of 1 LSB). All grounded pins should tie to a single common ground point to avoid ground loops. The VDD power supply should have a low noise level with adequate bypassing. It is best to operate the AD5441 from the analog power supply and grounds. GND * BIT 1 (MSB) BIT 2 BIT 3 DIGITAL INPUTS UNIPOLAR 2-QUADRANT MULTIPLYING IOUT RFEEDBACK BIT 12 (LSB) NOTES 1. SWITCHES SHOWN FOR DIGITAL INPUTS HIGH. 06492-021 *THESE SWITCHES PERMANENTLY ON. The most straightforward application of the AD5441 is in the 2-quadrant multiplying configuration shown in Figure 21. If the reference input signal is replaced with a fixed dc voltage reference, the DAC output will provide a proportional dc voltage output according to the transfer equation VOUT = −D/4096 × VREF Figure 20. Simplified DAC Circuit The 12 output current steering NMOS FET switches are in series with each R-2R resistor. where: To further ensure accuracy across the full temperature range, permanently on MOS switches were included in series with the feedback resistor and the R-2R ladder’s terminating resistor. Figure 20 shows the location of the series switches. During any testing of the resistor ladder or RFEEDBACK (such as incoming inspection), VDD must be present to turn on these series switches. VREF is the externally applied reference voltage source. D is the decimal data loaded into the DAC register. VDD R2 VDD VREF R1 VREF LD C1 RFB AD5441 CLK IOUT1 A1 GND VOUT = 0 TO –VREF SRI AGND μCONTROLLER NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER. Figure 21. Unipolar (2-Quadrant) Operation Rev. PrA | Page 11 of 16 04587-009 10kΩ AD5441 Preliminary Technical Data BIPOLAR 4-QUADRANT MULTIPLYING INTERFACE LOGIC INFORMATION Figure 22 shows a suggested circuit to achieve 4-quadrant multiplying operation. The summing amplifier multiplies VOUT1 by 2 and offsets the output with the reference voltage so that a midscale digital input code of 2048 places VOUT2 at 0 V. The negative full-scale voltage will be VREF when the DAC is loaded with all zeros. The positive full-scale output will be −(VREF − 1 LSB) when the DAC is loaded with all ones. Therefore, the digital coding is offset binary. The voltage output transfer equation for various input data and reference (or signal) values follows The AD5441 has been designed for ease of operation. The timing diagram in Figure 5 illustrates the input register loading sequence. Note that the most significant bit (MSB) is loaded first. Once the 12-bit input register is full, the data is transferred to the DAC register by taking LD momentarily low. VOUT2 = (D/2048 − 1) − VREF where: D is the decimal data loaded into the DAC register. VREF is the externally applied reference voltage source. R3 20kΩ VDD VDD R1 VREF LD C1 RFB AD5441 CLK IOUT1 A1 GND R4 10kΩ A2 VOUT = –VREF TO +VREF SRI AGND μCONTROLLER VDD 04587-010 NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER. The AD5441’s digital inputs, SRI, LD, and CLK, are TTL compatible. The input voltage levels affect the amount of current drawn from the supply; peak supply current occurs as the digital input (VIN) passes through the transition region. See Figure 8 for the supply current vs. logic input voltage graph. Maintaining the digital input voltage levels as close as possible to the supplies, VDD and GND, minimizes supply current consumption. The AD5441’s digital inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 23 shows the input protection diodes and series resistor; this input structure is duplicated on each digital input. High voltage static charges applied to the inputs are shunted to the supply and ground rails through forward-biased diodes. These protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions. LD, CLK, SRI 5kΩ Figure 22. Bipolar (4-Quadrant) Operation GND Figure 23. Digital Input Protection Rev. PrA | Page 12 of 16 06492-020 VREF ±10V R5 20kΩ R2 DIGITAL SECTION Preliminary Technical Data AD5441 OUTLINE DIMENSIONS 3.25 3.00 2.75 1.95 1.75 1.55 0.25 0.20 0.15 8 EXPOSEDPAD 0.60 0.45 0.30 4 BOTTOM VIEW 2.95 2.75 2.55 0.15 0.10 0.05 1 0.50 BSC 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 031207-A 1.00 0.85 0.80 5 2.25 2.00 1.75 TOP VIEW PIN 1 INDICATOR 1.89 1.74 1.59 0.55 0.40 0.30 0.20 REF Figure 24. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] (CP-8-1) Dimensions are shown in millimeters 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5 5.15 4.90 4.65 4 PIN 1 0.65 BSC 0.95 0.85 0.75 0.15 0.00 1.10 MAX 0.38 0.22 COPLANARITY 0.10 0.23 0.08 8° 0° 0.80 0.60 0.40 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 25. 8-Lead Mini Small Outline Package [MINI_SO] (RM-8) Dimensions are shown in millimeters Rev. PrA | Page 13 of 16 AD5441 Preliminary Technical Data NOTES Rev. PrA | Page 14 of 16 Preliminary Technical Data AD5441 NOTES Rev. PrA | Page 15 of 16 AD5441 Preliminary Technical Data NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06492-0-3/07(PrA) Rev. PrA | Page 16 of 16