AD ADG1204

FEATURES
FUNCTIONAL BLOCK DIAGRAM
2 pF off capacitance
1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at +12 V, ±15 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
14-lead TSSOP and 12-lead LFCSP
Typical power consumption: <0.03 µW
ADG1204
S1
S2
D
S3
S4
1 OF 4
DECODER
A0
A1
EN
04779-0-001
Preliminary Technical Data
2 pF Off Capacitance, 1 pC Charge Injection,
±15 V/12 V 4:1 iCMOS™ Multiplexer
ADG1204
Figure 1.
APPLICATIONS
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1204 is a CMOS analog multiplexer, comprising four
single channels designed on an iCMOS process. iCMOS
(industrial-CMOS) is a modular manufacturing process that
combines high voltage CMOS (complementary metal-oxide
semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 30-V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike
analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages, while providing
increased performance, dramatically lower power consumption,
and reduced package size.
The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching. iCMOS construction ensures ultralow power dissipation, making the parts
ideally suited for portable and battery powered instruments.
The ADG1204 switches one of four inputs to a common output,
D, as determined by the 3-bit binary address lines, A0, A1, and
EN. Logic 0 on the EN pin disables the device. Each switch
conducts equally well in both directions when on, and has an
input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All switches
exhibit break-before-make switching action. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
2 pF off capacitance (±15 V supply).
1 pC charge injection.
3 V logic-compatible digital inputs:
VIH = 2.0 V, VIL = 0.8 V
No VL logic power supply required.
Ultralow power dissipation: <0.03 µW.
14-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP package.
Rev. PrD
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infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADG1204
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Pin Configurations and Function Descriptions ............................8
Dual Supply ................................................................................... 3
Terminology .......................................................................................9
Single Supply ................................................................................. 5
Typical Performance Characteristics ........................................... 10
Absolute Maximum Ratings............................................................ 7
Test Circuits..................................................................................... 13
Truth Table .................................................................................... 7
Outline Dimensions ....................................................................... 15
ESD Caution.................................................................................. 7
Ordering Guide .......................................................................... 15
REVISION HISTORY
11/04—Revision PrD: Preliminary Version
Rev. PrD | Page 2 of 16
Preliminary Technical Data
ADG1204
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
25°C
85°C
Y Version1
Unit
120
160
VDD to VSS
180
V
Ω typ
Ω max
Ω typ
On Resistance Match between
Channels (∆RON)
5
On Resistance Flatness (RFLAT(ON))
25
50
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINLor INH
±0.01
±0.5
±0.01
±0.5
±0.04
±1
±1
±5
±1
±5
±2
±5
2.0
0.8
0.005
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS
5
40
tON (EN)
40
tOFF (EN)
20
Break-before-Make Time Delay, tD
15
90
40
1
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
1
75
85
0.002
700
2
7
4
0.001
5.0
IDD
150
300
ISS
0.001
5.0
Rev. PrD | Page 3 of 16
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
µA typ
µA max
Test Conditions/Comments
VS = ±10 V, IS = −10 mA; Figure 21
VS = ±10 V, IS = −10 mA
VS = −5 V, 0 V, +5 V; IS = −10 mA
VDD = +10 V, VSS = −10 V
VS = 0 V/10 V, VD = 10 V/0 V; Figure 22
VS = 0 V/10 V, VD = 10 V/0 V; Figure 22
VS = VD = 0 V or 10 V; Figure 23
VIN = VINL or VINH
RL = 50 Ω, CL = 35 pF
VS = ±10 V; Figure 24
RL = 50 Ω, CL = 35 pF
VS = ±10 V; Figure 24
RL = 50 Ω, CL = 35 pF
VS = ±10 V; Figure 24
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 10 V; Figure 25
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
RL = 600 Ω, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; Figure 29
VDD = +16.5 V, VSS = −16.5 V
Digital Inputs = 0 V or VDD
Digital Inputs = 5 V
Digital Inputs = 0 V or VDD
ADG1204
Parameter
IGND
Preliminary Technical Data
25°C
0.001
85°C
Y Version1
5.0
IGND
150
300
1
2
Unit
µA typ
µA max
µA typ
µA max
Test Conditions/Comments
Digital Inputs = 0 V or VDD
Digital Inputs = 5 V
Y Version temperature range is −40°C to +125°C.
Guaranteed by design, not subject to production test.
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
25°C
85°C
Y Version1
Unit
VSS to VDD
V
Ω typ
Ω max
Ω typ
220
On Resistance Match between
Channels (∆RON)
10
On Resistance Flatness (RFLAT(ON))
30
Ω max
Ω typ
Ω max
±0.01
±0.5
±0.01
±0.5
±0.04
±1
nA typ
nA max
nA typ
nA max
nA typ
nA max
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
±1
±5
±1
±5
±2
±5
2.0
0.8
0.005
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
5
160
tOFF
60
Break-before-Make Time Delay, tD
50
Charge Injection
20
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
56
60
20
15
1
100
Rev. PrD | Page 4 of 16
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
Test Conditions/Comments
VS = ±3.3 V, IS = −10 mA; Figure 21
VS = ±3.3 V, IS = −10 mA
VS = ±3.3 V, IS = −10 mA
VDD = 5.5 V, VSS = −5.5 V
VD = ±4.5 V, VS = ±4.5 V; Figure 22
VD = ±4.5 V, VS = ±4.5 V; Figure 22
VD = VS = ±4.5 V; Figure 23
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS = 3 V; Figure 24
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V; Figure 25
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
RL = 50 Ω, CL = 5 pF; Figure 29
f = 1 MHz
f = 1 MHz
f = 1 MHz
Preliminary Technical Data
Parameter
POWER REQUIREMENTS
IDD
25°C
ADG1204
Y Version1
85°C
0.001
µA typ
µA max
µA typ
µA max
5.0
ISS
0.001
5.0
1
2
Unit
Test Conditions/Comments
VDD = +5.5 V, VSS = −5.5 V
Digital Inputs = 0 V or 5.5 V
Digital Inputs = 0 V or 5.5 V
Y Version temperature range is −40°C to +125°C.
Guaranteed by design, not subject to production test.
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
25°C
On Resistance Match between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
1
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
85°C
Y Version1
Unit
0 V to VDD
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
220
12
±0.01
±0.5
±0.01
±0.5
±0.04
±1
±1
±5
±1
±5
±2
±5
2.0
0.8
0.001
±0.5
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS
5
40
tON (EN)
50
tOFF (EN)
15
Break-before-Make Time Delay, tD
15
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
CD (Off)
CD, CS (On)
5
75
85
700
2
2
4
1
Rev. PrD | Page 5 of 16
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
Test Conditions/Comments
VS = 10 V, IS = −10 mA; Figure 21
VS = 10 V, IS = −10 mA
VS = 3 V, 6 V, 9 V; IS = −10 mA
VDD = 12 V
VS = 1 V/10 V, VD = 10 V/1 V; Figure 22
VS = 1 V/10 V, VD = 10 V/1 V; Figure 22
VS = VD = 1 V or 10 V; Figure 23
VIN = VINL or VINH
RL = 50 Ω, CL = 35 pF
VS = ±10 V; Figure 24
RL = 50 Ω, CL = 35 pF
VS = 8 V; Figure 24
RL = 50 Ω, CL = 35 pF
VS = 8 V; Figure 24
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 8 V; Figure 25
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 28
RL = 50 Ω, CL = 5 pF; Figure 29
ADG1204
Parameter
POWER REQUIREMENTS
IDD
Preliminary Technical Data
25°C
85°C
Y Version1
0.001
5.0
IDD
150
300
1
2
Y Version temperature range is −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. PrD | Page 6 of 16
Unit
µA typ
µA max
µA typ
µA max
Test Conditions/Comments
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Preliminary Technical Data
ADG1204
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs
Peak Current, S or D
Continuous Current, S or D
Operating Temperature Range
Industrial (B Version)
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
14-Lead TSSOP, θJA Thermal
Impedance
12-Lead LFCSP, θJA Thermal
Impedance
Lead Temperature, Soldering
Vapor Phase (60 s)
Infrared (15 s)
1
Rating
38 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
100 mA (pulsed at 1 ms, 10%
duty cycle max)
30 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
TRUTH TABLE
Table 5.
EN
0
1
1
1
1
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
150°C
150.4°C/W
A1
X
0
0
1
1
A0
X
0
1
0
1
S1
Off
On
Off
Off
Off
30.4°C/W
215°C
220°C
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrD | Page 7 of 16
S2
Off
Off
On
Off
Off
S3
Off
Off
Off
On
Off
S4
Off
Off
Off
Off
On
ADG1204
Preliminary Technical Data
14 A1
2
13 GND
VSS
3
S1
4
S2
ADG1204
12 VDD
10 A1
1
11 A0
A0
EN
12 EN
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
9 GND
ADG1204
8 VDD
D
6
9
NC
S2 3
TOP VIEW
(Not to Scale)
7 S3
NC
7
8
NC
NC = NO CONNECT
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
11
2
12
Mnemonic
A0
EN
3
4
5
6
7–9
10
11
12
13
14
VSS
S1
S2
D
NC
S4
S3
VDD
GND
A1
1
2
3
4
5
6
7
8
9
10
Function
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
Most Negative Power Supply Potential.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
No Connection.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Rev. PrD | Page 8 of 16
04779-0-003
S1 2
S4 6
10 S4
D 4
5
NC 5
VSS 1
04779-0-002
11 S3
TOP VIEW
Preliminary Technical Data
ADG1204
TERMINOLOGY
IDD
The positive supply current.
CD, CS (On)
The on switch capacitance, which is measured with reference to
ground.
ISS
The negative supply current.
CIN
The digital input capacitance.
VD (VS)
The analog voltage on Terminals D and S.
tON (EN)
The delay between applying the digital control input and the
output switching on. See Figure 24, Test Circuit 4.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
tOFF (EN)
The delay between applying the digital control input and the
output switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID, IS (On)
The channel leakage current with the switch on.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINL
The maximum input voltage for Logic 0.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
VINH
The minimum input voltage for Logic 1.
On Response
The frequency response of the on switch.
IINL (IINH)
The input current of the digital input.
Insertion Loss
The loss due to the on resistance of the switch.
CS (Off)
The off switch source capacitance, which is measured with
reference to ground.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
tTRANS
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
Rev. PrD | Page 9 of 16
ADG1204
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. On Resistance as a Function of VD (VS) for Single Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 9. Leakage Currents as a Function of VD (VS)
Rev. PrD | Page 10 of 16
Preliminary Technical Data
ADG1204
Figure 10. Leakage Currents as a Function of VD (VS)
Figure 13. Leakage Currents as a Function of Temperature
Figure 11. Leakage Currents as a Function of VD (VS)
Figure 14. Supply Currents vs. Input Switching Frequency
Figure 12. Leakage Currents as a Function of Temperature
Figure 15. Charge Injection vs. Source Voltage
Rev. PrD | Page 11 of 16
ADG1204
Preliminary Technical Data
Figure 16. tON/tOFF Times vs. Temperature
Figure 19. On Response vs. Frequency
Figure 17. Off Isolation vs. Frequency
Figure 20. THD + N vs. Frequency
Figure 18. Crosstalk vs. Frequency
Rev. PrD | Page 12 of 16
Preliminary Technical Data
ADG1204
TEST CIRCUITS
V
VS
VD
VDD VSS
A0
+2.4V
A
VD
Figure 23. Test Circuit 3—On Leakage
0.1µF
ADDRESS
DRIVE (VIN)
S1
S2
S3
S4
A1
D
NC = No Connect
Figure 22. Test Circuit 2—Off Leakage
VDD VSS
VS
S
NC
A
VS
Figure 21. Test Circuit 1—On Resistance
0.1µF
D
EN
VS1
VS4
3V
50%
90%
VOUT
D
50%
0V
90%
VOUT
GND
RL
50Ω
tTRANSITION
CL
35pF
tTRANSITION
04779-0-023
04779-0-020
IDS
ID (ON)
ID (OFF)
S
A
04779-0-022
D
04779-0-021
IS (OFF)
S
Figure 24. Test Circuit 4—Address to Output Switching Times
VDD VSS
0.1µF
VDD VSS
S1
S2
S3
S4
A1
VS
50Ω
+2.4V
A0
EN
ADDRESS
DRIVE (VIN)
VS1
D
VOUT
GND
RL
50Ω
3V
0V
VOUT
CL
35pF
80%
80%
04779-0-024
0.1µF
tBBM
Figure 25. Test Circuit 5—Break-before-Make Time
VDD VSS
0.1µF
ENABLE
DRIVE (VIN)
VDD VSS
S1
S2
S3
S4
A1
A0
VS
3V
50%
V0
OUTPUT
EN
VS
D
GND
50Ω
VOUT
RL
50Ω
0.9V0
0.9V0
0V
CL
35pF
Delay.
Figure 26. Test Circuit 6—Enable to Output Switching Delay
Rev. PrD | Page 13 of 16
50%
0V
tON(EN)
tOFF(EN)
04779-0-025
0.1µF
ADG1204
Preliminary Technical Data
VDD
VSS
VDD
VSS
S
D
VOUT
RS
∆VOUT
QINJ = CL × ∆VOUT
VOUT
VIN
CL
1nF
VS
SW OFF
SW OFF
SW ON
DECODER
GND
SW ON
SW OFF
04779-0-026
VIN
A1 A2
SW OFF
EN
Figure 27. Test Circuit 7— Charge Injection
VDD
VSS
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
S
VOUT
VSS
VDD
VSS
0.1µF
S1
RL
50Ω
50Ω
50Ω
VDD
0.1µF
D
VS
S2
R
50Ω
D
VS
GND
OFF ISOLATION = 20 LOG
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
Figure 28. Test Circuit 8—Off Isolation
VDD
04779-0-029
GND
VOUT
04779-0-027
RL
50Ω
VOUT
VS
Figure 30. Test Circuit 10—Channel-to-Channel Crosstalk
VSS
0.1µF
0.1µF
VDD
VDD
VSS
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
AUDIO PRECISION
VDD
50Ω
RS
VS
S
D
RL
50Ω
GND
VSS
IN
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
04779-0-028
VIN
INSERTION LOSS = 20 LOG
VS
V p-p
D
Figure 29. Test Circuit 9—Bandwidth
RL
600Ω
VOUT
GND
Figure 31. Test Circuit 11—THD + Noise
Rev. PrD | Page 14 of 16
04779-0-030
S
Preliminary Technical Data
ADG1204
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65
BSC
1.05
1.00
0.80
0.20
0.09
1.20
MAX
0.15
0.05
0.30
0.19
SEATING
COPLANARITY
PLANE
0.10
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimension shown in millimeters
3.00
BSC SQ
0.60 MAX
0.45
PIN 1
INDICATOR
0.75
0.55
0.35
9
2.75
BSC SQ
TOP
VIEW
10 11 12
8
12 MAX
1.00
0.85
0.80
*1.45
1
1.30 SQ
1.15
2
7
6
EXPOSED PAD
(BOTTOM VIEW)
PIN 1
INDICATOR
5
4
3
0.25 MIN
0.50
BSC
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 33. 12-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
ADG1204YRU
ADG1204YCP
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Rev. PrD | Page 15 of 16
Package Option
RU-14
CP-12-1
ADG1204
Preliminary Technical Data
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04779–0–11/04(PrD)
Rev. PrD | Page 16 of 16