High Performance, Digital Output Gyroscope ADXRS453 FEATURES GENERAL DESCRIPTION Complete rate gyroscope on a single chip ±300°/sec angular rate sensing Ultrahigh vibration rejection: 0.01°/sec/g Excellent 16°/hour null bias stability Internal temperature compensation 2000 g powered shock survivability SPI digital output with 16-bit data-word Low noise and low power 3.3 V to 5 V operation −40°C to +105°C operation Ultrasmall, light, and RoHS compliant Two package options Low cost SOIC_CAV package for yaw rate (z-axis) response Innovative ceramic vertical mount package (LCC_V), which can be oriented for pitch, roll, or yaw response The ADXRS453 is an angular rate sensor (gyroscope) intended for industrial, instrumentation, and stabilization applications in high vibration environments. An advanced, differential, quad sensor design rejects the influence of linear acceleration, enabling the ADXRS453 to offer high accuracy rate sensing in harsh environments where shock and vibration are present. APPLICATIONS The ADXRS453 is available in a 16-lead plastic cavity SOIC (SOIC_CAV) and an SMT-compatible vertical mount package (LCC_V), and is capable of operating across a wide voltage range (3.3 V to 5 V). The ADXRS453 uses an internal, continuous self-test architecture. The integrity of the electromechanical system is checked by applying a high frequency electrostatic force to the sense structure to generate a rate signal that can be differentiated from the baseband rate data and internally analyzed. The ADXRS453 is capable of sensing an angular rate of up to ±300°/sec. Angular rate data is presented as a 16-bit word that is part of a 32-bit SPI message. Rotation sensing in high vibration environments Rotation sensing for industrial and instrumentation applications High performance platform stabilization FUNCTIONAL BLOCK DIAGRAM HIGH VOLTAGE GENERATION PDD ADXRS453 LDO REGULATOR HV DRIVE Z-AXIS ANGULAR RATE SENSOR Q DAQ P DAQ 12-BIT ADC DECIMATION FILTER DEMOD TEMPERATURE CALIBRATION FAULT DETECTION Q FILTER REGISTERS/MEMORY ARITHMETIC LOGIC UNIT CLOCK PHASEDIVIDER LOCKED LOOP AMPLITUDE DETECT BAND-PASS FILTER DVDD AVDD SPI INTERFACE MOSI MISO SCLK CS DVSS SELF-TEST CONTROL PSS EEPROM AVSS 09155-001 CP5 VX Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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ADXRS453 TABLE OF CONTENTS Features .............................................................................................. 1 Application Circuits ................................................................... 12 Applications ....................................................................................... 1 ADXRS453 Signal Chain Timing ............................................. 13 General Description ......................................................................... 1 SPI Communication Protocol ....................................................... 14 Functional Block Diagram .............................................................. 1 Command/Response ................................................................. 14 Revision History ............................................................................... 2 Device Data Latching ................................................................. 15 Specifications..................................................................................... 3 SPI Timing Characteristics ....................................................... 16 Absolute Maximum Ratings............................................................ 4 Command/Response Bit Definitions....................................... 17 Thermal Resistance ...................................................................... 4 Fault Register Bit Definitions ................................................... 18 Rate Sensitive Axis ....................................................................... 4 Recommended Start-Up Sequence with CHK Bit Assertion . 20 ESD Caution .................................................................................. 4 Rate Data Format............................................................................ 21 Pin Configurations and Function Descriptions ........................... 5 Memory Map and Registers .......................................................... 22 Typical Performance Characteristics ............................................. 7 Memory Map .............................................................................. 22 Theory of Operation ........................................................................ 9 Memory Register Definitions ................................................... 23 Continuous Self-Test .................................................................... 9 Package Orientation and Layout Information ............................ 25 Mechanical Performance ............................................................... 10 Solder Profile............................................................................... 27 Noise Performance ......................................................................... 11 Package Marking Codes ............................................................ 28 Applications Information .............................................................. 12 Outline Dimensions ....................................................................... 29 Calibrated Performance ............................................................. 12 Ordering Guide .......................................................................... 30 Mechanical Considerations for Mounting .............................. 12 REVISION HISTORY 1/11—Revision 0: Initial Version Rev. 0 | Page 2 of 32 ADXRS453 SPECIFICATIONS TA = TMIN to TMAX, PDD = 5 V, angular rate = 0°/sec, bandwidth = f0/200 (~77.5 Hz), ±1 g, continuous self-test on. Table 1. Parameter MEASUREMENT RANGE SENSITIVITY Nominal Sensitivity Sensitivity Tolerance Nonlinearity 1 Cross-Axis Sensitivity 2 NULL ACCURACY NOISE PERFORMANCE Rate Noise Density LOW-PASS FILTER Cutoff (−3 dB) Frequency Group Delay 3 SENSOR RESONANT FREQUENCY SHOCK AND VIBRATION IMMUNITY Sensitivity to Linear Acceleration Vibration Rectification SELF-TEST Magnitude Fault Register Threshold Sensor Data Status Threshold Frequency ST Low-Pass Filter Cutoff (−3 dB) Frequency Group Delay3 SPI COMMUNICATIONS Clock Frequency Voltage Input High Voltage Input Low Voltage Output Low Voltage Output High Pull-Up Current MEMORY REGISTERS Temperature Register Value at 45°C Scale Factor Quadrature, Self-Test, and Rate Registers Scale Factor POWER SUPPLY Supply Voltage Quiescent Supply Current Turn-On Time Test Conditions/Comments Full-scale range See Figure 2 Symbol FSR Min ±300 Typ Max ±400 80 Unit °/sec TA = 25°C TA = −40°C to +105°C ±0.4 ±0.5 LSB/°/sec % % FSR rms % °/sec °/sec TA = 25°C TA = 105°C 0.015 0.023 °/sec/√Hz °/sec/√Hz TA = −40°C to +105°C Best fit straight line −3 +3 0.05 −3 f0/200 f = 0 Hz fLP tLP f0 3.25 13 DC to 5 kHz +3 77.5 4 15.5 4.75 19 0.01 0.0002 Hz ms kHz °/sec/g °/sec/g2 See the Continuous Self-Test section 2559 Compared to LOCSTx register data Compared to LOCSTx register data f0/32 2239 1279 fST 2879 3839 485 f0/8000 52 1.95 64 8.08 PDD + 0.3 PDD × 0.15 0.5 0.85 × PDD −0.3 MOSI, CS, SCLK MOSI, CS, SCLK MISO, current = 3 mA MISO, current = −2 mA CS, PDD = 3.3 V, CS = PDD × 0.15 CS, PDD = 5 V, CS = PDD × 0.15 76 PDD − 0.5 60 80 200 300 LSB LSB LSB Hz Hz ms MHz V V V V μA μA See the Memory Register Definitions section PDD IDD Maximum limit is guaranteed by Analog Devices, Inc., characterization. Cross-axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB). 3 Minimum and maximum limits are guaranteed by design. 2 Rev. 0 | Page 3 of 32 LSB LSB/°C 80 LSB/°/sec 3.15 Power-on to 0.5°/sec of final value 1 0 5 6.0 100 5.25 8.0 V mA ms ADXRS453 ABSOLUTE MAXIMUM RATINGS RATE SENSITIVE AXIS Table 2. The ADXRS453 is available in two package options. Rating • 2000 g 2000 g −0.3 V to +6.0 V Indefinite • −55°C to +125°C −40°C to +125°C The SOIC_CAV package is for applications that require z-axis (yaw) rate sensing. The LCC_V (vertical mount) package is for applications that require x-axis or y-axis (pitch or roll) rate sensing and for applications that require z-axis (yaw) rate sensing. The package has leads on two faces such that it can be mounted vertically for pitch or roll sensing or horizontally for yaw sensing. See Figure 2 for details. −65°C to +150°C −40°C to +150°C RATE AXIS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. + 16 9 SOIC PACKAGE ESD CAUTION Table 3. Thermal Resistance Package Type 16-Lead SOIC_CAV (RG-16-1) 14-Lead Ceramic LCC_V (EY-14-1)1 1 θJA 191.5 185.5 θJC 25 23 RATE AXIS + LCC_V PACKAGE Figure 2. Rate Signal Increases with Clockwise Rotation THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, for a device soldered in a printed circuit board (PCB) for surface-mount packages. Z-AXIS 09155-002 Parameter Acceleration (Any Axis, 0.5 ms) Unpowered Powered Supply Voltage (PDD) Output Short-Circuit Duration (Any Pin to Ground) Operating Temperature Range LCC_V Package SOIC_CAV Package Storage Temperature Range LCC_V Package SOIC_CAV Package Unit °C/W °C/W Thermal resistance of the LCC_V package is for the vertical layout, not the horizontal layout. Rev. 0 | Page 4 of 32 ADXRS453 DVDD 1 16 SCLK RSVD 2 15 MOSI RSVD 3 14 AVDD CS 4 13 DVSS MISO 5 12 RSVD PDD 6 11 AVSS PSS 7 10 RSVD VX 8 9 ADXRS453 TOP VIEW (Not to Scale) CP5 09155-003 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration, 16-Lead SOIC_CAV Table 4. Pin Function Descriptions, 16-Lead SOIC_CAV Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic DVDD RSVD RSVD CS MISO PDD PSS VX CP5 RSVD AVSS RSVD DVSS AVDD MOSI SCLK Description Digital Regulated Voltage. See Figure 26 for the application circuit diagram. Reserved. This pin must be connected to DVSS. Reserved. This pin must be connected to DVSS. Chip Select. Master In/Slave Out. Supply Voltage. Switching Regulator Ground. High Voltage Switching Node. See Figure 26 for the application circuit diagram. High Voltage Supply. See Figure 26 for the application circuit diagram. Reserved. This pin must be connected to DVSS. Analog Ground. Reserved. This pin must be connected to DVSS. Digital Signal Ground. Analog Regulated Voltage. See Figure 26 for the application circuit diagram. Master Out/Slave In. SPI Clock. Rev. 0 | Page 5 of 32 AVSS 1 8 9 10 11 12 13 14 PDD BACK VIEW (Not to Scale) Figure 4. Pin Configuration, 14-Terminal LCC_V (Vertical Layout) Figure 5. Pin Configuration, 14-Terminal LCC_V (Horizontal Layout) Table 5. Pin Function Descriptions, 14-Terminal LCC_V Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Mnemonic AVSS AVDD MISO DVDD SCLK CP5 RSVD RSVD VX CS DVSS MOSI PSS PDD 09155-005 AVDD RSVD 2 PSS CP5 TOP VIEW (Not to Scale) SCLK DVDD MISO 7 CP5 6 5 4 3 VX 5 6 CS DVSS MOSI 4 RSVD 3 7 RSVD RSVD 8 09155-004 VX 9 CS DVSS AVDD 11 10 SCLK 2 MOSI 1 12 MISO PSS 13 DVDD PDD 14 AVSS ADXRS453 Description Analog Ground. Analog Regulated Voltage. See Figure 27 for the application circuit diagram. Master In/Slave Out. Digital Regulated Voltage. See Figure 27 for the application circuit diagram. SPI Clock. High Voltage Supply. See Figure 27 for the application circuit diagram. Reserved. This pin must be connected to DVSS. Reserved. This pin must be connected to DVSS. High Voltage Switching Node. See Figure 27 for the application circuit diagram. Chip Select. Digital Signal Ground. Master Out/Slave In. Switching Regulator Ground. Supply Voltage. Rev. 0 | Page 6 of 32 ADXRS453 TYPICAL PERFORMANCE CHARACTERISTICS 20 40 35 16 PERCENT OF POPULATION (%) 14 12 10 8 6 4 30 25 20 15 10 0 0.4 0.8 1.2 1.6 2.0 ERROR (°/sec) 0 –2.0 –1.6 –1.2 30 30 25 25 PERCENT OF POPULATION (%) 20 0.8 1.2 1.6 2.0 15 10 5 20 15 10 5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 10 5 0.020 0.015 0.010 0.005 0 –0.005 –0.010 –0.015 –0.030 09155-008 2.5 15 0 3.0 2.0 1.5 1.0 0 0.5 5 –0.5 3.0 10 –1.0 0.030 15 –1.5 2.5 20 –2.0 0.025 20 PERCENT OF POPULATION (%) 25 –2.5 –1.5 Figure 10. LCC_V Null Drift over Temperature 25 –3.0 –2.0 ERROR (°/sec) Figure 7. SOIC_CAV Null Drift over Temperature CHANGE IN SENSITIVITY (%) –2.5 –3.0 3.0 ERROR (°/sec) 09155-007 2.5 2.0 1.5 1.0 0 0.5 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 –0.025 PERCENT OF POPULATION (%) 0.4 Figure 9. LCC_V Null Accuracy at 25°C 0 PERCENT OF POPULATION (%) 0 ERROR (°/sec) Figure 6. SOIC_CAV Null Accuracy at 25°C 0 –0.8 –0.4 09155-010 –0.8 –0.4 CHANGE IN SENSITIVITY (%) Figure 8. SOIC_CAV Sensitivity Error at 25°C Figure 11. LCC_V Sensitivity Error at 25°C Rev. 0 | Page 7 of 32 09155-011 –1.6 –1.2 09155-006 0 –2.0 09155-009 5 2 –0.020 PERCENT OF POPULATION (%) 18 ADXRS453 45 30 PERCENT OF POPULATION (%) PERCENT OF POPULATION (%) 40 25 20 15 10 5 35 30 25 20 15 10 –3 –2 –1 1 0 2 0 09155-012 0 3 ERROR (%) –3 2 2 1 1 0 –1 –1 –2 –2 90 110 130 –3 –50 09155-014 10 30 50 70 TEMPERATURE (°C) 1000 09155-016 100 10 1 0.1 0.01 0.001 0.0001 0 Figure 14. Null Output over Temperature, 16 Devices Soldered on PCB Rev. 0 | Page 8 of 32 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 110 130 09155-017 ERROR (%) 3 –10 AVERAGING TIME (Hours) Figure 16. Typical Root Allan Variance at 105°C 3 –30 0.00001 0.001 0.0000001 1000 AVERAGING TIME (Hours) 0.01 09155-013 100 10 1 0.1 0.01 0.001 0.0001 0.00001 0.01 0.0000001 3 0.1 0.000001 ROOT ALLAN VARIANCE (°/sec) 0.1 0.000001 ROOT ALLAN VARIANCE (°/sec) 2 1 Figure 13. Typical Root Allan Variance at 40°C NULL OUTPUT (°/sec) 1 0 Figure 15. LCC_V Sensitivity Drift over Temperature 1 –3 –50 –1 ERROR (%) Figure 12. SOIC_CAV Sensitivity Drift over Temperature 0.001 –2 09155-015 5 Figure 17. Sensitivity over Temperature, 16 Devices Soldered on PCB ADXRS453 THEORY OF OPERATION The ADXRS453 operates on the principle of a resonator gyroscope. Figure 18 shows a simplified version of one of four polysilicon sensing structures. Each sensing structure contains a dither frame that is electrostatically driven to resonance. This produces the necessary velocity element to produce a Coriolis force when the device experiences angular rate. In the SOIC_CAV package, the ADXRS453 is designed to sense a z-axis (yaw) angular rate; the LCC_V vertical mount package orients the device such that it can sense pitch or roll angular rate on the same PCB. CONTINUOUS SELF-TEST The ADXRS453 gyroscope implements a complete electromechanical self-test. An electrostatic force is applied to the gyroscope frame, resulting in a deflection of the capacitive sense fingers. This deflection is exactly equivalent to deflection that occurs as a result of external rate input. The output from the beam structure is processed by the same signal chain as a true rate output signal, providing complete coverage of both the electrical and mechanical components. The electromechanical self-test is performed continuously during operation at a rate higher than the output bandwidth of the device. The self-test routine generates equivalent positive and negative rate deflections. This information can then be filtered with no overall effect on the demodulated rate output. X Y Z 09155-018 SELF-TEST AMPLITUDE. INTERNALLY COMPARED TO THE SPECIFICATION TABLE LIMITS. LOW FREQUENCY RATE INFORMATION. 09155-019 RATE SIGNAL WITH CONTINUOUS SELF-TEST SIGNAL. Figure 19. Continuous Self-Test Demodulation Figure 18. Simplified Gyroscope Sensing Structure When the sensing structure is exposed to angular rate, the resulting Coriolis force couples into an outer sense frame, which contains movable fingers that are placed between fixed pickoff fingers. This forms a capacitive pickoff structure that senses Coriolis motion. The resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. The quad sensor design rejects linear and angular acceleration, including external g-forces and vibration. This is achieved by mechanically coupling the four sensing structures such that external g-forces appear as common-mode signals that can be removed by the fully differential architecture implemented in the ADXRS453. The resonator requires 22.5 V (typical) for operation. Because only 5 V is typically available in most applications, a switching regulator is included on chip. The difference amplitude between the positive and negative self-test deflections is filtered to f0/8000 (~1.95 Hz) and is continuously monitored and compared to hard-coded self-test limits. If the measured amplitude exceeds these limits (listed in Table 1), one of two error conditions is asserted, depending on the magnitude of the self-test error. • • For less severe self-test error magnitudes, the CST bit of the fault register is asserted. However, the status bits (ST[1:0]) in the sensor data response remain set to 01 for valid sensor data. For more severe self-test errors, the CST bit of the fault register is asserted and the status bits (ST[1:0]) in the sensor data response are set to 00 for invalid sensor data. Table 1 lists the thresholds for both of these failure conditions. If desired, the user can access the self-test information by issuing a read command to the self-test memory register (Address 0x04). See the SPI Communication Protocol section for more information about error reporting. Rev. 0 | Page 9 of 32 ADXRS453 MECHANICAL PERFORMANCE The ADXRS453 has excellent shock and vibration rejection. Figure 20 shows the output noise response of the ADXRS453 in a vibration free environment. Figure 21 shows the response of the same device to 15 g rms random vibration (50 Hz to 5 kHz). As shown in Figure 21, no frequencies are particularly sensitive to vibration. Response to vibration in all axes is similar. Shock response is also excellent, as shown in Figure 22 and Figure 23. Figure 22 shows a 99 g input stimulus applied to each axis, and Figure 23 shows the typical response to this shock in each axis. Shock response of 0.01°/sec/g is apparent. 0.1 40 0 INPUT STIMULUS (g) GYRO OUTPUT (°/sec/ Hz) 20 0.01 0.001 –20 –40 –60 –80 5 50 FREQUENCY (Hz) 500 –120 09155-020 0.0001 0 Figure 20. ADXRS453 Output Noise Response with No Vibration Applied 0.05 0.10 TIME (Seconds) 0.15 0.20 09155-022 –100 Figure 22. 99 g Shock Input 0.1 10 8 GYRO OUTPUT (°/sec) GYRO OUTPUT (°/sec/ Hz) 6 0.01 0.001 4 2 0 –2 –4 –6 5 50 FREQUENCY (Hz) 500 –10 09155-021 0.0001 Figure 21. ADXRS453 Output Noise Response with 15 g RMS Random Vibration (50 Hz to 5 kHz) Applied 0 0.05 0.10 TIME (Seconds) 0.15 0.20 09155-023 –8 Figure 23. Typical Output Response Due to 99 g Shock (see Figure 22) Rev. 0 | Page 10 of 32 ADXRS453 NOISE PERFORMANCE Table 6. Statistical Noise Data Mean 0.0109 0.0149 0.0222 0.050 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0 –50 0 50 TEMPERATURE (°C) 100 Figure 24. Noise Density vs. Temperature, 16 Devices Rev. 0 | Page 11 of 32 150 09155-024 Temperature −40°C +25°C +105°C Noise (°/sec/√Hz) Standard Deviation 0.0012 0.0015 0.0019 Noise increases fairly linearly with temperature, as shown in Figure 24. NOISE DENSITY (°/sec/ Hz) The ADXRS453 noise performance is very consistent from device to device and varies very predictably with temperature. Table 6 contains statistical noise data at three temperature points for a large population of ADXRS453 devices (more than 3000 parts from several manufacturing lots). ADXRS453 APPLICATIONS INFORMATION CALIBRATED PERFORMANCE RSVD MOSI RSVD AVDD CS DVSS MISO RSVD 1µF GND 3.3V TO 5V PDD AVSS PSS RSVD 1µF MECHANICAL CONSIDERATIONS FOR MOUNTING Mount the ADXRS453 in a location close to a hard mounting point of the PCB. Mounting the ADXRS453 at an unsupported PCB location (that is, at the end of a lever or in the middle of a trampoline, as shown in Figure 25) can result in apparent measurement errors because the gyroscope is subject to the resonant vibration of the PCB. Locating the gyroscope near a hard mounting point helps to ensure that any PCB resonances at the gyroscope are above the frequency at which harmful aliasing with the internal electronics can occur. To ensure that aliased signals do not couple into the baseband measurement range, design the module so that the first system level resonance occurs at a frequency higher than 800 Hz. SCLK 16 1 DVDD 1µF 100nF 8 VX 470µH CP5 9 GND GND DIODE >24V BREAKDOWN 09155-026 The ADXRS453 gyroscope uses internal EEPROM memory to store its temperature calibration information. The calibration information is encoded into the device during factory test. The calibration data is used to perform offset, gain, and self-test corrections over temperature. By storing this information internally, the ADXRS453 eliminates the need for the customer to perform system level temperature calibration. Figure 26. Recommended Application Circuit, SOIC_CAV Package 3.3V TO 5V TOP VIEW 1 14 AVSS PDD AVDD PSS MISO MOSI DVDD DVSS SCLK CS CP5 VX 1µF 1µF 1µF GYROSCOPE PCB GND MOUNTING POINTS 09155-025 100nF GND Figure 25. Incorrectly Placed Gyroscope RSVD 470µH RSVD APPLICATION CIRCUITS Table 7. Components for ADXRS453 Application Circuits Component Inductor Diode Capacitor Capacitor Qty 1 1 3 1 Description 470 μH >24 V breakdown voltage 1 μF 100 nF Rev. 0 | Page 12 of 32 GND DIODE >24V BREAKDOWN 09155-027 Figure 26 and Figure 27 show the recommended application circuits for the ADXRS453 gyroscope. These application circuits provide a connection reference for the available package types. Note that DVDD, AVDD, and PDD are all individually connected to ground through 1 μF capacitors; do not connect these supplies together. In addition, an external diode and inductor must be connected for proper operation of the internal shunt regulator (see Table 7). These components allow the internal resonator drive voltage to reach its required level. Figure 27. Recommended Application Circuit, LCC_V Package ADXRS453 The transfer function for the rate data LPF is given as ADXRS453 SIGNAL CHAIN TIMING The ADXRS453 primary signal chain is shown in Figure 28. The signal chain is the series of necessary functional circuit blocks through which the rate data is generated and processed. This sequence of electromechanical elements determines how quickly the device can translate an external rate input stimulus to an SPI word that is sent to the master device. The group delay, which is a function of the filter characteristic, is the time required for the output of the low-pass filter to be within 10% of the external rate input. In Figure 28, the group delay is shown to be ~4 ms. Additional delay can be observed due to the timing of SPI transactions and the population of the rate data into the internal device registers. Figure 28 illustrates this delay through each element of the signal chain. ⎡ 1 − Z −64 ⎤ ⎢ −1 ⎥ ⎣⎢ 1 − Z ⎦⎥ 2 where: T= 1 1 = f 0 16 kHz (typ) (f0 is the resonant frequency of the ADXRS453.) The transfer function for the continuous self-test LPF is given as 1 64 − (63 × Z −1 ) where: T= 16 = 1 ms (typ) f0 (f0 is the resonant frequency of the ADXRS453.) PRIMARY SIGNAL CHAIN <5µs DELAY BAND-PASS FILTER ARITHMETIC LOGIC UNIT <5µs DELAY 12-BIT ADC DEMOD RATE DATA LPF CONTINUOUS SELF-TEST LPF Z-AXIS ANGULAR RATE SENSOR <64ms GROUP DELAY Figure 28. Primary Signal Chain and Associated Delays Rev. 0 | Page 13 of 32 <2.2ms DELAY SPI TRANSACTION MISO MOSI 09155-028 <5µs DELAY REGISTERS/MEMORY 4ms GROUP DELAY ADXRS453 SPI COMMUNICATION PROTOCOL The device response to the initial command is 0x00000001. This response prevents the transmission of random data to the master device upon the initial command/response exchange. COMMAND/RESPONSE Input/output is handled through a 32-bit command/response SPI interface. With the command/response SPI interface, the response to a command is issued during the next sequential SPI exchange (see Figure 29). The SPI interface uses the ADXRS453 pins described in Table 8. Table 8. SPI Signals The format for the interface is defined as follows: Signal Serial Clock Chip Select Master Out/ Slave In Master In/ Slave Out Clock Phase = Clock Polarity = 0 Table 9 shows the commands that can be sent from the master device to the gyroscope. Table 10 shows the responses to these commands from the gyroscope. For descriptions of the bits in the commands and responses, see the Command/Response Bit Definitions section and the Fault Register Bit Definitions section. Pin SCLK CS MOSI Description Exactly 32 clock cycles during CS active Active low chip select pin Input for data sent to the gyroscope (slave) from the main controller (master) Output for data sent to the main controller (master) from the gyroscope (slave) MISO CS SCLK 32 CLOCK CYCLES 32 CLOCK CYCLES COMMAND N COMMAND N + 1 MOSI RESPONSE N – 1 09155-029 MISO RESPONSE N Figure 29. SPI Protocol Table 9. SPI Commands 25 24 23 22 21 20 19 Bit 18 17 16 15 14 SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0 SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 Command 31 30 29 SQ1 SQ0 1 Sensor Data Read 0 28 27 SQ2 Write 0 26 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHK P P D3 D2 D1 D0 P Table 10. SPI Responses Bit Command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 SQ2 SQ1 SQ0 P0 ST1 ST0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Sensor Data Read 0 1 0 P0 1 1 1 0 SM2 SM1 SM0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 10 D0 9 D5 D4 D3 D2 D1 D0 P1 Write D5 D4 D3 D2 D1 D0 P1 0 0 1 P0 1 1 1 0 SM2 SM1 SM0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 R/W Error 0 0 0 P0 1 1 1 0 SM2 SM1 SM0 0 0 SPI RE DU Rev. 0 | Page 14 of 32 8 7 6 5 4 3 2 1 0 PLL Q NVM POR PWR CST CHK P1 PLL Q NVM POR PWR CST CHK P1 ADXRS453 Note that the transmitted data is only as recent as the sequential transmission delay implemented by the system. Conditions that result in a sequential transfer delay of several seconds cause the next sequential device response to contain data that is several seconds old. DEVICE DATA LATCHING To allow for rapid acquisition of data from the ADXRS453, device data latching is implemented, as shown in Figure 30. When the chip select pin is asserted (CS goes low), the data in the device is latched into memory. When the full MOSI command is received and the chip select pin is deasserted (CS goes high), the data is shifted into the SPI port registers in preparation for the next sequential command/response exchange. Device data latching allows for an extremely fast sequential transfer delay of 0.1 μs (see Table 11). DEVICE DATA IS LATCHED AFTER THE ASSERTION OF CS. LATCHED DATA IS TRANSMITTED DURING THE NEXT SEQUENTIAL COMMAND/RESPONSE EXCHANGE. CS 32 CLOCK CYCLES 32 CLOCK CYCLES MOSI COMMAND N 0x… COMMAND N + 1 0x… MISO RESPONSE N – 1 0x00000001 RESPONSE N 0x… Figure 30. Device Data Latching Rev. 0 | Page 15 of 32 32 CLOCK CYCLES COMMAND N + 2 0x… RESPONSE N + 1 0x… 09155-031 SCLK ADXRS453 • • • • SPI TIMING CHARACTERISTICS The following conditions apply to the SPI command/response timing characteristics in Table 11: • • All timing parameter are guaranteed through characterization. All timing is shown with respect to 10% DVDD and 90% of the actual delivered voltage waveform. Parameters are valid for 3.0 V ≤ DVDD ≤ 5.5 V. Capacitive load for all signals is assumed to be ≤80 pF. Ambient temperature is −40°C ≤ TA ≤ +105°C. The MISO pull-up is 47 kΩ or 110 μA. Table 11. SPI Command/Response Timing Characteristics Symbol fOP tSCLKH tSCLKL tSCLK tF tR tSU tHIGH tA tV tLAG_MISO tDIS tLEAD tLAG_CS Min tTD Max 8.08 1/2 × tSCLK 1/2 × tSCLK Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Description SPI operating frequency SCLK high time SCLK low time SCLK period SCLK fall time SCLK rise time Data input (MOSI) setup time Data input (MOSI) hold time Data output (MISO) access time Data output (MISO) valid after SCLK Data output (MISO) lag time Data output (MISO) disable time Enable (CS) lead time Enable (CS) lag time 0.1 μs Sequential transfer delay 1/2 × tSCLK − 13 1/2 × tSCLK − 13 123.7 5.5 5.5 37 49 13 13 20 40 0 40 CS tTD tSCLK tLEAD tSCLKH tSCLKL tR tLAG_CS tF SCLK tA tV MISO tLAG_MISO tDIS MSB LSB tHIGH tSU MSB LSB 09155-030 MOSI Figure 31. SPI Timings Rev. 0 | Page 16 of 32 ADXRS453 SPI Bit COMMAND/RESPONSE BIT DEFINITIONS The SPI bit is set when either of the following occurs: Table 12. SPI Interface Bit Definitions Bits SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 P SPI RE DU ST1, ST0 P0 P1 • • Description Sequence bits (from master) Sensor module bits (from master) Register address Data Command odd parity SPI command/response Request error Data unavailable Status bits Response, odd parity, Bits[31:16] Response, odd parity, Bits[31:0] Too many or not enough bits were transmitted. A message from the control module contains a parity error. A SPI error causes the device to issue a R/W error response regardless of the SPI command type issued by the master device (see Table 10). In addition, any error during a sensor data request results in the device issuing a read/write error. RE Bit The request error (RE) bit is the communication error bit transmitted from the ADXRS453 device to the control module. Request errors can occur when • • SQ2 to SQ0 Bits The SQ2 to SQ0 bits provide the system with a means of synchronizing the data samples that are received from multiple sensors. To facilitate correct synchronization, the ADXRS453 gyroscope includes the SQ[2:0] bits in the response sequence as they were received in the request. • An invalid command is sent from the control module. A read/write command specifies an invalid memory register. A write command attempted to write to a nonwritable memory register. DU Bit The SM2 to SM0 bits are the sensor module bits from the master device. These bits are not implemented in the ADXRS453 and are hard-coded to 000 for all occurrences. After the chip select pin is deasserted (CS goes high), the user must wait 0.1 μs before reasserting the CS pin to initiate another command/response frame with the device. Failure to adhere to this timing specification may result in a data unavailable (DU) error. A8 to A0 Bits ST1 and ST0 Bits The A8 to A0 bits represent the memory address for data read or data write. These bits should be supplied by the master when the memory registers are being accessed; these bits are ignored for all sensor data requests. For a complete description of the available memory registers, see the Memory Register Definitions section. The status bits (ST1 and ST0) are used to signal to the master device the type of data contained in the response message (see Table 13). SM2 to SM0 Bits D15 to D0 Bits The D15 to D0 bits are the 16-bit device data, which can contain any of the following: • • • • Data from the master to be written to a memory register, as specified by the A8 to A0 bits. Sensor rate output data from the slave. Device data from the slave read from the memory register specified by the A8 to A0 bits, as well as the data from the next sequential register. Following a write command, the 16-bit data that is written to the specified memory register in the ADXRS453 and is reflected back to the master device for correlation. Table 13. Status Bit Code Definitions ST[1:0] 00 01 10 11 Contents of Bits[D15:D0] Invalid data for sensor data response Valid sensor data Sensor self-test data Read/write response Either of the following conditions can result in the ST[1:0] bits being set to 00 during a sensor data response: • • The self-test response is sufficiently different from its nominal value (see the Specifications section for the appropriate limits). The PLL fault bit is active (see the PLL Bit section). P0 Bit P0 is the parity bit that establishes odd parity for Bits[31:16] of the device response. P Bit A parity bit (P) is required for all master-to-slave data transmissions. The communication protocol requires one parity bit to achieve odd parity for the entire 32-bit command. “Don’t care” bits are also factored into the parity calculation. P1 Bit P1 is the parity bit that establishes odd parity for the entire 32-bit device response. Rev. 0 | Page 17 of 32 ADXRS453 FAULT REGISTER BIT DEFINITIONS UV Bit Table 14 describes the bits available for signaling faults to the user. The individual bits of the fault registers are updated asynchronously, depending on their respective detection criteria; however, it is recommended that the fault registers be read at a rate of at least 250 Hz. When asserted, an individual status bit is not deasserted until it is read by the master device. If the error persists after a fault register read, the status bit is immediately reasserted and remains asserted until the next sequential command/ response exchange. The bits in the FAULT0 register are appended to every sensor data response (see Table 10). Both fault registers can be accessed by issuing a read command to Address 0x0A. The UV fault bit is asserted if the internally regulated voltage (nominally 3 V) is observed to be less than 2.77 V. This measurement is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When a UV fault occurs, the PWR fault bit is asserted simultaneously. Because the UV fault bit is not transmitted as part of a sensor data response, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error to determine the specific error condition. Table 14. Fault Register Bit Definitions Register FAULT1 FAULT0 Bit Name Fail AMP OV UV PLL Q NVM POR PWR CST CHK Description Failure that sets the ST[1:0] bits to 00 Amplitude detection failure Regulator overvoltage Regulator undervoltage Phase-locked loop failure Quadrature error Nonvolatile memory fault Power-on or reset failed to initialize Power regulation failed due to overvoltage or undervoltage condition Continuous self-test failure or amplitude detection failed Check: generate faults PLL Bit The PLL bit indicates that the device has experienced a failure in the phase-locked loop functional circuit block. This occurs when the PLL fails to achieve synchronization with the resonator structure. If the PLL status flag is active, the ST[1:0] bits of the sensor data response are set to 00, indicating that the response contains potentially invalid rate data. Q Bit A Q fault is asserted based on two independent quadrature calculations. • • Fail Bit The fail flag is asserted when the ST[1:0] bits are set to 00 (see the ST1 and ST0 Bits section). Assertion of the fail bit indicates that the device has experienced a gross failure and that the sensor data could be invalid. AMP Bit The AMP fault bit is asserted when the measured amplitude of the silicon resonator has been significantly reduced. This condition can occur if the voltage supplied to CP5 falls below the requirements of the internal voltage regulator. This fault bit is OR’ed with the CST fault bit; therefore, during a sensor data request, the CST bit position represents either an AMP failure or a CST failure. The full fault register can be read from memory to determine the specific failure. OV Bit The OV fault bit is asserted if the internally regulated voltage (nominally 3 V) is observed to exceed 3.3 V. This measurement is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When an OV fault occurs, the PWR fault bit is asserted simultaneously. Because the OV fault bit is not transmitted as part of a sensor data response, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error to determine the specific error condition. The quad memory register (Address 0x08) contains a value corresponding to the total instantaneous quadrature present in the device. If this value exceeds 4096 LSB, a Q fault is issued. An internal quadrature accumulator records the amount of quadrature correction performed by the ADXRS453. A Q fault is issued when the quadrature error present in the device has contributed to an equivalent of 4°/sec (typical) of rate offset. NVM Bit An NVM error is transmitted to the control module when the internal nonvolatile memory data fails a checksum calculation. This check is performed once every 50 μs and does not include the PIDx memory registers. POR Bit An internal check is performed on device startup to ensure that the volatile memory of the device is functional. This is accomplished by programming a known value from the device ROM into a volatile memory register. This value is then continuously compared to the known value in ROM every 1 μs for the duration of the device operation. If the value stored in the volatile memory changes or does not match the value stored in ROM, the POR error flag is asserted. The value stored in ROM is rewritten to the volatile memory upon a device power cycle. Rev. 0 | Page 18 of 32 ADXRS453 PWR Bit CHK Bit The device performs a continuous check of the internal 3 V regulated voltage level. If either an overvoltage (OV) or undervoltage (UV) fault is asserted, the PWR bit is also asserted. This condition occurs if the regulated voltage is observed to be either above 3.3 V or below 2.77 V. An internal low-pass filter removes high frequency glitching effects to prevent the PWR bit from being asserted unnecessarily. To determine whether the fault is a result of an overvoltage or undervoltage condition, the OV and UV fault bits must be read. The CHK bit is transmitted by the control module to the ADXRS453 as a method of generating faults. By asserting the CHK bit, the device creates conditions that result in the generation of all faults represented in the fault registers. For example, the self-test amplitude is deliberately altered to exceed the fault detection threshold, resulting in a self-test error. In this way, the device is capable of checking both its ability to detect a fault condition and its ability to report that fault condition to the control module. CST Bit The fault conditions are initiated nearly simultaneously; however, the timing for receiving fault codes when the CHK bit is asserted depends on the time required to generate each unique fault. It takes no more than 50 ms for all internal faults to be generated and the fault register to be updated to reflect the condition of the device. Until the CHK bit is cleared, the status bits (ST[1:0]) are set to 10, indicating that the data should be interpreted by the control module as self-test data. After the CHK bit is deasserted, an additional 50 ms are required for the fault conditions to decay and for the device to return to normal operation. See the Recommended Start-Up Sequence with CHK Bit Assertion section for the proper methodology for asserting the CHK bit. The ADXRS453 is designed with continuous self-test functionality. The measured self-test amplitudes are compared to the limits presented in Table 1. Deviations from these values result in reported self-test errors. The two thresholds for a self-test failure are as follows: • • Self-test value > ±512 LSB from nominal results in the assertion of the self-test flag in the fault register. Self-test value > ±1856 LSB from nominal results in the assertion of the self-test flag in the fault register and the setting of the ST[1:0] bits to 00, indicating that the rate data contained in the sensor data response is potentially invalid. Rev. 0 | Page 19 of 32 ADXRS453 in an apparent one-transaction delay before the data resulting from the assertion of the CHK bit is reported by the device. For all other read/write interactions with the device, no such delay exists, and the MOSI command is serviced during the next sequential command/response exchange. RECOMMENDED START-UP SEQUENCE WITH CHK BIT ASSERTION Figure 32 illustrates a recommended start-up sequence that can be implemented by the user. Alternate start-up sequences can be used, but the response from the ADXRS453 must be handled correctly. If the start-up sequence is implemented immediately after power is applied to the device, the total time to implement the following fault detection routine is approximately 200 ms. Note that if the CHK bit is deasserted and the user tries to obtain data from the device before the CST fault flag clears, the device reports the data as error data. As described in the Device Data Latching section, the data present in the device upon the assertion of the CS signal is used in the next sequential command/response exchange. This results MOSI: SENSOR DATA REQUEST (THIS CLEARS THE CHK BIT) MISO: STANDARD INITIAL RESPONSE MISO: SENSOR DATA RESPONSE DATA LATCH POINT CS X 32 CLOCK CYCLES SCLK MOSI: SENSOR DATA REQUEST MOSI: SENSOR DATA REQUEST MISO: CHK RESPONSE ST[1:0] = 10 MISO: CHK RESPONSE ST[1:0] = 10 X 32 CLOCK CYCLES X 32 CLOCK CYCLES 32 CLOCK CYCLES MOSI 0x20000003 0x20000000 0x20000000 0x20000000 MISO 0x00000001 0x… 0x…FF OR 0x…FE (PARITY DEPENDENT) 0x…FF OR 0x…FE (PARITY DEPENDENT) t = 100ms POWER IS APPLIED TO THE DEVICE. WAIT 100ms TO ALLOW FOR THE INTERNAL CIRCUITRY TO BE INITIALIZED. t = 150ms WHEN THE 100ms START-UP TIME HAS ELAPSED, THE MASTER DEVICE IS FREE TO ASSERT THE CHK BIT AND START THE PROCESS OF INTERNAL ERROR CHECKING. DURING THE FIRST COMMAND/ RESPONSE EXCHANGE AFTER POWER-ON, THE ADXRS453 IS DESIGNED TO ISSUE A PREDEFINED RESPONSE. t = 200ms A 50ms DELAY IS REQUIRED SO THAT THE GENERATION OF FAULTS WITHIN THE DEVICE IS ALLOWED TO COMPLETE. HOWEVER, BECAUSE THE DEVICE DATA IS LATCHED BEFORE THE CHK BIT IS ASSERTED, THE DEVICE RESPONSE DURING THIS COMMAND/RESPONSE EXCHANGE DOES NOT CONTAIN FAULT INFORMATION. THIS RESPONSE CAN BE DISCARDED. t = 200ms + tTD ANOTHER 50ms DELAY MUST BE OBSERVED TO ALLOW THE FAULT CONDITIONS TO CLEAR. IF THE DEVICE IS FUNCTIONING PROPERLY, THE MISO RESPONSE CONTAINS ALL ACTIVE FAULTS, AS WELL AS HAVING SET THE MESSAGE FORMAT TO SELF-TEST DATA. THIS IS INDICATED THROUGH THE ST BITS BEING SET TO 10. Figure 32. Recommended Start-Up Sequence Rev. 0 | Page 20 of 32 t = 200ms + 2tTD THE FAULT BITS OF THE ADXRS453 REMAIN ACTIVE UNTIL CLEARED. DUE TO THE REQUIRED DECAY PERIOD FOR EACH FAULT CONDITION, FAULT CONDITIONS REMAIN PRESENT UPON THE IMMEDIATE DEASSERTION OF THE CHK BIT. THIS RESULTS IN A SECOND SEQUENTIAL RESPONSE IN WHICH THE FAULT BITS ARE ASSERTED. AGAIN, THE RESPONSE IS FORMATTED AS SELF-TEST DATA INDICATING THAT THE FAULT BITS HAVE BEEN SET INTENTIONALLY. ALL FAULT CONDITIONS ARE CLEARED, AND ALL SUBSEQUENT DATA EXCHANGES NEED ONLY OBSERVE THE SEQUENTIAL TRANSFER DELAY TIMING PARAMETER. 09155-032 MOSI: SENSOR DATA REQUEST CHK BIT ASSERTED ADXRS453 RATE DATA FORMAT The ADXRS453 gyroscope transmits rate data in a 16-bit format as part of a 32-bit SPI data frame. See Table 10 for the full 32-bit format of the sensor data response. The rate data is transmitted MSB first, from D15 to D0. The data is formatted as a twos complement number with a scale factor of 80 LSB/°/sec. Therefore, the highest obtainable value for positive (clockwise) rotation is 0x7FFF (decimal +32,767), and the highest obtainable value for negative (counterclockwise) rotation is 0x8000 (decimal −32,768). Performance of the device is not guaranteed above ±24,000 LSB (±300°/sec). Table 15. Rate Data 16-Bit Rate Data Decimal (LSBs) Hex (D15:D0) +32,767 0x7FFF … … +24,000 0x5DC0 … … +160 0x00A0 … … +80 0x0050 … … +40 0x0028 … … +20 0x0014 … … 0 0x0000 … … −20 0xFFEC … … −40 0xFFD8 … … −80 0xFFB0 … … −160 0xFF60 … … −24,000 0xA240 … … −32,768 0x8000 Description Maximum possible positive data value (not guaranteed) … +300°/sec rotation (positive FSR) … +2°/sec rotation … +1°/sec rotation … +0.5°/sec rotation … +0.025°/sec rotation … Zero rotation value … −0.025°/sec rotation … −0.5°/sec rotation … −1°/sec rotation … −2°/sec rotation … −300°/sec rotation (negative FSR) … Maximum possible negative data value (not guaranteed) Rev. 0 | Page 21 of 32 ADXRS453 MEMORY MAP AND REGISTERS MEMORY MAP Table 16 provides a list of the memory registers that can be read from or written to by the user. See the SPI Communication Protocol section for the proper input sequence to read from or write to a specific memory register. Each memory register has eight bits of data; however, when a read request is performed, the data always returns as a 16-bit message. This is accomplished by appending the data from the next sequential register to the memory address that was specified. Data is transmitted MSB first. For proper acquisition of data from the memory register, make the read request to the even-numbered register address only; for example, to read the LOCSTx registers, address Register 0x04, but not Register 0x05. For a description of each memory register listed in Table 16, see the Memory Register Definitions section. Table 16. Memory Register Map Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 Register Name RATE1 RATE0 TEM1 TEM0 LOCST1 LOCST0 HICST1 HICST0 QUAD1 QUAD0 FAULT1 FAULT0 PID1 PID0 SN3 SN2 SN1 SN0 D7 (MSB) RTE15 RTE7 TEM9 TEM1 LCST15 LCST7 HCST15 HCST7 QAD15 QAD7 Unused PLL PIDB15 PIDB7 SNB31 SNB23 SNB15 SNB7 D6 RTE14 RTE6 TEM8 TEM0 LCST14 LCST6 HCST14 HCST6 QAD14 QAD6 Unused Q PIDB14 PIDB6 SNB30 SNB22 SNB14 SNB6 D5 RTE13 RTE5 TEM7 Unused LCST13 LCST5 HCST13 HCST5 QAD13 QAD5 Unused NVM PIDB13 PIDB5 SNB29 SNB21 SNB13 SNB5 D4 RTE12 RTE4 TEM6 Unused LCST12 LCST4 HCST12 HCST4 QAD12 QAD4 Unused POR PIDB12 PIDB4 SNB28 SNB20 SNB12 SNB4 Rev. 0 | Page 22 of 32 D3 RTE11 RTE3 TEM5 Unused LCST11 LCST3 HCST11 HCST3 QAD11 QAD3 Fail PWR PIDB11 PIDB3 SNB27 SNB19 SNB11 SNB3 D2 RTE10 RTE2 TEM4 Unused LCST10 LCST2 HCST10 HCST2 QAD10 QAD2 AMP CST PIDB10 PIDB2 SNB26 SNB18 SNB10 SNB2 D1 RTE9 RTE1 TEM3 Unused LCST9 LCST1 HCST9 HCST1 QAD9 QAD1 OV CHK PIDB9 PIDB1 SNB25 SNB17 SNB9 SNB1 D0 (LSB) RTE8 RTE0 TEM2 Unused LCST8 LCST0 HCST8 HCST0 QAD8 QAD0 UV 0 PIDB8 PIDB0 SNB24 SNB16 SNB8 SNB0 ADXRS453 MEMORY REGISTER DEFINITIONS Low CST (LOCSTx) Registers The SPI-accessible memory registers are described in this section. As noted in the Memory Map section, when requesting data from a memory register, only the first sequential memory address should be addressed. The data returned by the device contains 16 bits of memory register information. Bits[15:8] contain the MSB of the requested information, and Bits[7:0] contain the LSB. Addresses: Rate (RATEx) Registers Addresses: 0x00 (RATE1) 0x01 (RATE0) Register update rate: f0/32 (~485 Hz) Scale factor: 80 LSB/°/sec The RATEx registers contain the temperature compensated rate output of the device, filtered to f0/200 (~77.5 Hz). This data can also be accessed by issuing a sensor data read request to the device. The data is presented as a 16-bit, twos complement number. MSB D15 RTE15 D7 RTE7 D14 RTE14 D6 RTE6 D13 RTE13 D5 RTE5 D12 RTE12 D4 RTE4 D11 RTE11 D3 RTE3 D10 RTE10 D2 RTE2 D9 RTE9 D1 RTE1 LSB D8 RTE8 D0 RTE0 0x04 (LOCST1) 0x05 (LOCST0) Register update rate: f0/16 (~970 Hz) Scale factor: 80 LSB/°/sec The LOCSTx registers contain the value of the temperature compensated and low-pass filtered continuous self-test delta. This value is a measure of the difference between the positive and negative self-test deflections and corresponds to the values presented in Table 1. The device issues a CST error if the value of the self-test exceeds the established self-test limits. The self-test data is filtered to f0/8000 (~1.95 Hz) to prevent false triggering of the CST fault bit. The data is presented as a 16-bit, twos complement number, with a scale factor of 80 LSB/°/sec. MSB D15 LCST15 D7 LCST7 D14 LCST14 D6 LCST6 D13 LCST13 D5 LCST5 0x03 (TEM0) f0/32 (~485 Hz) Scale factor: 5 LSB/°C The TEMx registers contain a value corresponding to the temperature of the device. The data is presented as a 10-bit, twos complement number. 0 LSB corresponds to a temperature of approximately 45°C (see Table 17). MSB D15 TEM9 D7 TEM1 D14 TEM8 D6 TEM0 D13 TEM7 D5 D12 TEM6 D4 D11 D10 TEM5 TEM4 D3 D2 Unused D9 TEM3 D1 LSB D8 TEM2 D0 Table 17. Sample Temperatures and TEMx Register Contents Temperature 45°C 85°C 0°C 1 D10 LCST10 D2 LCST2 D9 LCST9 D1 LCST1 LSB D8 LCST8 D0 LCST0 Addresses: 0x06 (HICST1) 0x07 (HICST0) 0x02 (TEM1) Register update rate: D11 LCST11 D3 LCST3 High CST (HICSTx) Registers Temperature (TEMx) Registers Addresses: D12 LCST12 D4 LCST4 Register update rate: f0/16 (~970 Hz) Scale factor: 80 LSB/°/sec The HICSTx registers contain the unfiltered self-test information. The HICSTx data can be used to supplement fault diagnosis in safety critical applications because sudden shifts in the self-test response can be detected. However, the CST bit of the fault register is not set when the HICSTx data is observed to exceed the self-test limits. Only the LOCSTx memory registers, which are designed to filter noise and the effects of sudden temporary self-test spiking due to external disturbances, control the assertion of the CST fault bit. The data is presented as a 16-bit, twos complement number. MSB D15 HCST15 D7 HCST7 Value of TEM1 and TEM0 Registers1 0000 0000 00XX XXXX 0011 0010 00XX XXXX 1100 0111 11XX XXXX X = don’t care. Rev. 0 | Page 23 of 32 LSB D14 D13 D12 D11 D10 D9 D8 HCST14 HCST13 HCST12 HCST11 HCST10 HCST9 HCST8 D6 D5 D4 D3 D2 D1 D0 HCST6 HCST5 HCST4 HCST3 HCST2 HCST1 HCST0 ADXRS453 Quad Memory (QUADx) Registers Part ID (PIDx) Registers Addresses: Addresses: 0x08 (QUAD1) 0x0C (PID1) 0x09 (QUAD0) 0x0D (PID0) Register update rate: f0/64 (~240 Hz) Register update rate: Not applicable Scale factor: 80 LSB/°/sec equivalent Scale factor: Not applicable The QUADx registers contain a value corresponding to the amount of quadrature error present in the device at a given time. Quadrature can be likened to a measurement of the error of the motion of the resonator structure and can be caused by stresses and aging effects. The quadrature data is filtered to f0/200 (~77.5 Hz) and can be read frequently to detect sudden shifts in the level of quadrature. The data is presented as a 16-bit, twos complement number. MSB D15 QAD15 D7 QAD7 D14 QAD14 D6 QAD6 D13 QAD13 D5 QAD5 D12 QAD12 D4 QAD4 D11 QAD11 D3 QAD3 D10 QAD10 D2 QAD2 D9 QAD9 D1 QAD1 LSB D8 QAD8 D0 QAD0 The (PIDx) registers contain a 16-bit number that identifies the version of the ADXRS453. Combined with the serial number, this information allows for a higher degree of device individualization and tracking. The initial product ID is R01 (0x5201), with subsequent versions of silicon incrementing this value to R02, R03, and so on. MSB D15 PIDB15 D7 PIDB7 D14 PIDB14 D6 PIDB6 D13 PIDB13 D5 PIDB5 D12 PIDB12 D4 PIDB4 D11 PIDB11 D3 PIDB3 Addresses: Addresses: LSB D8 PIDB8 D0 PIDB0 0x0E (SN3) 0x0A (FAULT1) 0x0F (SN2) 0x0B (FAULT0) 0x10 (SN1) Register update rate: Not applicable 0x11 (SN0) Scale factor: Not applicable The FAULTx registers contain the state of the error flags in the device. The FAULT0 register is appended to the end of every device data transmission (see Table 10); however, this register can also be accessed independently through its memory location. The individual fault bits are updated asynchronously, requiring <5 μs to activate, as soon as the fault condition exists on chip. When toggled, each fault bit remains active until the fault register is read or a sensor data command is received. If the fault is still active after the bit is read, the fault bit is immediately reasserted. D7 PLL D9 PIDB9 D1 PIDB1 Serial Number (SNx) Registers Fault (FAULTx) Registers MSB D15 D10 PIDB10 D2 PIDB2 D14 D13 Unused D6 D5 Q NVM D12 D4 POR D11 Fail D3 PWR D10 AMP D2 CST D9 OV D1 CHK LSB D8 UV D0 0 Register update rate: Not applicable Scale factor: Not applicable The SNx registers contain a 32-bit identification number that uniquely identifies the device. To read the entire serial number, two memory read requests must be initiated. The first read request to Address 0x0E returns the upper 16 bits of the serial number, and the following read request to Address 0x10 returns the lower 16 bits of the serial number. MSB D31 SNB31 D23 SNB23 D15 SNB15 D7 SNB7 Rev. 0 | Page 24 of 32 D30 SNB30 D22 SNB22 D14 SNB14 D6 SNB6 D29 D28 D27 SNB29 SNB28 SNB27 D21 D20 D19 SNB21 SNB20 SNB19 D13 D12 D11 SNB13 SNB12 SNB11 D5 D4 D3 SNB5 SNB4 SNB3 D26 SNB26 D18 SNB18 D10 SNB10 D2 SNB2 D25 SNB25 D17 SNB17 D9 SNB9 D1 SNB1 LSB D24 SNB24 D16 SNB16 D8 SNB8 D0 SNB0 ADXRS453 PACKAGE ORIENTATION AND LAYOUT INFORMATION ADXRS453 (PACKAGE FRONT) 14 8 09155-033 1 7 Figure 33. 14-Lead Ceramic LCC_V, Vertical Mount 0.55 0.55 0.55 11.232 0.95 0.95 1.55 1.55 1.27 2.55 9.462 5.55 0.572 1.5 Figure 34. Sample SOIC_CAV Solder Pad Layout (Land Pattern), Dimensions Shown in Millimeters, Not to Scale 1 0.8 0.8 1 1.5 Figure 35. Sample LCC_V Solder Pad Layout (Land Pattern) for Vertical Mounting, Dimensions Shown in Millimeters, Not to Scale Rev. 0 | Page 25 of 32 09155-035 1.691 09155-034 2.55 ADXRS453 0.90 1.50 0.50 3.10 7.70 1.00 1.50 0.80 09155-036 2.70 Figure 36. Sample LCC_V Solder Pad Layout (Land Pattern) for Horizontal Mounting, Dimensions Shown in Millimeters, Not to Scale Rev. 0 | Page 26 of 32 ADXRS453 SOLDER PROFILE SUPPLIER TP ≥ TC USER TP ≤ TC TC TC – 5°C SUPPLIER tP USER tP TP tP MAXIMUM RAMP-UP RATE = 3°C/sec MAXIMUM RAMP-DOWN RATE = 6°C/sec TC – 5°C TL TEMPERATURE TSMAX PREHEAT AREA tL TSMIN tS 09155-037 25 TIME 25°C TO PEAK TIME Figure 37. Recommended Soldering Profile Table 18. Recommended Soldering Profile Limits Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX), tS Ramp-Up Rate (TSMAX to TL) Time Maintained Above Liquidous (tL) Liquidous Temperature (TL) Classification Temperature (TC)1 Peak Temperature (TP) Time Within 5°C of Actual Peak Temperature (tP) Ramp-Down Rate (TP to TL) Time 25°C to Peak Temperature 1 Sn63/Pb37 3°C/sec max Pb-Free 3°C/sec max 100°C 150°C 60 sec to 120 sec 3°C/sec max 60 sec to 150 sec 183°C 220°C TC + 0°C/−5°C 10 sec to 30 sec 6°C/sec max 6 minutes max 150°C 200°C 60 sec to 120 sec 3°C/sec max 60 sec to 150 sec 217°C 250°C TC + 0°C/−5°C 20 sec to 40 sec 6°C/sec max 8 minutes max Based on IPC/JEDEC J-STD-020D.01 for SnPb and Pb-free processes. Package volume < 350 mm3, package thickness > 2.5 mm. Rev. 0 | Page 27 of 32 ADXRS453 PACKAGE MARKING CODES XRS453 BRGZ n #YYWW LLLLLLLLL 09155-038 XRS453 BEYZ n #YYWW LLLLLLLLL Figure 38. LCC_V and SOIC_CAV Package Marking Codes Table 19. Package Code Designations Marking XRS 453 B RG EY Z n # YYWW LLLLLLLLL Meaning Angular rate sensor Series number Temperature grade (−40°C to +105°C) Package designator (SOIC_CAV package) Package designator (LCC_V package) RoHS compliant Revision number Pb-free designation Assembly date code Assembly lot code (up to nine characters) Rev. 0 | Page 28 of 32 ADXRS453 OUTLINE DIMENSIONS 10.30 BSC 16 9 7.80 BSC 1 DETAIL A 10.42 BSC 8 PIN 1 INDICATOR 0.25 GAGE PLANE 8° 4° 0° 1.27 BSC 9.59 BSC 3.73 3.58 3.43 0.87 0.77 0.67 1.50 1.35 1.20 0.50 0.45 0.40 0.58 0.48 0.38 0.75 0.70 0.65 DETAIL A 072409-B 0.28 0.18 0.08 COPLANARITY 0.10 Figure 39. 16-Lead Small Outline, Plastic Cavity Package [SOIC_CAV] (RG-16-1) Dimensions shown in millimeters FRONT VIEW 9.20 9.00 SQ 8.80 8.08 8.00 7.92 0.275 REF 0.350 0.305 0.260 7.70 7.55 7.40 BACK VIEW 7.18 7.10 7.02 1 1.175 REF C 0.30 REF 4.40 4.00 3.60 2 3 4 5 6 0.50 TYP 7 SIDE VIEW 1.00 0.675 NOM 0.500 MIN 1.60 (PINS 2, 6) (PINS 1, 7) R 0.20 REF 1 2 3 4 5 6 7 14 13 12 11 10 9 8 (ALL PINS) 0.80 0.40 12 13 14 DO NOT SOLDER CENTER PADS. (PINS 2, 6, 9, 13) 0.80 (PINS 10, 11, 12) 0.35 REF 0.80 REF (METALLIZATION BUMP BUMP HEIGHT 0.03 NOM) 04-08-2010-A 1.70 REF 1.40 11 1.50 (PINS 9-10, 12-13) 0.30 REF 0.35 REF 0.30 REF (PINS 1, 7, 8, 14) 10 1.00 0.60 1.70 REF 9 (PINS 2, 6) (PINS 3-5) (ALL PINS) 8 (PINS 3-5, 10-12) BOTTOM VIEW (PADS SIDE) Figure 40. 14-Terminal Ceramic Leadless Chip Carrier, Vertical Form [LCC_V] (EY-14-1) Dimensions shown in millimeters Rev. 0 | Page 29 of 32 ADXRS453 ORDERING GUIDE Model 1, 2, 3 ADXRS453BEYZ EVAL-ADXRS453Z EVAL-ADXRS453Z-V EVAL-ADXRS453Z-M EVAL-ADXRS453Z-S Temperature Range −40°C to +105°C Package Description 14-Terminal Ceramic Leadless Chip Carrier, Vertical Form [LCC_V] Evaluation Board, SOIC_CAV Evaluation Board, LCC_V Analog Devices Inertial Sensor Evaluation System (Includes ADXRS453 Satellite) ADXRS453 Satellite, Standalone, to be used with Inertial Sensor Evaluation System 1 Z = RoHS Compliant Part. The tape and reel version of the ADXRS453BEYZ (14-terminal LCC_V) is releasing in the second quarter of 2011. 3 The ADXRS453BRG (16-lead SOIC_CAV) is releasing in the second quarter of 2011. 2 Rev. 0 | Page 30 of 32 Package Option EY-14-1 ADXRS453 NOTES Rev. 0 | Page 31 of 32 ADXRS453 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09155-0-1/11(0) Rev. 0 | Page 32 of 32