PJDLLLC70 Very Low Capacitance Diode Array This diode array is configured to protect up to two high speed data transmission lines, used in Low Voltage Differential Signal (LVDS) ports. Acting as a line terminator, minimizes overshoot and undershoot conditions due to bus impedance as well as protect against over-voltage events as electrostatic discharges. The line-line concept minimizes the problems to customers to re-route PCB lines, simplifying the design. SOT563 Package 6 1 2 SPECIFICATION FEATURES 5 4 3 Maximum Capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground Line1 +VREF Line2 Maximum Leakage Current of 1µA @ VRWM Industry Standard SMT Package SOT563 6 5 4 1 2 3 IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact* 100% Tin Matte finish (LEAD-FREE PRODUCT) APPLICATIONS USB 2.0 and Firewire Port Protection Line1 Gnd Line2 HDMI Version 1.3 Note: pins 1and 6 (Line1) as well as pins 3 and 4 (Line2) must be connected externally, as the drawing attached below. DVI MARKING : 70 I/O Line 1 1 6 GND 2 5 I/O Line 2 3 4 +VREF Line-line concept ease the PCB design, directly placing the device over the data lines, opening only the contact points. VREF is fixed by the operating voltage, referenced to the ground. MAXIMUM RATINGS Tj = 25°C Unless otherwise noted Rating Symbol Value Units Peak Pulse Current (8/20µs Waveform) I PPM 12 A Rectifier Repetitive Peak Reverse Voltage VRRM 70 V TJ -55 to +125 °C Storage Temperature Range Tstg -55 to +150 °C Soldering Temperature, t max = 10s TL 260 °C Operating Junction Temperature Range Note: ESD Testing requires to connect a TVS between +VREF and GND, if there is no +VREF Bias connected. 7/23/2009 Page 1 www.panjit.com PJDLLLC70 ELECTRICAL CHARACTERISTICS Parameter Reverse Stand-Off Voltage Symbol Tj = 25°C unless otherwise noted Conditions Min V RWM Typical Max Units 70 V 85 Reverse Breakdown Voltage VBR I BR = 50µA Reverse Leakage Current IR VR = 70V 1 µA Diode Surge Forward Voltage (8/20µs) VFC I pp = 1 A 2 V Diode Surge Forward Voltage (8/20µs) VFC I pp = 5 A 7 V Diode Surge Forward Voltage (8/20µs) VFC I pp = 12 A 13 V Off State Capacitance CT 0 Vdc Bias f = 1MHz Between I/O Line and GND 1.0 pF 0 Vdc Bias f = 1MHz Between I/O lines 1.0 pF 7/23/2009 Page.2 V www.panjit.com PJDLLLC70 PACKAGE DIMENSIONS - SOT563 APPLICATION EXAMPLE (USB2.0 port) 4 and 3 pins connected together through the same Data line D+ D+ Vbus+ (5V or 3.3V) D- D6 and 1 pins connected together through the same Data line 7/23/2009 Page.3 www.panjit.com