PJDLLLC05 Low Capacitance TVS Diode Array This diode array is configured to protect up to two high speed data transmission lines, used in Low Voltage Differential Signal (LVDS) ports. Acting as a line terminator, minimizes overshoot and undershoot conditions due to bus impedance, as well as protect against over-voltage events as electrostatic discharges. The line-line concept minimizes the problems to customers to re-route PCB lines, simplifying the design. SOT563 Package 6 1 2 SPECIFICATION FEATURES Maximum Capacitance of 1.2pF at 0Vdc 1MHz Line-to-Ground 5 4 3 Line2 Line1 Gnd 6 5 4 1 2 3 Maximum Leakage Current of 1.0µA @ VRWM Industry Standard SMT Package SOT563 IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact* 100% Tin Matte finish (LEAD-FREE PRODUCT) APPLICATIONS Line1 Gnd Line2 USB 2.0 and Firewire Port Protection HDMI Version 1.3 Note: pins 1and 6 (Line1), pins 3 and 4 ( Line2) and pins 2 and 5 (Gnd) must be connected externally, as the drawing attached below. DVI MARKING : 05 I/O Data line + 1 6 Ground 2 5 I/O Data line - 3 4 Line-line concept ease the PCB design, directly placing the device over the data lines, opening only the contact points. VREF is fixed by the operating voltage, referenced to the ground. MAXIMUM RATINGS Tj = 25°C Unless otherwise noted Rating Symbol Value Units Peak Pulse Power (8/20µs Waveform) P PPM 50 W Peak Pulse Current (8/20µs Waveform) I PP 6 A Operating Junction Temperature Range TJ -55 to +125 °C Storage Temperature Range Tstg -55 to +150 °C Soldering Temperature, t max = 10s TL 260 °C 7/23/2009 Page 1 www.panjit.com PJDLLLC05 ELECTRICAL CHARACTERISTICS Parameter Reverse Stand-Off Voltage Symbol Tj = 25°C unless otherwise noted Conditions Min VWRM Typical Max Units 5 V 6.2 Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 5V 1.0 µA Clamping Voltage (8/20µs) Vc I pp = 1 A 10 V Clamping Voltage (8/20µs) Vc I pp = 2 A 12 V Clamping Voltage (8/20µs) Vc I pp = 5 A 15 V Off State Junction Capacitance Cj 0 Vdc Bias f = 1MHz Between I/O pins and GND 1.0 pF 0 Vdc Bias f = 1MHz Between I/O pins 1.0 pF 7/23/2009 Page.2 V www.panjit.com PJDLLLC05 PACKAGE DIMENSIONS - SOT563 APPLICATION EXAMPLE (USB2.0 port) 4 and 3 pins connected together through the same Data line D+ D+ 2 and 5 pins connected together To Ground D- D6 and 1 pins connected together through the same Data line 7/23/2009 Page.3 www.panjit.com