PJSR70TB4 Very Low Capacitance Diode Array This diode array is configured to protect up to two high speed data transmission lines, used in Low Voltage Differential Signal (LVDS) ports. Acting as a line terminator, minimizes overshoot and undershoot conditions due to bus impedance as well as protect against over-voltage events as electrostatic discharges. This configuration comes in the new SOT543 package, offering a significative printed circuit board space savings compared to the SOT143. SOT543 Package 4 3 1 2 SPECIFICATION FEATURES Maximum Capacitance of 1.0pF at 0Vdc 1MHz Line-to-Ground Maximum Leakage Current of 1.0µA @ VRWM +VREF New SMT Package SOT543 Line1 4 3 1 2 Gnd Line2 IEC61000-4-2 Full Compliance; 15kV Air, 8kV Contact* 100% Tin Matte finish (LEAD-FREE PRODUCT) APPLICATIONS USB 2.0 and Firewire Port Protection HDMI Version 1.3 DVI MAXIMUM RATINGS Tj = 25°C Unless otherwise noted Rating Symbol Value Units Peak Pulse Current (8/20µs Waveform) I PPM 12 A Rectifier Repetitive Peak Reverse Voltage VRRM 70 V TJ -55 to +125 °C Storage Temperature Range Tstg -55 to +150 °C Soldering Temperature, t max = 10s TL 260 °C Operating Junction Temperature Range Note: ESD Testing requires to connect a TVS between +VREF and GND, if there is no +VREF Bias connected. 2/18/2009 Page 1 www.panjit.com PJSR70TB4 ELECTRICAL CHARACTERISTICS Parameter Reverse Stand-Off Voltage Symbol Tj = 25°C unless otherwise noted Conditions Min Typical V RWM Reverse Breakdown Voltage VBR I BR = 50µA Reverse Leakage Current IR VR = 70V Diode Surge Forward Voltage (8/20µs) VFC Diode Surge Forward Voltage (8/20µs) Max Units 70 V 85 V 1.0 µA I pp = 1A 2.0 V VFC I pp = 5A 7.0 V Diode Surge Forward Voltage (8/20µs) VFC I pp = 12A 12 V Off State Capacitance CT 0 Vdc Bias f = 1MHz Between I/O Line and GND 0.8 1.0 pF 0 Vdc Bias f = 1MHz Between I/O lines 0.5 0.6 pF 2/18/2009 Page 2 www.panjit.com PJSR70TB4 PACKAGE DIMENSIONS - SOT543 4 4 0.038 (1.0) APPLICATION EXAMPLE Vbus+ LVDS D+ D- 2/18/2009 Page 3 IC Controller www.panjit.com