SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
•
•
•
•
•
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Each Device Drives 12 Lines
60-V Output Voltage Swing Capability
25-mA Output Source Current Capability
High-Speed Serially-Shifted Data Input
TTL-Compatible Inputs
Latches on All Driver Outputs
DW OR N PACKAGE
(TOP VIEW)
Q11
Q12
STROBE
SERIAL OUT
DATA IN
VCC1
CLOCK
LATCH ENABLE
Q1
Q2
description
The SN65512B and SN75512B are monolithic
BIDFET † integrated circuits designed to drive a
dot matrix or segmented vacuum fluorescent
display.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
Q10
Q9
Q8
Q7
VCC2
GND
Q6
Q5
Q4
Q3
logic symbol‡
All device inputs are diode-clamped pnp inputs
and assume a high logic level when open
circuited. The nominal input threshold voltage is
1.5 V. Outputs are totem-pole structures formed
by an npn emitter-follower and double-diffused
MOS (DMOS) transistors.
LATCH ENABLE
The device consists of a 12-bit shift register,
12 latches, and 12 output AND gates. Serial data
is entered into the shift register on the low-to-high
transition of CLOCK. When high, LATCH ENABLE
transfers the shift register contents to the outputs
of the 12 latches. The active-low STROBE input
enables all Q outputs. Serial data output from the
shift register can be used to cascade shift
registers. This output is not affected by LATCH
ENABLE or STROBE.
STROBE
8
TTL / VAC
FLUOR DISPLAY
3
SRG12
CLOCK
DATA IN
The SN65512B is characterized for operation
from − 40°C to 85°C. The SN75512B is
characterized for operation from 0°C to 70°C.
7
C1/
5
2D
3
2D
3
2D
3
2D
3
2D
3
2D
3
2D
3
2D
3
2D
3
2D
3
2D
3
2D
3
9
10
11
12
13
14
17
18
19
20
1
2
4
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
SERIAL OUT
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
† BIDFET − Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.
Copyright 1989, Texas Instruments Incorporated
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• DALLAS, TEXAS 75265
• HOUSTON, TEXAS 77251−1443
POST OFFICE BOX 655303
POST OFFICE BOX 1443
4−3
SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
logic diagram (positive logic)
STROBE
LATCH
ENABLE
Shift
Register
Latches
C2
1D
DATA IN
CLOCK
C1
R1
2D
LC1
Q1
LC2
Q2
C2
1D
R2
2D
C1
8 Stages
(Q3 thru Q10)
Not Shown
C2
1D
R11
2D
C1
1D
C1
LC11
Q11
LC12
Q12
C2
R12
2D
SERIAL OUT
FUNCTION TABLE
CONTROL INPUTS
OUTPUTS
SHIFT REGISTER
R1 THRU R12
LATCHES
LC1 THRU LC12
FUNCTION
CLOCK
LATCH
ENABLE
Load
↑
No ↑
X
X
Load and shift†
No change
Determined by LATCH
ENABLE‡
R12
Determined by STROBE
Latch
X
L
H
X
As determined above
Stored data
New data
R12
Determined by STROBE
Strobe
X
X
H
L
As determined above
Determined by LATCH
ENABLE‡
R12
All LC
LC1 thru LC12, respectively
STROBE
SERIAL
Q1 THRU Q12
H = high level, L = low level, X = irrelevant, ↑ = low-to-high-level transition
† R12 takes on the state of R11, R11 takes on the state of R10, . . . R2 takes on the state of R1, and R1 takes on the state of the data input.
‡ New data enter the latches while LATCH ENABLE is high. These data are stored while LATCH ENABLE is low.
4−4
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
typical operating sequence
CLOCK
DATA IN
Valid
Irrelevant
SR
Contents
Invalid
Valid
LATCH
ENABLE
Latch
Contents
Previously Stored Data
New Data Valid
STROBE
Valid
Q Outputs
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC1
OUT
VCC2 for
Q Outputs
VCC1 for
SERIAL OUT
Output
Input
GND
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
4−5
SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC1
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: SN65512B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
SN75512B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTES: 1. Voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
DW
1125 mW
9.0 mW/°C
720 mW
585 mW
N
1150 mW
9.2 mW/°C
736 mW
589 mW
recommended operating conditions
SN65512B
SN75512B
MIN
MAX
MIN
MAX
Supply voltage, VCC1
5
15
5
15
V
Supply voltage, VCC2
0
60
0
60
V
High-level input voltage, VIH
2
2
UNIT
V
Low-level input voltage, VIL
0.8
0.8
V
High-level output current, IOH
−25
−25
mA
5
mA
Low-level output current, IOL
VCC1 = 10 V
VCC1 = 15 V,
Clock frequency, fclock
VCC1 = 5 V,
VCC1 = 15 V,
Pulse duration, CLOCK high or low, tw
Setup time, DATA IN valid before CLOCK ↑, tsu (see Figure 1)
Hold time, DATA IN valid after CLOCK ↑, th (see Figure 1)
VCC1 = 5 V,
VCC1 = 15 V,
VCC1 = 5 V,
VCC1 = 15 V,
VCC1 = 5 V,
5
TA = 25°C
TA = 25°C
0
4
0
4
0
1
0
1
TA = 25°C
TA = 25°C
100
100
500
500
TA = 25°C
TA = 25°C
100
100
250
250
TA = 25°C
TA = 25°C
50
50
250
250
Operating free-air temperature, TA
4−6
−40
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
85
0
MHz
ns
ns
ns
70
°C
SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
electrical characteristics over recommended operating free-air temperature range, VCC2 = 60 V
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
II = − 12 mA
IOH = − 25 mA,
VOH
High-level output voltage
VOL
Low-level output voltage
IIH
IIL
High-level input current
IOL = 200 µA,
VCC1 = 15 V,
Low-level input current
VCC1 = 15 V,
Q outputs
IOH = − 200 µA,
IOL = 5 mA,
SERIAL OUT
Q outputs
SERIAL OUT
ICC1
Supply current from VCC1
VCC1 = 15 V
ICC2
Supply current from VCC2
VCC1 = 15 V
MIN
VCC1 = 10 V
VCC1 = 10 V
TYP†
57.5
58
9
9.5
VCC1 = 10 V
VCC1 = 10 V
MAX
UNIT
−1.5
V
V
2.6
5
0.05
0.2
VI = 5 V
VI = 0.8 V
0.01
1
µA
−25
−150
µA
VI = 5 V
VI = 0.8 V
80
500
µA
2
6
mA
All outputs high
10
100
µA
STROBE at 2 V
0.8
3
mA
MIN
V
† All typical values are at VCC1 = 5 V, TA = 25°C.
switching characteristics, VCC1 = 10 V, VCC2 = 60 V, TA = 25°C
MAX
UNIT
tPHL
tPLH
Propagation delay time, high-to-low level output
PARAMETER
TEST CONDITIONS
300
ns
Propagation delay time, low-to-high level output
300
ns
tTHL
tTLH
Transition time, high-to-low level output
500
ns
500
ns
CL = 30 pF,
Transition time, low-to-high level output
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
See Figure 2
4−7
SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
PARAMETER MEASUREMENT INFORMATION
tw
VIH
1.5 V
CLOCK
VIL
tw
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
th
tsu
VIH
Valid
DATA IN
VIL
Figure 1. Input Timing Voltage Waveforms
≤ 30 ns
≤ 30 ns
STROBE
10%
tPLH
3V
90%
1.5 V
0V
tPHL
90%
Q Outputs
10%
VOH
VOL
tTHL
tTLH
Figure 2. Switching Time Voltage Waveforms
4−8
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
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