SCBS180A − JUNE 1992 − REVISED JULY 1994 • • • • • Members of the Texas Instruments Widebus + Family State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation UBE (Universal Bus Exchanger) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 • • • • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise High-Drive Outputs (− 32-mA IOH, 64-mA IOL ) Bus Hold Inputs Eliminate the Need for External Pullup/Pulldown Resistors Packaged in 80-Pin Plastic Thin Quad Flat (PN) Package With 12 × 12-mm Body Using 0.5-mm Lead Pitch C11 C10 C9 A1 SELA OEA OEC SELC LEC CLKC C18 C17 VCC GND C16 C15 C14 C13 C12 GND SN74ABT32318 . . . PN PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 A2 A3 A4 GND A5 A6 A7 A8 A9 VCC GND A10 A11 A12 A13 A14 GND A15 A16 A17 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 41 20 C8 C7 C6 GND C5 C4 C3 C2 C1 VCC GND B18 B17 B16 B15 B14 GND B13 B12 B11 A18 CLKA LEA OEB SELB LEB CLKB B1 B2 VCC GND B3 B4 B5 B6 B7 GND B8 B9 B10 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Widebus+, EPIC-ΙΙB, and UBE are trademarks of Texas Instruments Incorporated. Copyright 1994, Texas Instruments Incorporated !"# $%&'()* &%*+"*# "*,%-(+"%* &'--)* +# %, .'/0"&+"%* $+)1 -%$'&# &%*,%-( % #.)&","&+"%*# .)- !) )-(# %, )2+# *#-'()*# #+*$+-$ 3+--+*41 -%$'&"%* .-%&)##"*5 $%)# *% *)&)##+-"04 "*&0'$) )#"*5 %, +00 .+-+())-#1 • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 5−1 SCBS180A − JUNE 1992 − REVISED JULY 1994 description The ′ABT32318 consists of three 18-bit registered input/output (I/O) ports. These registers combine D-type latches and flip-flops to allow data flow in transparent, latch, and clock modes. Data from one input port can be exchanged to one or more of the other ports. Because of the universal storage element, multiple combinations of real-time and stored data can be exchanged among the three ports. Data flow in each direction is controlled by the output-enable (OEA, OEB, and OEC), select-control (SELA, SELB, and SELC), latch-enable (LEA, LEB, and LEC), and clock (CLKA, CLKB, and CLKC) inputs. The A data register operates in the transparent mode when LEA is high. When LEA is low, data is latched if CLKA is held at a high or low logic level. If LEA is low, data is stored on the low-to-high transition of CLKA. Output data selection is accomplished by the select-control pins. All three ports have active-low output enables, so when the output-enable input is low, the outputs are active; when the output-enable input is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABT32318 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74ABT32318 is characterized for operation from − 40°C to 85°C. 5−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCBS180A − JUNE 1992 − REVISED JULY 1994 Function Tables STORAGE† INPUTS A OUTPUT CLKA LEA ↑ L L L ↑ L H H H L X L L X Q0‡ Q0‡ X H L L X H H H † A-port register shown. B and C ports are similar but use CLKB, CLKC, LEB, and LEC. ‡ Output level before the indicated steady-state input conditions were established. A-PORT OUTPUT INPUTS OUTPUT A OEA SELA H X Z L H Output of C register L L Output of B register B-PORT OUTPUT INPUTS OEB OUTPUT B SELB H X Z L H Output of A register L L Output of C register C-PORT OUTPUT INPUTS OUTPUT C OEC SELC H X L H Output of B register L L Output of A register Z • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5−3 SCBS180A − JUNE 1992 − REVISED JULY 1994 logic diagram (positive logic) OEC SELC CLKC LEC C1 OEB SELB CLKB LEB B1 OEA SELA CLKA LEA A1 5−4 77 76 Q CLK 74 75 LE D 52 24 25 Q CLK 27 26 LE D 28 78 79 Q CLK 22 23 LE D 80 1 of 18 Channels • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • SCBS180A − JUNE 1992 − REVISED JULY 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . −0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT32318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT32318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 3) SN54ABT32318 SN74ABT32318 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC −24 Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate 10 10 ns / V ∆t /∆VCC Power-up ramp rate High-level input voltage 2 2 0.8 Input voltage 0 Outputs enabled 200 TA Operating free-air temperature NOTE 3: Unused or floating control pins must be held high or low. −55 0 V 0.8 V VCC −32 V −40 mA µs / V 200 125 V 85 °C "*,%-(+"%* &%*&)-*# .-%$'&# "* !) ,%-(+"6) %$)#"5* .!+#) %, $)6)0%.()*1 !+-+&)-"#"& $++ +*$ %!)#.)&","&+"%*# +-) $)#"5* 5%+0#1 )2+# *#-'()*# -)#)-6)# !) -"5! % &!+*5) %- $"#&%*"*') !)#) .-%$'&# 3"!%' *%"&)1 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5−5 SCBS180A − JUNE 1992 − REVISED JULY 1994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH II II(hold) MIN VCC = 4.5 V, VCC = 4.5 V, II = −18 mA IOH = − 3 mA VCC = 5 V, IOH = − 3 mA IOH = − 24 mA VCC = 4.5 V VOL SN54ABT32318 TYP† MAX TEST CONDITIONS −1.2 −1.2 2.5 2.5 3 3 UNIT V V 2 IOH = − 32 mA IOL = 48 mA VCC = 4.5 V SN74ABT32318 TYP† MAX MIN 2 Control inputs VCC = 0 to 5.5 V, IOL = 64 mA VI = VCC or GND A, B, or C ports VCC = 2.1 V to 5.5 V, VI = VCC or GND A, B, or C ports VCC = 4.5 V VI = 0.8 V VI = 2 V 0.55 0.55 0.55 0.55 ±1 ±1 ± 20 ± 20 100 100 −100 −100 V µA µA A IOZPU‡ VCC = 0 to 2.1 V, OE = X VO = 0.5 V to 2.7 V, ± 50 ± 50 µA IOZPD‡ VCC = 2.1 V to 0, OE = X VO = 0.5 V to 2.7 V, ± 50 ± 50 µA IOZH§ IOZL§ VCC = 2.1 V to 5.5 V, VCC = 2.1 V to 5.5 V, VO = 2.7 V, VO = 0.5 V, 10 10 µA −10 −10 µA Ioff ICEX IO¶ VCC = 0, VCC = 5.5 V, VI or VO ≤ 4.5 V VO = 5.5 V Outputs high ±100 ±100 µA VCC = 5.5 V, VO = 2.5 V Outputs high VCC = 5.5 V, IO = 0, VI = VCC or GND ICC OE ≥ 2 V OE ≥ 2 V 50 −50 −100 Outputs low Outputs disabled VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ∆ICC# Ci Control inputs VI = 2.5 V or 0.5 V Cio A, B, or C ports VO = 2.5 V or 0.5 V −180 −50 −100 2 45 45 1 1 0.5 0.5 • mA mA 3 3 pF 11.5 11.5 pF POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • µA mA 2 † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter is specified by characterization. § The parameters IOZH and IOZL include the input leakage current. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 5−6 50 −180 SCBS180A − JUNE 1992 − REVISED JULY 1994 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT32318 MIN fclock Clock frequency tw Pulse duration tsu Setup time th Hold time MAX SN74ABT32318 MIN 150 MAX 150 LE high 3.3 3.3 CLK high or low 3.3 3.3 A, B, or C before CLK↑ 2.4 2.4 A, B, or C before LE↓ 2.1 2.1 A, B, or C after CLK↑ 1.4 1.4 A, B, or C after LE↓ 2.1 2.1 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) SN54ABT32318 MIN MAX 150 A, B, or C C, B, or A SEL C, B, or A LE C, B, or A CLK C, B, or A OE C, B, or A OE C, B, or A SN74ABT32318 MIN MAX 150 UNIT MHz 1.4 6.5 1.4 6.1 1.1 6.8 1.1 6.6 1.4 6.7 1.4 6.5 1.8 6.8 1.8 6.5 2.6 8 2.6 7.5 2.6 7.4 2.6 6.9 2.5 8 2.5 7.4 2.5 7.2 2.5 6.7 1.4 6.9 1.4 6.8 2.4 7.2 2.4 7.1 1 6.4 1 6.2 2 6.4 2 6 ns ns ns ns ns ns "*,%-(+"%* &%*&)-*# .-%$'&# "* !) ,%-(+"6) %$)#"5* .!+#) %, $)6)0%.()*1 !+-+&)-"#"& $++ +*$ %!)#.)&","&+"%*# +-) $)#"5* 5%+0#1 )2+# *#-'()*# -)#)-6)# !) -"5! % &!+*5) %- $"#&%*"*') !)#) .-%$'&# 3"!%' *%"&)1 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5−7 SCBS180A − JUNE 1992 − REVISED JULY 1994 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input (see Note B) 1.5 V 0V Output 1.5 V VOL tPLH tPHL Output Waveform 2 S1 at Open (see Note C) VOH Output 1.5 V 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note C) VOH 1.5 V 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 5−8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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