SDZS015 − MAY 1990 − REVISED OCTOBER 1990 • • • • • • DW OR NT PACKAGE (T0P VIEW) 10KH Compatible ECL and TTL Control Inputs 1Q 2Q 3Q 4Q VCC GND GND GND 5Q 6Q 7Q 8Q Noninverting Outputs Flow-Through Architecture Optimizes PCB Layout Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise Package Options Include “Small Outline” Packages and Standard Plastic 300-mil DIPs 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 1D 2D 3D 4D OE (TTL) VEE GND LE (ECL) 5D 6D 7D 8D description This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The eight latches of the SN10KHT5573 are transparent D-type latches. While latch enable (LE) is low, the Q outputs follow the data (D) inputs. When LE is high, the Q outputs are latched at the levels that were set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components. Output-enable OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. The SN10KHT5573 is characterized for operation from 0° to 75°C. logic symbol† FUNCTION TABLE OUTPUT CONTROL DATA INPUT OUTPUT (TTL) OE LE D Q L L L L L L H H L H X Q0 H X X Z LE OE 1D 2D 3D 4D 5D 6D 7D 8D 17 20 24 ECL/TTL C1 EN 1D ECL/TTL 1 23 2 22 3 21 4 16 9 15 10 14 11 13 12 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright 1990, Texas Instruments Incorporated ! " #$%! " &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%" %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"* • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 SDZS015 − MAY 1990 − REVISED OCTOBER 1990 logic diagram (positive logic) OE LE 20 17 ECL/TTL 1 C1 1D 24 1Q 1D ECL/TTL 2 2Q C1 2D 23 ECL/TTL 1D 3 C1 3D 22 ECL/TTL 1D 4 C1 4D 21 3Q ECL/TTL 4Q 1D 9 5Q C1 16 5D ECL/TTL 1D 10 C1 15 6D 6Q 1D ECL/TTL 11 7Q C1 7D 14 ECL/TTL 1D 12 C1 8D 2 13 ECL/TTL 1D • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 8Q SDZS015 − MAY 1990 − REVISED OCTOBER 1990 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V to 0 V Input voltage range, TTL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V Input voltage range, ECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V Input current range, TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Voltage applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditions MIN NOM MAX VCC VEE TTL supply voltage 4.5 5 5.5 V ECL supply voltage −4.94 −5.2 −5.46 V VIH VIL TTL high-level input voltage TTL low-level input voltage 0.8 V IIK TTL input clamp current −18 mA VIH ECL high-level input voltage (see Note 2) VIL IOH IOL 2 ECL low-level input voltage (see Note 2) UNIT V 0°C −1170 −840 25°C −1130 −810 75°C −1070 −735 0°C −1950 −1480 25°C −1950 −1480 75°C −1950 −1450 mV mV High-level output current −15 mA Low-level output current 48 mA TA Operating free-air temperature 0 75 °C NOTE 2: The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SDZS015 − MAY 1990 − REVISED OCTOBER 1990 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II OE only IIH IIL OE only IIH IIL TEST CONDITIONS MIN TYP† MAX VCC = 4.5 V, VCC = 5.5 V, VEE = − 4.94 V, VEE = − 5.46 V, II = − 18 mA VI = 7 V OE only VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V, VEE = − 5.46 V, VI = 2.7 V VI = 0.5 V VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V, VEE = − 5.46 V, VI = − 840 V VI = − 810 V 0°C 350 Data inputs and LE 25°C 350 VCC = 5.5 V, VEE = − 5.46 V, VI = − 735 V 75°C 350 VCC = 5.5 V, VEE = − 5.46 V, VI = − 1950 V OE only Data inputs and LE VOH VCC = 4.5 V, VCC = 4.5 V, IOH = − 3 mA, IOH = − 15 mA, VEE = − 5.2 V ± 5% VEE = − 5.2 V ± 5% VOL IOZH VCC = 4.5 V, VCC = 5.5 V, IOL = 48 mA, VO = 2.7 V, VEE = − 5.2 V ± 5% VEE = − 5.46 V IOZL IOS‡ VCC = 5.5 V, VCC = 5.5 V, VO = 0.5 V, VO = 0 V, VEE = − 5.46 V VEE = − 5.46 V ICCH ICCL VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V VEE = − 5.46 V ICCZ IEE VCC = 5.5 V, VCC = 5.5 V, VEE = − 5.46 V VEE = − 5.46 V Ci VCC = 5 V, VCC = 5 V, VEE = − 5.2 V VEE = − 5.2 V 0°C 0.5 25°C 0.5 75°C 0.5 V 0.1 mA 20 µA −0.5 mA µA µA 2.4 3.3 2 3.1 0.38 V 0.55 V 50 µA −50 µA −225 mA 62 89 mA 78 111 mA 75 108 mA −34 −48 mA −100 Co † All typical values are at VCC = 5 V, VEE = − 5.2 V, and TA = 25°C. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. UNIT −1.2 5 pF 7 pF timing requirements VCC = 4.5 V to 5.5 V, VEE = − 4.94 V to − 5.46 V, TA = MIN to MAX§ MIN tw tsu MAX Pulse duration, LE high 4 ns Setup time, data before LE↓ 1 ns th Hold time, data after LE↓ 1 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 UNIT • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • ns SDZS015 − MAY 1990 − REVISED OCTOBER 1990 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX MIN TYP† MAX 1.9 3.9 6.4 2.3 4.2 6.8 2.2 4 6.7 2.6 4.5 7.2 1.1 3.2 5.9 2.3 4.6 7.8 1.8 4 5.9 0.6 3.4 6.5 UNIT ns ns ns ns † All typical values are at VCC = 5 V, VEE = − 5.2 V, and TA = 25°C. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 5 SDZS015 − MAY 1990 − REVISED OCTOBER 1990 PARAMETER MEASUREMENT INFORMATION 7V Open SWITCH POSITION TABLE S1 From Output Under Test Test Point CL (See Note A) S1 Open Open Open Closed Open Closed TEST tPLH tPHL tPZH tPZL tPHZ tPLZ R1 R2 LOAD CIRCUIT tf tr ECL Input (See Note B) 80% 80% 50% 20% −890 mV 50% 20% −1690 mV −1690 mV −890 mV Low-Level Input VOH Out-of-Phase TTL Output 50% 50% tw tPLH tPHL −890 mV High-Level Input 50% 50% −1690 mV 1.5 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION VOL tPLH tPHL VOH In-Phase TTL Output 1.5 V 1.5 V 3V Output Control (Low-Level Enabling) (See Note C) VOL VOLTAGE WAVEFORMS ECL-INPUT PROPAGATION DELAY TIMES 1.5 V 1.5 V 0 tPZL tPLZ tr Timing Input tf 20% 80% 80% 50% 50% tsu Data Input 20% 20% Output Waveform 1 (See Note D) −890 mV 80% 80% 50% tPZH −890 mV 50% 20% tr 1.5 V −1690 mV th Output Waveform 2 (See Note D) −1690 mV tf 3.5 V tPHZ VOL 0.3 V VOH 1.5 V 0.3 V 0 VOLTAGE WAVEFORMS TTL ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS SETUP AND HOLD TIMES NOTES: A. CL includes probe and jig capacitance. B. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 1.5 ns, tf ≤ 1.5 ns. C. For TTL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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