SLLS125A − OCTOBER 1990 − REVISED NOVEMBER 1993
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Supports Distributed Arbitration for
Futurebus+ Master Selection
Supports Arbitrated Messages in
Distributed and Central Modes
Enables Use of a Common Hardware and
Software Interface for Both Distributed and
Central Modes
Requires No Hardware Modifications for
Changing Between Distributed and Central
Modes
Provides a CSR Bus Interface for Easy
Integration into the Futurebus+ CSR
Address Space
Has Two Bus Request Lines That Each May
Be Assigned Any One of 256 Priority Levels
Supports Round-Robin Fairness Arbitration
Within Two Separate Priority Levels to
Avoid Starvation of Any Single Module
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Supports Distributed-Mode Bus Parking to
Improve Performance of Successive Bus
Acquisitions By a Single Module During
Idle Bus Conditions
Offers Accurate Arbitration Settling Time
and Glitch Filter Programmability to Allow
Optimal Arbitration Bus Performance
Provides a FIFO for Capturing up to Four
Incoming Arbitrated Messages
Provides Hardware Support of Targeted
Interrupts
Supports Power-Fail Message Indication
With a Separate Terminal and Interrupt
Provides On-Chip Error Time-Out Detection
Has a JTAG Test Port
description
The TFB2010 arbitration bus controller (ABC) is a member of the Texas Instruments Futurebus+ chip set. This
chip set provides an integrated approach to the Futurebus+ interface that reduces new-product design time,
allows more functionality per circuit board, improves overall interface reliability, and reduces end-user down time
through built-in test capabilities.
The TFB2010 performs the Futurebus+ distributed-arbitration protocol to gain tenure of the bus (distributed
mode only), to send and receive arbitrated messages (central or distributed mode), and to update central-mode
arbiter priorities (central mode only).
The TFB2010 can be used in conjunction with a central-bus arbiter as an arbitrated-message controller to
program the central-bus arbiter, send asynchronous interrupts, or send event messages or interrupts to other
modules. In the case of a failure in the central-bus arbiter or if distributed arbitration is desired, it can be used
as a distributed-arbitration controller without a change in the host software. Priority changes are sent to the
central arbiter as arbitrated messages. This device monitors the bus for arbitration messages, storing these in
a FIFO or in the targeted interrupt register for reference by the processor. It also provides the necessary control
functions to gain control of the Futurebus+ for a module attempting to perform a bus transaction when operating
in the distributed-arbitration mode.
The TFB2010 is offered in a 100-pin plastic quad flat package (PJM) to enhance interface capability. The
TFB2010 is characterized for operation over the commercial temperature range of 0°C to 70°C.
NOTE: To maintain consistency with the notation used in the Futurebus+ standard (IEEE Std 896.1−1991), an active low-signal is denoted herein
by use of the trailing asterisk (*) on the signal name.
Copyright 1993, Texas Instruments Incorporated
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
7−1
SLLS125A − OCTOBER 1990 − REVISED NOVEMBER 1993
terminal assignments
CD4
CD5
VCC
CD6
CD7
CDP
GND
CA0
CA1
CA2
VCC
CA3
CA4
CA5
GND
CA6
CA7
CA8
VCC
CA9
PJM . . . PACKAGE
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
CD3
GND
CD2
CD1
CD0
VCC
COE*
CCE*
CWE*
GND
REFCLK
GND
RST*
BINIT*
SYSRESET*
VCC
BUSI*
ARBERR1
ARBERR0
GND
RQ1
RQ0
GR
VCC
PE
CENTMODE
CN0
CN1
CN2
GND
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
OEA
API
APO
GND
AQI
AQO
ARI
ARO
CN6
CN7
CNP
GND
WIN
LE*
CMPT*
VCC
CN3
CN4
CN5
VCC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC − No internal connection
7−2
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77251−1443
CA10
CA11
GND
GA4*
GA3*
GA2*
GA1*
GA0*
VCC
TMS
TCK
TDI
TDO
NC
GND
CLK
GND
PFAIL*
INT*
REF
VCC
NC
ASI
REI
GND
ACO0
ACI0
ACO1
ACI1
VCC
SLLS125A − OCTOBER 1990 − REVISED NOVEMBER 1993
Terminal Functions
CSR bus
TERMINAL
NAME
CA<11:0>
NO.
79,80,81,83,
84,85,87,88,
89,91,92,93
CCE*
I/O
FROM/TO
DESCRIPTION
I
CSR bus
CSR bus address inputs
8
I
CSR bus
CSR bus chip enable input
96,97,99,
100,1,3,4,5
I/O
CSR bus
CSR bus data
CDP
95
I/O
CSR bus
CSR bus data odd parity
COE*
7
I
CSR bus
CSR bus output enable input
CWE*
9
I
CSR bus
CSR bus write enable input
CD<7:0>
protocol controller interface
TERMINAL
I/O
FROM/TO
DESCRIPTION
NAME
NO.
ARBERR<1:0>
18,19
O
Arbitration error outputs:
LL
No error
LH
AC0 and AC1 asserted during phase 3
HL
Arbitration comparison error or parity error
HH
Arbitration time-out error (phase 2 or 4)
GR
23
O
Futurebus + mastership has been granted output (bus tenure may begin). This signal remains
in the high-impedance state while in the central-bus arbitration mode.
PE
25
I/O
In distributed mode when this device is the bus master, the TFB2010 asserts PE to indicate
that a module with a higher priority has become the master elect. PE is released along with
GR when RQ1 and RQ0 are released. In central mode, the TFB2010 puts this output in a
high-impedance state to allow the central-arbitration controller to control preemption. PE is
monitored by the TFB2010 during a Futurebus + system reset to determine the system
operational mode (central or distributed) following the reset.
21,22
I
RQ<1:0>
Futurebus + mastership is requested in centralized mode input:
RQ0 asserted:
use arbitration number in the RQ0 priority register
RQ1 asserted:
use arbitration number in the RQ1 priority register
Once a request is asserted, it is not released until GR* has been asserted (the TI protocol
controllers perform this handshake internally). Once GR* is asserted, RQn* may be released
at any time after AS has been asserted by the module in the last bus transaction (AS may
already be released if no further transactions are to take place). Both request lines must be
released prior to release of GR*. Another RQn* can be asserted after GR* and PE have been
released.
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POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
7−3
SLLS125A − OCTOBER 1990 − REVISED NOVEMBER 1993
Terminal Functions
other module interfaces
TERMINAL
NAME
I/O
NO.
FROM/TO
CLK
65
I
INT*
62
O
(open-collector)
PFAIL*
63
O
REFCLK
11
I
DESCRIPTION
Clock input. CLK is used by the CSR bus master(s).
Host interrupt output. When an enabled interrupt condition occurs, INT is driven low.
Interrupts are cleared by writing a zero to the appropriate bit in the interrupt register. The
interrupt goes high during the write cycle to the interrupt register even if another interrupt
is pending.
Power-fail message received output
Module
Clock input. The recommended frequency and duty cycle are 33 MHz, 50% ± 5%;
25 MHz to 33 MHz and 50% ± 5% can be tolerated.
JTAG test port
TERMINAL
NAME
NO.
I/O
FROM/TO
DESCRIPTION
I
Module
JTAG test clock input
TCK
70
TDI
69
I
Module
JTAG test data input
TDO
68
O
Module
JTAG test data output
TMS
71
I
Module
JTAG test mode select input
I/O
FROM/TO
DESCRIPTION
I
Module
Bus interface reset input. BINIT is an open-collector signal indicating that a bus interface
reset is required
reset port
TERMINAL
NAME
NO.
BINIT*
14
BUSI*
17
I
Bus has been idle for longer than 1 µs, and reset is asserted by this module.
REF
61
O
Futurebus+ reset filtered output
REI
57
I
RST*
13
I
Module
Module power-up reset input. RST resets all logic; output signals go to their inactive states;
3-state outputs and bidirectionals go to the high-impedance state (for live-insertion
considerations).
SYSRESET*
15
I
Module
System reset input. SYSRESET* signal indicates that a system reset is required.
7−4
Futurebus+ reset input
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
SLLS125A − OCTOBER 1990 − REVISED NOVEMBER 1993
Terminal Functions
Futurebus+ interface
TERMINAL
NAME
I/O
NO.
DESCRIPTION
ACI<1:0>
52,54
I
Futurebus+ arbitration condition input
ACO<1:0>
53,55
O
Futurebus+ arbitration condition output
API, AQI, ARI
44,47,49
I
Futurebus+ arbitration handshake input
APO, AQO, ARO
45,48,50
O
Futurebus+ arbitration handshake output
ASI
58
I
Futurebus+ address handshake input
CENTMODE
26
O
Central-mode operation is in effect output
CMPT*
41
O
Arbitration contest logic compete indication output. Connects to COMPETE and OEB on the
competition transceiver.
CN<7:0>, CNP
36,35,33,32,31,
29,28,27,37
I/O
Futurebus+ contest number and parity
GA<4:0>*
77,76,75,74,73
I
Futurebus+ geographical address input
LE*
40
O
Enable latch on competition transceiver output (1 = competition number latched)
OEA
43
O
Enable TTL drivers on competition transceiver output
WIN
39
I
Arbitration contest logic win indication input
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
PJM
1500 mW
12 mW/°C
960 mW
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
0.8
V
−0.5
0
70
°C
2
Low-level input voltage, VIL
Operating free-air temperature range, TA
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
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7−5
SLLS125A − OCTOBER 1990 − REVISED NOVEMBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
MACRO
VIT Input threshold voltage
VIT + Positive-going input threshold voltage
IPI04LK
VIT − Negative-going input threshold voltage
VOH High-level output voltage
IPI09LK
TEST CONDITIONS
VI = VCC or 0 V,
II = ± 1 µA,
CL = 7.4 pF
IPI09LK
VOL Low-level output voltage
VOH High-level output voltage
VOL Low-level output voltage
VOH High-level output voltage
VOL Low-level output voltage
VOL Low-level output voltage
MIN
3.7
OPJ43LK
IOH = − 4 mA
IOL = 4 mA
3.7
OPJ83LK
IOH = − 8 mA
IOL = 8 mA
IOH = − 4 mA
IOL = 4 mA
3.7
OPI43LK
OPI42LK
IOL = 4 mA
TYP
MAX
UNIT
1.3
V
1.6
V
1.2
V
V
0.5
V
V
0.5
V
V
0.5
V
0.5
V
macros
Table 1 lists the internal and external buffer macros used in the TFB2010 design. To use this table, find the pin
of interest and note the macro name(s). If there is an entry only in the input macro column, the pin is an input.
If there is an entry only in the output macro column, the pin is an output. If there is an entry in both columns,
this is a 3-state bidirectional pin. The macro(s) are also listed in the electrical characteristics table.
Table 1. TFB2010 (ABC) Pin Names and Macro Numbers
PIN NAME
ACI<1:0>
INPUT MACRO
ACO<1:0>
API
PIN NAME
OPI43LK
IPI04LK
APO
AQI
OUTPUT MACRO
IPI04LK
OPI43LK
IPI04LK
IPI04LK
CWE*
IPI04LK
GA<4:0>*
IPI04LK
OPI43LK
INT*
OPI42LK
OPI43LK
OPI43LK
LE*
ARBERR<1:0>
OPI43LK
OEA
IPI04LK
PE
OPI43LK
OUTPUT MACRO
GR
AQO
ARI
INPUT MACRO
COE*
OPI43LK
IPI04LK
OPI43LK
PFAIL*
OPI43LK
ASI
IPI04LK
REF
OPI43LK
BINIT*
IPI09LK
REFCLK
IPI04LK
BUSI*
IPI09LK
REI
IPI04LK
CA<11:0>
IPI04LK
RQ<1:0>
IPI04LK
CCE*
IPI04LK
RST*
IPI09LK
CD<7:0>
IPI04LK
OPJ83LK
SYSRESET*
IPI09LK
CDP
IPI04LK
OPJ83LK
TCK
IPI04LK
OPI43LK
TDI
IPI04LK
ARO
CENTMODE
CLK
IPI04LK
CMPT*
TDO
OPI43LK
OPI43LK
TMS
IPI04LK
CN<7:0>
IPI04LK
OPI43LK
WIN
IPI04LK
CNP
IPI04LK
OPI43LK
7−6
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS
77251−1443
SLLS125A − OCTOBER 1990 − REVISED NOVEMBER 1993
MECHANICAL DATA
100-Pin Plastic Quad Flat Package (PJM Package)
23,45
22,95
20,2 NOM
30
1
31
100
17,45
16,95
14,0 NOM
50
81
51
80
0,30 NOM
0,65 NOM
3,50 MAX
0° - 7°
0,95
0,65
0,15 NOM
0,25 MIN
Seating Plane
Leads are coplanar to within 0,1 mm.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
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77251−1443
7−7
7−8
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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77251−1443
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