SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993 • DW OR N PACKAGE (TOP VIEW) Four Modes of Operation: Hold (Store) Shift Right Shift Left Load Data Operates With Outputs Enabled or at High Impedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for N-Bit Word Lengths Synchronous Clear Applications: Stacked or Push-Down Registers Buffer Storage Accumulator Registers Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs • • • • • • S0 OE1 OE2 G/QG E/QE C/QC A /QA QA′ CLR GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC S1 SL QH′ H/QH F/QF D/QD B/QB CLK SR description This 8-bit universal register features multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) and two output-enable (OE1, OE2) inputs can be used to choose the modes of operation listed in the function table. Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but this has no effect on clearing, shifting, or storage of data. The SN74F323 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS MODE Clear OE2† I/O PORTS OUTPUTS CLR S1 S0 OE1† CLK SL SR A /QA B/QB C/QC D/QD QA′ QH′ L L L ↑ X X L L L L F/QF L H/QH X E/QE L G/QG L L L L L L L X L L ↑ X X L L L L L L L L L L L H H X X ↑ X X X X X X X X X X L L H L L L L X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 H X X L L L X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 Shift Right H L H L L ↑ X H H QAn H L L ↑ X L L QAn QCn QCn QDn QDn QEn QEn QFn QFn QGn QGn QGn L QBn QBn H H L QGn Shift Left H H L L L ↑ H X QBn QCn L L L ↑ L X QBn QCn QEn QEn QFn QFn QGn QGn QHn QHn L QBn QBn H H QDn QDn H H Load H H H X X ↑ X X a b c d e f g h a h Hold L NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. These data inputs are loaded into the flip-flops while the flip-flop outputs are isolated from the I/O terminals. † When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. Copyright 1993, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 2−1 SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993 logic symbol† CLR 9 SRG8 4R 2 OE1 OE2 S0 S1 CLK SR A /QA & 3EN5 3 1 19 12 11 7 0 M 1 0 3 C4/1→/2← 1, 4D 8 3, 4D QA′ 5 B /QB 13 3, 4D 5 C/QC D/QD E/QE F/QF G/QG H/QH SL 6 14 5 15 4 16 18 3, 4D 17 5 2, 4D † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2−2 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • QH′ SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993 logic diagram (positive logic) CLR S0 S1 SR (shift right serial input) CLK 9 1 19 18 11 Six Identical Channels Not Shown† 12 1D 1D C1 QA′ OE1 OE2 SL (shift left serial input) C1 8 17 QH′ 2 3 7 16 A/QA H/QH † I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4). absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC Current into any output in the low state: QA′ or QH′ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA QA thru QH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−3 SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993 recommended operating conditions VCC VIH Supply voltage VIL IIK Low-level input voltage High-level input voltage MIN NOM MAX 4.5 5 5.5 2 High-level output current IOL Low-level output current TA Operating free-air temperature V V Input clamp current IOH UNIT 0.8 V −18 mA QA′ or QH′ −1 QA thru QH −3 QA′ or QH′ 20 QA thru QH 24 0 70 mA mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, QA thru QH Any output VOL QA′ or QH′ QA thru QH VCC = 4.5 V VCC = 4.75 V, VCC = 4.5 V IIH‡ Any other 2.5 3.4 IOH = − 1 mA IOH = − 3 mA 2.5 3.4 2.4 3.3 IOH = − 1 mA to − 3 mA IOL = 20 mA 2.7 IOL = 24 mA VI = 5.5 V A thru H II TYP† II = − 18 mA IOH = − 1 mA QA′ or QH′ VOH MIN TEST CONDITIONS VCC = 5.5 V S0 or S1 V V 0.5 0.5 VI = 7 V VI = 2.7 V VCC = 5.5 V, VI = 0.5 V V 1 0.1 70 VCC = 5.5 V, 20 mA µA A −0.65 Any other −1.2 mA −0.6 IOS§ VCC = 5.5 V, VO = 0 −60 ICC VCC = 5.5 V, See Note 2 68 † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. § Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 2: ICC is measured with OE1, OE2, and CLK at 4.5 V. 2−4 −1.2 0.3 A thru H IIL‡ UNIT 0.35 A thru H Any other MAX • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • −150 mA 95 mA SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25°C fclock tw tsu th Clock frequency Pulse duration CLK high or low Setup time before CLK↑ CLK↑ Hold time after CLK MIN MAX 0 70 MIN MAX UNIT 0 70 MHz 7 7 8.5 8.5 S0 or S1 High or low A /QA thru H/QH, SR, or SL High or low 5 5 CLR High or low 10 10 S0 or S1 High or low 0 0 A/QA thru H/QH, SR, or SL CLR High or low 2 2 High or low 0 0 ns ns ns switching characteristics (see Note 3) PARAMETER fmax tPLH tPHL FROM (INPUT) TO (OUTPUT) CLK QA A′ or QH H′ tPLH tPHL CLK QA thru QH tPZH tPZL OE1 or OE2 QA thru QH tPHZ tPLZ OE1 or OE2 QA thru QH VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C MIN TYP VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† MAX MIN UNIT MAX 70 100 3.2 6.6 9 3.2 70 10 MHz 2.7 6.1 8.5 2.7 9.5 3.2 6.6 9 3.2 10 4.2 8.1 11 4.2 12 2.7 5.6 8 2.7 9 3.2 6.6 10 3.2 11 1.7 4.1 6 1.7 7 1.2 3.6 5.5 1.2 6.5 ns ns ns ns † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 3: Load circuits and waveforms are shown in Section 1. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2−5 SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993 2−6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74F323DW OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74F323DWR OBSOLETE SOIC DW 20 TBD Call TI Call TI SN74F323N OBSOLETE PDIP N 20 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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