TOSHIBA TC62D722CFG

TC62D722CFG/CFNG
TOSHIBA CDMOS Integrated Circuit Silicone Monolithic
TC62D722CFG, TC62D722CFNG
16-Output constant current LED driver with the output gain control function and the PWM grayscale function
Feature
The TC62D722 series are LED drivers which have the sink-type
constant current output. This IC is most suitable for lighting the LED
module and the display.
The output gain control function of 8-bit and the PWM grayscale
function of 16, 14, 12, and 10-bit are built into this IC.
Output current value of 16 channels is set by one external
resistance.
In addition, the thermal shutdown function, the output open
detection function, and the output short detection function are built
in.
Characteristics

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

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





TC62D722CFG
SSOP24-P-300-1.00B
TC62D722CFNG
HTSSOP24-P-300-0.65
Supply voltage
: VDD  3.0 to 5.5 V
Weight
16-output built-in
SSOP24-P-300-1.00B : 0.32 g (Typ.)
Output current setup range
: IOUT  1.5 to 90 mA
HTSSOP24-P-300-0.65 : 0.10 g (Typ.)
Constant current output accuracy
(@ REXT = 1.2 k, VOUT = 1.0 V, VDD = 3.3 V, 5.0 V)
: S rank；Between outputs  1.5 % (max), Between devices:  1.5 % (max)
: N rank；Between outputs  2.5 % (max), Between devices:  2.5 % (max)
Output voltage
: VOUT  17 V (MAX)
I/O interface
: CMOS interfaces (Input of a schmitt trigger)
Data transfer frequency
: fSCK  30 MHz (MAX)
PWM frequency
: fPWM  33 MHz (MAX)
Operation temperature range
: Topr  40 to 85 C
8-bit (256 steps) output gain control function built-in.
PWM gray scale function built-in. (PWM resolution is selectable)
16-bit (65536 steps), 14-bit (16384 steps)
12-bit (4096 steps), 10-bit (1024 steps)
Thermal shutdown function (TSD) built-in.
Output error detection function built-in.
This function has the automatic operation and the command input manual operation.
Output open detection function (OOD) and output short detection function (OSD) built-in.
Power-on-reset function built-in. (When the power supply is turned on, internal data is reset)
Stand-by function built-in. (IDD=1μA at standby mode)
Output delay function built-in. (Output switching noise is reduced)
Package
CFG type
: SSOP24-P-300-1.00B
CFNG type
: HTSSOP24-P-300-0.65
Please ask Toshiba sales dept or agent for details for products’ name.
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2011-09-24
TC62D722CFG/CFNG
Block Diagram
OUT0
OUT1
▪▪▪▪▪▪▪▪▪▪
OUT15
16
Error detection result
data register
16
S0 (S1)
S1
S2
S3 (S1)
Output open/short detection circuit
VDD
POR
circuit
GND
Reference
voltage
Constant current output circuit
REXT
Output delay circuit
16
S4
S5 (S6)
0-bit
15-bit
Output ON/OFF setting data register
TSD
circuit
8-bit
DAC
8
Comparator
PWM
counter
Comparator
Comparator
PWMCLK
16
16
16
PWM data register
16-bit
PWM Data
for OUT0
6 ビット
16
TRANS
SIN
SCK
16-bit
PWM Data
for OUT15
16
16 Register 2
16
16-bit
16-bit
16-bit
▪▪▪▪▪▪▪▪▪▪▪▪▪
（for
synchronous）
PWM Data
PWM Data
PWM Data
16 for OUT0 16 for OUT1
16 for OUT15
POD
circuit
Command
control
circuit
Register 3
16-bit
▪▪▪▪▪▪▪▪▪▪▪▪▪
PWM Data （for output）
for OUT1
16
6 ビット
16
16-bit
PWM Data
for OUT0
16-bit
PWM Data
for OUT1
16
16
6 ビット
Register 1
▪▪▪▪▪▪▪▪▪▪▪▪▪
16-bit  2
State setting
register
16
16-bit
PWM Data
for OUT15
16
16
Data transfer control circuit
16
16
0-bit
15-bit
16-bit shift register
F/F
2
SOUT
selection
circuit
SOUT
2011-09-24
TC62D722CFG/CFNG
Pin Assignment (top view)
GND
VDD
SIN
REXT
SCK
SOUT
PWMCLK
TRANS
OUT0
OUT15
OUT1
OUT14
OUT2
OUT13
OUT3
OUT12
OUT4
OUT11
OUT5
OUT10
OUT6
OUT9
OUT7
OUT8
Pin Description
Pin No
Pin Name
I/O
Function
1
GND

2
SIN
I
The serial data input pin.
3
SCK
I
The serial data transfer clock input pin.
4
TRANS
I
The data transfer command input pin.
5
OUT0
O
The sink type constant current output pin.
6
OUT1
O
The sink type constant current output pin.
7
OUT2
O
The sink type constant current output pin.
8
OUT3
O
The sink type constant current output pin.
9
OUT 4
O
The sink type constant current output pin.
10
OUT5
O
The sink type constant current output pin.
11
OUT6
O
The sink type constant current output pin.
12
OUT7
O
The sink type constant current output pin.
13
OUT8
O
The sink type constant current output pin.
14
OUT9
O
The sink type constant current output pin.
15
OUT10
O
The sink type constant current output pin.
16
OUT11
O
The sink type constant current output pin.
17
OUT12
O
The sink type constant current output pin.
18
OUT13
O
The sink type constant current output pin.
19
OUT14
O
The sink type constant current output pin.
20
OUT15
O
The sink type constant current output pin.
21
PWMCLK
I
The reference clock input pin for PWM grayscale control.
One cycle of the input clock becomes a minimum pulse width of the PWM output.
22
SOUT
O
The serial data output pin.
23
REXT

The constant current value setting resistor connection pin.
24
VDD

The power supply input pin.
The ground pin.
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2011-09-24
TC62D722CFG/CFNG
Equivalent circuit of input and output
1. SCK, SIN
2. PWMCLK, TRANS
VDD
VDD
(SCK)
(SIN)
(PWMCLK)
(TRANS)
GND
GND
3. SOUT
VDD
SOUT
GND
4. OUT0
to
OUT15
OUT0 to OUT15
GND
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2011-09-24
TC62D722CFG/CFNG
1. Explanation of the function (Basic data input pattern)
Data input is done with the SIN pin and the SCK pin.Command selection is done with the SCK pin and the TRANS pin.
About the operation of each command
Command
Number of SCK pulses
at TRANS=”H” Note3,4
S0
0,1
The PWM data in the 16-bit shift register is transmitted to the PWM data register 1.
S1
2,3
1. The PWM data in the PWM data register 1 is transmitted to the PWM data register 2 or 3. Note1
2. The automatic output open/short detection result data is transmitted to the 16-bit shift register. Note2
3. PWM output start.
S2
7,8
Input of the output ON/OFF data. (When this function is not used, this input is unnecessary.)
S3
9,10
The manual output open/short detection functions are executed. Note2
The manual output open/short detection result data is transmitted to the 16-bit shift register. Note2
Operation
S4
11,12
Reset of the internal PWM counter.
S5
13,14
Input of the state setting data (1).
S6
15,16
Input of the state setting data (2).
Note1: Transmitted register changes by a PWM counter synchronization setting.
Note2: This operation is performed when the output open/short detection function is “Active” setting.
Note3: Other SCK numbers are disregarded.
Note4: If SCK is "L" when changing TRANS into "H", Please make SCL "L" when changing TRANS into "L"
If SCK is "H" when changing TRANS into "H", Please make SCL "H" when changing TRANS into "L"
S0 command (The PWM data is transmitted to the PWM data register 1.)
S1 command (The PWM data is transmitted to the PWM data register 2 or 3.)
S2 command (Input of the output ON/OFF data.)
S3 command (The output open/short detection functions manual operation is executed.)
S4 command (Reset of the internal PWM counter.)
S5 command (Input of the state setting data (1).)
S6 command (Input of the state setting data (2).)
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2011-09-24
TC62D722CFG/CFNG
2. About the operation of each command
2-1-1) S0 command (The PWM data is transmitted to the PWM data register 1.)
Operation) In the number of SCK pulses at TRANS="H" is 0 or 1, the following operation is executed.
The PWM data in the 16-bit shift register is transmitted to the PWM data register 1.
It is necessary to repeat this command 16 times to input the PWM data of OUT0 to OUT15 .
The order of the PWM data transfer is the following.
OUT15 → OUT14 → OUT13 → OUT12 → OUT11→ OUT10 → OUT9 → OUT8
→ OUT7 → OUT6 → OUT5 → OUT4 → OUT3 → OUT2 → OUT1→ OUT0
Basic input pattern of S0 command)
Repetition pattern
（The PWM data of OUT15 ~ OUT0 is input by repeating this pattern 16 times. ）
SCK
1
TRANS
SIN
SOUT
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
Previous Data
D1
D0
The period of TRANS="H" does not
receive the data input from SIN.
D15
D14 D13 D12
SOUT is operation at the time of S6 command N0=0 conditions.
Command execution
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2011-09-24
TC62D722CFG/CFNG
2-1-2) Input form of the PWM data
PWM resolution is set by the S5 command. Default setting is “16-bit”.
1. 16-bit PWM setting
MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
･･･
･･･
･･･
･･･
･･･
･･･
･･･
PWM setting
(reference)
0/65535(Default)
1/65535
2/65535
･･･
D0
･･･
D1
･･･
D2
･･･
D3
･･･
D4
･･･
D5
･･･
D6
･･･
D7
･･･
D8
･･･
D15 D14 D13 D12 D11 D10 D9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D15 to D0 is serial-data-inputted at MSB first.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
65533/65535
65534/65535
65535/65535
2. 14-bit PWM setting
MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
･･･
･･･
･･･
･･･
･･･
PWM setting
(reference)
0/16383(Default)
1/16383
2/16383
･･･
D0
･･･
D1
･･･
D2
･･･
D3
･･･
D4
･･･
D5
･･･
D6
･･･
D7
･･･
D8
･･･
D15 D14 D13 D12 D11 D10 D9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D15 to D0 is serial-data-inputted at MSB first.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
16381/16383
16382/16383
16383/16383
Don’t care
3. 12-bit PWM setting
MSB
LSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
･･･
･･･
･･･
PWM setting
(reference)
0/4095(Default)
1/4095
2/4095
･･･
D0
･･･
D1
･･･
D2
･･･
D3
･･･
D4
･･･
D5
･･･
D6
･･･
D7
･･･
D8
･･･
D15 D14 D13 D12 D11 D10 D9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D15 to D0 is serial-data-inputted at MSB first.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
4093/4095
4094/4095
4095/4095
Don’t care
4. 10-bit PWM setting
LSB
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
･･･
･･･
･･･
･･･
･･･
･･･
･･･
･･･
･･･
･･･
D15 D14 D13 D12 D11 D10 D9
PWM setting
(reference)
0/1023(Default)
1/1023
2/1023
D8
･･･
MSB
1
1
1
1
1
1
1
1
1
D15 to D0 is serial-data-inputted at MSB first.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1021/1023
1022/1023
1023/1023
Don’t care
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2011-09-24
TC62D722CFG/CFNG
2-2-1) S1 command (The PWM data is transmitted to the PWM data register 2 or 3.)
Operation) In the number of SCK pulses at TRANS="H" is 2 or3, the following operation is executed.
1. The PWM data in the PWM data register 1 is transmitted to the PWM data register 2 or 3.
2. The automatic output open/short detection result data is transmitted to the 16-bit shift
register. Note1
When internal PWM count is 1 to 21, the output open/short detection automatic operation is
done. During detection, the detection current flows to the OUT0 ~ OUT15 terminal. The
detection current is about 4A.
3. The PWM output start.
In the input of this command, the PWM output is turned on once.
When restarting by same PWM data, please input this command again.
About the output operation when this command is input while PWM output.
1. When the PWM counter is the synchronous mode. Note2
After the present PWM output has ended, PWM output is started by new PWM data.
2. When the PWM counter is the asynchronous mode. Note2
The present PWM output is canceled and a PWM output is immediately started by new PWM
data.
Basic input pattern of S1 command)
The first SCK (signal X) after S1 command is used for transmission of the output open/short
detection result data. The input from SIN is not received. Note1
When internal PWM count is 1 to 21, the output open/short detection automatic operation is done.
The detection current flows to the OUT0 ~ OUT15 terminal. The detection current is about 4A. Note1
Note1: This operation is performed when the output open/short detection function is “Active” setting.
The output open/short detection functions are set by S6 command.
Default setting is “Not Active”.
Note2: PWM output synchronization PWM resolution is set by the S6 command.
Default setting is “Synchronous mode”.
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2011-09-24
TC62D722CFG/CFNG
2-2-2) Output form of the output open/short detection result data
It is transmitted to 16 bit-shift register in the following form.
MSB
LSB
E15
E14
E13
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
E0
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
E15 to E0 is serial-data-outputted at MSB first.
Error code (when output open detection function is effective)
The state of output
Error code
VOOD  VOUT
0
VOOD < VOUT
1
Error code (when output short detection function is effective)
The state of output
Error code
VOSD1/2  VOUT
0
VOSD1/2 > VOUT
1
Condition of output
Open
Normal
Condition of output
short-circuit
Normal
Error code (when output open/short detection function is effective)
The state of output
Error code
Condition of output
VOOD  VOUT or VOSD1/2  VOUT
0
Open or short-circuit
VOOD < VOUT or VOSD1/2 > VOUT
1
Normal
When both output error detection function is effective, Open and short-circuit are undistinguishable.
When internal PWM count is 1 to 21, the output open/short detection automatic operation is done.
When the output is off during the output open/short detection execution, the error code becomes "1".
Setting of
Setting of
The PWM step that becomes error code "1"
PWM output mode
PWM bits number
without relations in the state of the output pin.
16 bit PWM setting
Normal
14 bit PWM setting
0 to 20 PWM stepsetting
PWM output mode
12 bit PWM setting
10 bit PWM setting
16 bit PWM setting
14 bit PWM setting
0 to 2560 PWM stepsetting
Division
12 bit PWM setting
PWM output mode
10 bit PWM setting
0 to 960 PWM stepsetting
The above table is unrelated at the time of the output open/short detection manual operation by S3
command.
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2011-09-24
TC62D722CFG/CFNG
2-3-1) S2 command (Input of the output ON/OFF data.)
When this function is not used, this input is unnecessary.
Operation) In the number of SCK pulses at TRANS="H" is 7 or 8, the following operation is executed.
Input of the output ON/OFF data.
Even if PWM data is not changed to 0 settings, ON/OFF of the output can be controlled.
About the output operation when this command is input while PWM output.
1. When the PWM counter is the synchronous mode. Note1
The setting of this command is reflected in the next PWM output.
2. When the PWM counter is the asynchronous mode. Note1
The setting of this command is reflected immediately.
Basic input pattern of S2 command)
Note1: PWM output synchronization PWM resolution is set by the S6 command.
Default setting is “Synchronous mode”.
2-3-2) Input form of the output ON/OFF data
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
D15 to D0 is serial-data-inputted at MSB first.
The output ON/OFF data setting
Input Data
Setting
1
0
Output operates according to PWM data setting. (Default)
Output turn off
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2011-09-24
TC62D722CFG/CFNG
2-4) S3 command (The manual output open/short detection functions are executed.)
Operation) In the number of SCK pulses at TRANS="H" is 9 or 10, the following operation is executed.
The manual output open/short detection functions are executed. Note1
The output is compulsorily turned on during tON(S3) with about 60μA. And detection is done.
The manual output open/short detection result data is transmitted to the 16-bit shift register.
tON(S3) is about 800ns.
For the period of tON(S3), please set SCK and TRANS to “L”.
When inputting this command during PWM output, the manual output open/short detection
functions are executed after the PWM output. In this case, tON(S3) occurs after a PWM output.
Basic input pattern of S3 command)
The first SCK (signal X) after this command is used for transmission of the output open/short
detection result data. The input from SIN is not received. Note1
Note1: This operation is performed when the output open/short detection function is “Active” setting.
The output open/short detection functions are set by S6 command.
Default setting is “Not Active”.
2-5) S4 command (Reset of the internal PWM counter.)
Operation) In the number of SCK pulses at TRANS="H" is 11 or 12, the following operation is executed.
The internal PWM counter is reset.
When the internal PWM counter is reset, the output is turned off.
It is necessary to input S1 command to turn on the output again.
Basic input pattern of S4 command)
n 0 0 0 0
PWMCLK
SCK
１
2
11
12
TRANS
ON
SOUT
OFF
Command execution
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2011-09-24
TC62D722CFG/CFNG
2-6-1) S5 command (Input of the state setting data (1).)
Operation) In the number of SCK pulses at TRANS="H" is 13 or 14, the following operation is executed.
The state setting data (1) in the 16-bit shift register is transmitted to the state setting register.
Basic input pattern of S5 command)
2-6-2) Input form of the state setting data (1)
MSB
D15 D14 D13 D12 D11 D10 D9
D8
A7
A6
A5
A4
A3
A2
A1
A0
D15 to D0 is serial-data-inputted at MSB first.
Please input "L" data to D7 to D4.
D7
-
D6
-
D5
-
D4
-
D3
B1
D2
B0
D1
H0
LSB
D0
L0
The state setting data (1) setting
Setting bit
A7
A6 to A0
B1 to B0
H0
L0
Outline of command
Setting of
output gain control range
Setting of
output gain control data
Setting of
PWM resolution
Setting of
Initialization function
Setting of
standby mode (1) function
Input data
0
1
High setting mode
Low setting mode
47.5% to 202.7%
8.46% to 43.96%
(Default)
47.5% to
202.7%
Please refer to 1314 page.
100.0%
Please refer to 15 page.
16-bit
Not Active
Active
Not Active
Not Active
Active
Not Active
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TC62D722CFG/CFNG
2-6-3) Details of each setting
A setting (setting of output gain control data reference value)
1. In the case of the high setting mode (47.5% to 202.7%)
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Current
gain(%)
202.7
201.5
200.3
199.1
197.8
196.6
195.4
194.2
193.0
191.7
190.5
189.3
188.1
186.8
185.6
184.4
183.2
181.9
180.7
179.5
1
1
0
1
0
1
1
178.3
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
177.1
175.8
174.6
173.4
172.2
170.9
169.7
168.5
167.3
166.1
164.8
163.6
162.4
161.2
159.9
158.7
157.5
156.3
155.1
153.8
152.6
151.4
150.2
148.9
147.7
146.5
145.3
144.1
142.8
141.6
140.4
139.2
137.9
136.7
135.5
134.3
133.1
131.8
130.6
129.4
128.2
126.9
125.7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
13
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Current
gain(%)
124.5
123.3
122.0
120.8
119.6
118.4
117.2
115.9
114.7
113.5
112.3
111.0
109.8
108.6
107.4
106.2
104.9
103.7
102.5
101.3
100.0
(Default)
98.8
97.6
96.4
95.2
93.9
92.7
91.5
90.3
89.0
87.8
86.6
85.4
84.2
82.9
81.7
80.5
79.3
78.0
76.8
75.6
74.4
73.2
71.9
70.7
69.5
68.3
67.0
65.8
64.6
63.4
62.1
60.9
59.7
58.5
57.3
56.0
54.8
53.6
52.4
51.1
49.9
48.7
47.5
2011-09-24
TC62D722CFG/CFNG
2. In the case of the low setting mode (8.46% to 43.96%)
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Current
gain(%)
43.96
43.68
43.40
43.12
42.84
42.56
42.28
42.00
41.72
41.44
41.16
40.89
40.61
40.33
40.05
39.77
39.49
39.21
38.93
38.65
38.37
38.09
37.81
37.53
37.25
36.97
36.69
36.41
36.13
35.85
35.57
35.29
35.02
34.74
34.46
34.18
33.90
33.62
33.34
33.06
32.78
32.50
32.22
31.94
31.66
31.38
31.10
30.82
30.54
30.26
29.98
29.70
29.42
29.15
28.87
28.59
28.31
28.03
27.75
27.47
27.19
26.91
26.63
26.35
14
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Current
gain(%)
26.07
25.79
25.51
25.23
24.95
24.67
24.39
24.11
23.83
23.55
23.27
23.00
22.72
22.44
22.16
21.88
21.60
21.32
21.04
20.76
20.48
20.20
19.92
19.64
19.36
19.08
18.80
18.52
18.24
17.96
17.68
17.40
17.13
16.85
16.57
16.29
16.01
15.73
15.45
15.17
14.89
14.61
14.33
14.05
13.77
13.49
13.21
12.93
12.65
12.37
12.09
11.81
11.53
11.26
10.98
10.70
10.42
10.14
9.86
9.58
9.30
9.02
8.74
8.46
2011-09-24
TC62D722CFG/CFNG
B setting (Setting of PWM resolution)
B[1]
0
0
1
1
B[0]
0
1
0
1
Setting
16-bit (65536 steps) setting. (Default)
14-bit (16384 steps) setting.
12-bit (4096 steps) setting.
10-bit (1024 steps) setting.
H setting (Setting of Initialization function）
H[0]
0
1
Setting
The initialization function becomes not active (Default)
It's normal operation mode.
The initialization function becomes active.
All data in IC is initialized.
After data initialization, it becomes normal operation mode.
L setting (Setting of standby mode (1) function)
L[0]
0
1
Setting
The standby mode (1) function becomes not active. (Default)
It's normal operation mode.
The standby mode (1) function becomes active.
The circuits other than the logic circuit are turned off. And power supply current is
reduced.
(All the data of the IC are stored. Data input is possible.)
When S0 command is inputted at the standby mode (1), IC returns to normal operation
mode.
Return time to the normal operation mode is about 30 μs.
15
2011-09-24
TC62D722CFG/CFNG
2-7-1) S6 command (Input of the state setting data (2).)
Operation) In the number of SCK pulses at TRANS="H" is 15 or 16, the following operation is executed.
The state setting data (2) in the 16-bit shift register is transmitted to the state setting register.
Basic input pattern of S6 command)
2-7-2) Input form of the state setting data (2)
MSB
D15 D14 D13 D12 D11 D10 D9
D8
C0
D0
E0
F0
G0
I0
J0
K0
D15 to D0 is serial-data-inputted at MSB first.
Please input "L" data to D5 to D0.
D7
M0
D6
N0
D5
-
D4
-
D3
-
D2
-
D1
-
LSB
D0
-
The state setting data (2) setting
Setting
bit
C0
D0
E0
F0
G0
I0
J0
K0
M0
N0
Input data
Outline of command
Setting of
thermal shutdown function (TSD)
Setting of
PWMCLK open detection function (POD)
Setting of
output open detection function (OOD)
Setting of
output short detection function (OSD)
Setting of
PWM output synchronization
Setting of
PWM output system
Setting of
standby mode (2) function
This function becomes active only at the
time of the 16-bit PWM setting.
Setting of
output short detection voltage
Setting of
output delay function
Setting of
SCK trigger of SOUT
16
(Default)
0
1
Active
Not Active
Active
Active
Not Active
Active
Not Active
Active
Not Active
Not Active
Active
Not Active
Synchronous
Asynchronous
Synchronous
Normal
output
Division
output
Normal
output
Not Active
Active
Not Active
VOSD1
VOSD2
VOSD1
Active
Not Active
Active
Up edge
trigger mode
Down edge
trigger mode
Up edge
trigger mode
2011-09-24
TC62D722CFG/CFNG
2-7-3) Details of each setting
C setting (Setting of thermal shutdown function (TSD))
C[0]
0
1
Setting
Thermal shutdown function becomes active. (Default)
Thermal shutdown function becomes not active.
D setting (Setting of PWMCLK open detection function (POD))
D[0]
0
1
Setting
PWMCLK open detection function becomes active. (Default)
When it was the state that a PWMCLK signal isn't input by breaking of wiring,
it's the function which prevents PWM output keeping stopping by on state.
When PWMCLK is not inputted for about 1 second after it is inputted even once,
all output is turned off compulsorily.
Output compulsion off is released by the initialization function of S5 command.
In addition, the output compulsion off is removed by inputting PWMCLK again.
PWMCLK open detection function becomes not active.
E setting (Setting of output open detection function (OOD))
E[0]
0
1
Setting
Output open detection function becomes not active. (Default)
Output open detection function becomes active.
F setting (Setting of output short detection function (OSD))
F[0]
0
1
Setting
Output short detection function becomes not active. (Default)
Output short detection function becomes active.
G setting (Setting of PWM output synchronization)
G[0]
0
1
Setting
PWM output synchronous mode. (Default)
PWM output asynchronous mode.
I setting (Setting of PWM output system)
I[0]
0
1
Setting
Normal PWM output mode. (Default)
Division PWM output mode.
17
2011-09-24
TC62D722CFG/CFNG
J setting (Setting of standby mode (2))
J[0]
0
1
Setting
The standby mode (2) function becomes not active. (Default)
It's normal operation mode.
The standby mode (2) function becomes active.
A state changes according to the data in a PWM data register.
Condition 1: All data in the PWM data register1 and the PWM data register3 are "L".
It becomes standby mode (2).
The circuits other than the logic circuit are turned off. And power supply
current is reduced.
(All the data of the IC are stored. Data input is possible.)
Condition 2: Excluding condition 1.
It becomes Pre standby mode.
It is the same operation as normal operation mode.
Return time from standby mode (2) to Pre standby mode is about 30 μs.
This function becomes active only at the time of the 16-bit PWM setting.
K setting (Setting of output short detection voltage)
K[0]
0
1
Setting
VOSD1 setting. (Default)
VOSD2 setting.
M setting (Setting of output delay function)
M[0]
0
1
Setting
Output delay function becomes active. (Default)
Output delay function becomes not active.
N setting (Setting of SCK trigger of SOUT)
N[0]
0
1
Setting
It becomes up edge trigger mode. (Default)
Data output trigger from SOUT, becomes up edge of SCK
It becomes down edge trigger mode.
Data output trigger from SOUT, becomes down edge of SCK
18
2011-09-24
TC62D722CFG/CFNG
3. Input of PWM setting data
3-1) Normal input mode (S0 command: 16 times)
It commands the PWM data input only.
The PWM data for OUT0 to OUT15 are transferred to the PWM data resister by repeating the PWM
data input to the 16-bit shift register and S0 command input 16 times.
Unless S1 command is input, the PWM data for OUT0 to OUT15 is not reflected on output.
Normal input mode) S0 command 16 times
3-2) Speed input mode (S0 command 15 times + S1 command once)
It commands PWM data input and reflecting the PWM data on output at the same time.
The PWM data for OUT0 to OUT15 are reflected in the output by inputting S1 command after
repeating the PWM data input to the 16-bit shift register and S0 command input 15 times.
Normal input mode should be used to input PWM data only.
Speed input mode) S0 command 15 times + S1 command once
19
2011-09-24
TC62D722CFG/CFNG
4. About operation of a PWM output
The PWM output is outputted once to one S1 command.
When doing PWM output once again, it's necessary to input S1 command.
When S1 command is inputted during a PWM output by PWM output asynchronous mode, the present
PWM output is canceled and a PWM output is immediately started by new PWM data.
When S1 command is inputted during a PWM output by PWM output synchronous mode, after the
present PWM output has ended, a PWM output is started by new PWM data.
If S1 command is inputted two or more times during a PWM output by PWM output synchronous mode,
after the present PWM output has ended, a PWM output will be started by the PWM data inputted at the
end.
20
2011-09-24
TC62D722CFG/CFNG
5. PWM Output
5-1) Normal PWM output mode.
Output waveform of 16-bit PWM.
TRANS
(S1command)
0
1
2
3
511 512 513 514
49,151 49,153 49,155
16,383 16,385 16,387
32,767 32,769 32,771
49,150 49,152 49,154
16,382 16,384 16,386
32,766 32,768 32,770
65,024 65,026
65,023 65,025
65,535
65,534 65,536
PWMCLK
ON
OUTn
PWMDATA=0000h
OFF
ON
OUTn
PWMDATA=0001h
OFF
ON
OUTn
PWMDATA=0002h
OFF
ON
OUTn
PWMDATA=0003h
OFF
ON
OUTn
PWMDATA=0201h
OFF
ON
OUTn
PWMDATA=4001h
OFF
ON
OUTn
PWMDATA=8001h
OFF
ON
OUTn
PWMDATA=C001h
OFF
ON
OUTn
PWMDATA=FE01h
OFF
ON
OUTn
PWMDATA=FFFFh
OFF
21
2011-09-24
TC62D722CFG/CFNG
5-2) Division PWM output mode.
PWM output period is divided into 128 pieces.
Because turn on time of output is not biased, it is effective in the flicker prevention on the display.
Output waveform of 16-bit PWM.
TRANS
(S1command)
0
1
2
3
511 512 513 514
49,151 49,153 49,155
16,383 16,385 16,387
32,767 32,769 32,771
49,150 49,152 49,154
16,382 16,384 16,386
32,766 32,768 32,770
65,024 65,026
65,023 65,025
65,535
65,534 65,536
PWMCLK
period1
period2~period32
period33~period64
period65~period96
period97~period127
period128
ON
OUTn
PWMDATA=0000h
OFF
ON
OUTn
PWMDATA=0001h
OFF
ON
OUTn
PWMDATA=0002h
OFF
ON
OUTn
PWMDATA=0003h
OFF
ON
OUTn
PWMDATA=0004h
OFF
ON
OUTn
PWMDATA=0080h
OFF
ON
OUTn
PWMDATA=0081h
OFF
ON
OUTn
PWMDATA=0081h
OFF
ON
OUTn
PWMDATA=FFC0h
OFF
ON
OUTn
PWMDATA=FFC1h
OFF
ON
OUTn
PWMDATA=FFC2h
OFF
ON
OUTn
PWMDATA=FFFDh
OFF
ON
OUTn
PWMDATA=FFFEh
OFF
ON
OUTn
PWMDATA=FFFFh
OFF
22
2011-09-24
TC62D722CFG/CFNG
6. Thermal shutdown circuit (TSD)
When the temperature of internal IC exceeds 150C, all constant current outputs are turned off by this
function. The constant current is outputted again when the temperature decreases to the rating.
The thermal shutdown function of this IC aims at stopping the influence (emitting smoke, ignition) on
the circumference (LED and substrate) to the minimum, when it is used on the conditions beyond not a
function but the maximum rating for preventing destruction of IC and IC results in destruction.
Calculation of heat
Take care not to let the temperature of the internal IC exceed 150℃ by referring to the formula below.
Consumption power (IC output) W = (LED supply voltage V - Minimum of Vf of LED V )
× Output current A × number of output × (ON Duty % / 100 )
Consumption power (IC supply) W = IC supply voltage V ×IC supply current A
Total of consumption power W = Consumption power (IC output) W + Consumption power (IC supply) W
Heat value of internal IC C = Thermal Resistance C / W × total of power consumption W
Temperature of internal IC C = Heat value of internal IC C + Ambient temperature C
In case used LED supply voltage is high, and heat value of internal IC is large.
Heat value of internal IC can be reduced by decreasing the voltage with the external resistance shown below.
Controller
SCK
SIN
VDD
TRANS
PWMCLK
OUT0
OUT7
OUT15
SOUT
Resistance for heat protection
VDD
GND
VLED
REXT
Setting method of resistance for heat protection
Voltage that should decrease by external resistance V
= LED supply voltage V - maximum of Vf of LED V - Output voltage V
Resistance for heat protection  = Voltage that should decrease by external resistance V / Output current A
7. Output delay function
This function is intended to have the effect of reducing switching noise by reducing the di/dt when all
outputs are ON or OFF at the same time.There is a switching timelag between outputs.
A switching timelag between outputs is put in order of the following.
OUT0 → OUT15 → OUT7 → OUT8 → OUT1 → OUT14 → OUT6 → OUT9 → OUT2 → OUT13 →
OUT5 → OUT10 → OUT3 → OUT12 → OUT 4 → OUT11
23
2011-09-24
TC62D722CFG/CFNG
8. Power on reset (POR)
It avoids the malfunction by resetting all internal data of IC and setting default in startup.
POR circuit operates only when VDD rises from 0 V. To restart POR, VDD should be 0.1 V or less.
As for the voltage of storing the internal data, it is guaranteed after VDD reaches 3.0 V or more once.
VDD waveform
VDD=3.0V
VDD voltage for guaranteed data
VDD=2.8 V
VDD voltage for end of reset
VDD=0.1 V
End of POR
VDD=0 V
POR working range
Beyond POR working range
24
POR working range
2011-09-24
TC62D722CFG/CFNG
Application circuit (Dynamic lighting)
VDD
OUT0
OUT7
OUT15
REXT
GND
SCK
SIN
TRANS
PWMCLK
VDD
SOUT
OUT0
OUT7
OUT15
REXT
SCK
SIN
TRANS
GND
VDD
SOUT
OUT0
OUT7
PWMCLK
OUT15
GND
SOUT
25
VDD
REXT
VLED
Controller
SCK
SIN
TRANS
PWMCLK
2011-09-24
TC62D722CFG/CFNG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating Note1
Unit
S u p p l y
v o l t a g e
VDD
0.3 to 6.0
V
O u t p u t
c u r r e n t
IOUT
95
mA
VIN
0.3 to VDD  0.3 Note2
V
Logic
input
voltage
O u t p u t
v o l t a g e
VOUT
0.3 to 17
V
Operating
temperature
Topr
40 to 85
°C
temperature
Tstg
Storage
T hermal
P o w e r
resistance
d i s s i p a t i o n
Rth(j-a)
PD
55 to 150
CFG
CFNG
°C
CFG
94 Note3
45.47 Note4
1.32 Note5
CFNG
2.74 Note5
°C/W
W
Note1: Voltage is ground referenced.
Note2: 6V must not be exceeded.
Note3: PCB condition is 76.2 mm×114.3 mm×1.6 mm Cu=30% (SEMI Conforming)
Note4: PCB condition is JEDEC 2s2p
Note5: When ambient temperature is 25°C or more. Every time ambient temperature exceeded 1°C, please decrease 1/Rth(j-a).
Operating Condition
DC Characteristics (Unless otherwise noted, VDD = 3.0 V to 5.5 V, Ta = -40 to 85 °C)
Characteristics
Symbol
Test Conditions
Min
Typ.
Max
Unit
v o l t a g e
VDD

3.0

5.5
V
High level logic input voltage
VIH
Test terminal is
SIN, SCK, TRANS, PWMCLK
0.7VDD

VDD
V
Low level logic input voltage
VIL
Test terminal is
SIN, SCK, TRANS, PWMCLK
GND

0.3VDD
V
High level SOUT output current
IOH



1
mA
Low level SOUT output current
IOL



1
mA
Constant current output
IOUT
Test terminal is OUTn
1.5

90
mA
S u p p l y
26
2011-09-24
TC62D722CFG/CFNG
AC Characteristics 1 (Unless otherwise noted, VDD = 5.0 V, Ta = 25 °C)
Characteristics
Symbol
Serial data transfer frequency
fSCK
Test Conditions
Min
Typ.
Max


30
Down edge trigger mode


25
Up edge trigger mode
Cascade connect
Unit
MHz
w i d t h
twSCK
SCK=“H” or “L”
15
20

ns
PWMCLK pulse width
twPWM
PWM=“H” or “L” , REXT =200 Ω to 12 kΩ
15
20

ns
twTRANS
TRANS=“H”
20


ns
tSETUP1
SIN-SCK
1


tSETUP2
TRANS-SCK
5


tSETUP3
TRANS-SCK
5


tSETUP4
TRANS-SCK
2


tSETUP5
ＴRANS-PWMCLK
5


tHOLD1
SIN-SCK
3


tHOLD2
TRANS-SCK
7


tHOLD3
TRANS-SCK
7


tHOLD4
TRANS-SCK
2


tHOLD5
TRANS-PWMCLK
5


Min
Typ.
Max


30
Down edge trigger mode


25
S C K
p u l s e
TRANS
pulse
width
Serial data setup time
Serial data hold time
ns
ns
AC Characteristics 2 (Unless otherwise noted, VDD = 3.3 V, Ta = 25 °C)
Characteristics
Symbol
Serial data transfer frequency
fSCK
S C K
wi dt h
twSCK
SCK=“H” or “L”
15
20

ns
PWMCLK pulse width
twPWM
PWM=“H” or “L” , REXT =200 Ω to 12 kΩ
15
20

ns
twTRANS
TRANS=“H”
20


ns
tSETUP1
SIN-SCK
1


tSETUP2
TRANS-SCK
5


tSETUP3
TRANS-SCK
5


tSETUP4
TRANS-SCK
2


tSETUP5
ＴRANS-PWMCLK
5


tHOLD1
SIN-SCK
3


tHOLD2
TRANS-SCK
7


tHOLD3
TRANS-SCK
7


tHOLD4
TRANS-SCK
2


tHOLD5
TRANS-PWMCLK
5


p u l s e
TRANS
pulse
width
Serial data setup time
Serial data hold time
Test Conditions
Up edge trigger mode
27
Cascade connect
Unit
MHz
ns
ns
2011-09-24
TC62D722CFG/CFNG
Electrical Characteristics
Electrical Characteristics 1 (Unless otherwise noted, VDD = 5.0 V, Ta = 25 °C)
Characteristics
Symbol
Test
Circuit
H i g h
l e v e l
SOUT output voltage
VOH
1
L o w
l e v e l
SOUT output voltage
VOL
1
High level logic input current
IIH
2
Low level logic input current
IIL
Min
Typ.
Max
Unit
IOH=1mA
VDD 
0.3

VDD
V
IOL=1mA
GND

0.3
V
VIN = VDD
Test terminal is SIN, SCK


1
A
3
VIN = GND
Test terminal is
PWMCLK, SIN, SCK, TRANS


-1
A
IDD1
4
Stand-by mode (1) or (2)
VOUT=17V, SCK=“L”


1.0
μA
IDD2
4


7.0
mA
IOUT(IC)
5

1.0
1.5
%
Constant current error(Ch to Ch)
IOUT(Ch)
（S rank）
5

1.0
1.5
%
Constant current error(IC to IC)
（N rank）
IOUT(IC)
5

1.0
2.5
%
Constant current error(Ch to Ch)
IOUT(Ch)
（N rank）
5
VOUT=1.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on

1.0
2.5
%
Output OFF leak current
IOK
5
VOUT=17V, REXT=1.2k,
OUTn off


0.5
A
Constant current output
power supply voltage regulation
%VDD
5
VDD=4.5 to 5.5V, VOUT=1.0V
REXT=1.2k
OUT0 to OUT15 , 1ch output on

1
5
%/V
Constant current output
output voltage regulation
%VOUT
5
VOUT=1.0 to 3.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on

0.1
0.5
%/V
Pull-down
RDOWN
2
Test terminal is TRANS, PWMCLK
250
500
750
k
VOOD
6
REXT=200Ω to 12kΩ
0.2
0.3
0.4
V
VOSD1
6
REXT=200Ω to 12kΩ
VDD 
1.3
VDD 
1.4
VDD 
1.5
6
REXT=200Ω to 12kΩ
0.5 
VDD
T S D s t a r t t e m p e r a t u r e TTDS(ON)

Junction temperature
150


C
TSD release temperature TTSD(OFF)

Junction temperature
100


C
Ta=-40 to +85C
Power supply current
Constant current error(IC to IC)
（S rank）
O O D
O S D
resistor
v o l t a g e
Test Conditions
VOUT=1.0V, REXT=1.2k
All output off
VOUT=1.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on
VOUT=1.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on
VOUT=1.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on
v o l t a g e
VOSD2
28
0.525  0.55 
VDD
VDD
V
2011-09-24
TC62D722CFG/CFNG
Electrical Characteristics 2 (Unless otherwise noted, VDD = 3.3 V, Ta = 25 °C)
Characteristics
Symbol
Test
Circuit
H i g h
l e v e l
SOUT output voltage
VOH
1
L o w
l e v e l
SOUT output voltage
VOL
1
High level logic input current
IIH
2
Low level logic input current
IIL
Test Conditions
Min
Typ.
Max
Unit
IOH=1mA
VDD 
0.3

VDD
V
IOL=1mA
GND

0.3
V
VIN = VDD
Test terminal is SIN, SCK


1
A
3
VIN = GND
Test terminal is
PWMCLK, SIN, SCK, TRANS


-1
A
IDD1
4
Stand-by mode (1) or (2)
VOUT=17V, SCK=“L””


1.0
μA
IDD2
4
VOUT=1.0V, REXT=1.2k
All output off


7.0
mA

1.0
1.5
%

1.0
1.5
%

1.0
2.5
%
Ta=-40 to +85C
Power supply current
VOUT=1.0V, REXT=1.2k
Constant current error(IC to IC)
IOUT(IC)
（S rank）
5
Constant current error(Ch to Ch)
IOUT(Ch)
（S rank）
5
Constant current error(IC to IC)
IOUT(IC)
（N rank）
5
Constant current error(Ch to Ch)
IOUT(Ch)
（N rank）
5
VOUT=1.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on

1.0
2.5
%
Output OFF leak current
5
VOUT=17V, REXT=1.2k, OUTn off


0.5
A

1
5
%/V
IOK
OUT0 to OUT15 , 1ch output on
VOUT=1.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on
VOUT=1.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on
Constant current output
power supply voltage regulation
%VDD
5
VDD=3.0 to 3.6V, VOUT=1.0V
REXT=1.2k
OUT0 to OUT15 , 1ch output on
Constant current output
output voltage regulation
%VOUT
5
VOUT=1.0 to 3.0V, REXT=1.2k
OUT0 to OUT15 , 1ch output on

0.1
0.5
%/V
r e s i s t o r RDOWN
2
Test terminal is TRANS, PWMCLK
250
500
750
k
VOOD
6
REXT=200Ω to 12kΩ
0.2
0.3
0.4
V
VOSD1
6
REXT=200Ω to 12kΩ
VDD 
1.3
VDD 
1.4
VDD 
1.5
6
REXT=200Ω to 12kΩ
0.5 
VDD
T S D s t a r t t e m p e r a t u r e TTDS(ON)

Junction temperature
150


C
TSD release temperature TTSD(OFF)

Junction temperature
100


C
Pull-down
O O D
O S D
v o l t a g e
v o l t a g e
VOSD2
29
0.525  0.55 
VDD
VDD
V
2011-09-24
TC62D722CFG/CFNG
Switching Characteristics
Switching Characteristics 1 (Unless otherwise specified, VDD = 5.0 V, Ta = 25 °C)
Symbol
Test
Circuit
SCK↑-SOUT
tPD1U
7
Up edge trigger mode
6
16
30
SCK↓-SOUT
tPD1D
7
Down edge trigger mode
2
10
14
PWMCLK- OUT0
tPD2
7
REXT=1.2k

30
40
Constant current output
r i s e
t i m e
tor
7
10  90% at voltage waveform of OUTn
REXT=1.2k

10
20
ns
Constant current output
f a l l
t i m e
tof
7
90  10% at voltage waveform of OUTn
REXT=1.2k

10
20
ns
7
REXT=1.2k
1
4
9
ns
7
REXT=1.2k
1
4
9
ns
Characteristics
Propagation
d e l a y
C o n s t a n t c u r r e n t o u t p u t tDLY(ON)
d e l a y
t i m e tDLY(OFF)
Test Conditions
Min Typ. Max Unit
ns
Switching Characteristics 2 (Unless otherwise specified, VDD = 3.3 V, Ta = 25 °C)
Symbol
Test
Circuit
SCK↑-SOUT
tPD1U
7
Up edge trigger mode
6
16
30
SCK↓-SOUT
tPD1D
7
Down edge trigger mode
2
13
18
PWMCLK- OUT0
tPD2
7
REXT=1.2k

30
40
Constant current output
r i s e
t i m e
tor
7
10 to 90% at voltage waveform of OUTn
REXT=1.2k

10
20
ns
Constant current output
f a l l
t i m e
tof
7
90 to 10% at voltage waveform of OUTn
REXT=1.2k

10
20
ns
7
REXT=1.2k
2
6
12
ns
7
REXT=1.2k
2
6
12
ns
Characteristics
Propagation
d e l a y
C o n s t a n t c u r r e n t o u t p u t tDLY(ON)
d e l a y
t i m e tDLY(OFF)
Test Conditions
30
Min Typ. Max Unit
ns
2011-09-24
TC62D722CFG/CFNG
Test circuit
Test circuit 1 : High level SOUT output voltage / Low level SOUT output voltage
SCK
SIN
Controller
VDD
OUT0
TRANS
PWMCLK
OUT7
OUT15
SOUT
CL  10.5 pF
V
VDD  3.3 V, 5.0 V
GND
IO = -1mA to 1mA
REXT
Test circuit 2 : High level logic input current / Pull-down resistance
VIH = VDD
A
A
A
SCK
SIN
VDD
OUT0
TRANS
PWMCLK
A
OUT7
OUT15
GND
SOUT
VDD  3.3 V, 5.0 V
REXT
Test circuit 3 : Low level logic input current
A
A
A
A
SCK
SIN
VDD
OUT0
TRANS
PWMCLK
OUT7
OUT15
REXT
GND
SOUT
VDD  3.3 V, 5.0 V
VIL = GND
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Test circuit 4 : Power supply current
Controller
SCK
SIN
VDD
OUT0
TRANS
PWMCLK
OUT7
OUT15
A
VDD  3.3 V, 5.0 V
SOUT
VOUT  1 V, 17 V
GND
REXT  1.2k
REXT
VDD
TRANS
PWMCLK
GND
OUT0
A
OUT7
A
OUT15
A
SOUT
VOUT  1 to 3 V, 17 V
REXT
REXT  1.2k
Controller
SCK
SIN
32
VDD  3.0 to 3.3 V, 4.5 to 5.5 V
Test circuit 5 : Constant current error / Output OFF leak current
Constant current output power supply voltage regulation
Constant current output output voltage regulation
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TC62D722CFG/CFNG
Test Circuit 6 : OOD voltage / OSD voltage
Controller
SCK
SIN
VDD
OUT0
V
TRANS
PWMCLK
OUT7
V
OUT15
V
VOUT1  1.0 V
VDD  3.3 V, 5.0 V
SOUT
VOUT2
GND
REXT  200, 12k
REXT
All output is set to turning on. Only one output is connected with the VOUT2 power supply, and other outputs
are connected with the VOUT1 power supply. VOUT2 is changed and OOD voltage / OSD voltage is checked in
the error detection result from each output terminal voltage and SOUT.
Test Circuit 7 : Switching Characteristics
OUT0
OUT7
OUT15
GND
SOUT
CL  10.5 pF
RL  200
CL  10.5 pF
REXT
REXT  1.2k
VIH  VDD
VIL  GND
tr  tf  10 ns
(10 to 90%)
33
RL
CL
RL
CL
RL
CL
VDD  3.3 V, 5.0 V
VDD
VLED  5.0V
Controller
SCK
SIN
TRANS
PWMCLK
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TC62D722CFG/CFNG
Timing waveform
1. SCK, TRANS, SIN, SOUT, PWMCLK
If SCK is "L" when changing TRANS into "H", Please make SCL "L" when changing TRANS into "L"
If SCK is "H" when changing TRANS into "H", Please make SCL "H" when changing TRANS into "L"
2. OUTn
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3.PWMCLK, OUT0 to OUT15
PWMCLK
OUT0
twPWM
twPWM
tDLY(ON)
tPD2
OFF
tPD2
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT15
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT7
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT8
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT1
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT14
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT6
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT9
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT2
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT13
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT5
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT10
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT3
ON
OFF
tDLY(ON)
tDLY(OFF)
OUT12
tDLY(ON)
OUT4
ON
OFF
tDLY(OFF)
ON
OFF
tDLY(OFF)
OUT11
ON
OUTn is a voltage waveform.
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TC62D722CFG/CFNG
Reference data
This data is provided for reference only. So, in designing for mass production, take enough care in
evaluating IC operation.
Output Current (IOUT) – Constant current output setting resistance (REXT)
The output gain control data is default.
IOUT - REXT
90
80
Theoretical formula
IOUT (A) = (1.03(V)  REXT ())  16.5
70
IOUT (mA)
60
50
40
30
20
10
0
VDD=3.0V to 5.5V
VOUT=1.0V
Ta=25°C
0
1000
2000
3000
4000
5000
REXT (Ω)
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TC62D722CFG/CFNG
Reference data
This data is provided for reference only. So, in designing for mass production, take enough care in
evaluating IC operation.
Output current (IOUT) – Output voltage (VOUT)
IOUT - VOUT
VDD =3.3V,Ta=25℃,1chON
100
90
80
IOUT (mA)
70
60
50
40
30
20
10
0
0
0.5
1
1.5
VOUT (V)
2
2.5
3
2
2.5
3
IOUT - VOUT
VDD=5.0V,Ta=25℃,1chON
100
90
80
IOUT (mA)
70
60
50
40
30
20
10
0
0
0.5
1
1.5
VOUT (V)
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TC62D722CFG/CFNG
Notes on design of ICs
1. Regarding decoupling capacitor between power supply and GND
It is recommended that decoupling capacitor between power supply and GND should place as near IC as possible.
2. Regarding resistors for setting of output current
When resistors for setting of output current (REXT) are used commonly by many ICs, in designing for mass production, take enough
care in evaluating IC operation.
3. Regarding PCB layout
There is only one GND terminal on this device when the inductance in the GND line and the resistor are large, the device may
malfunction due to the GND noise when output switching by the circuit board pattern and wiring.
Therefore, take care when designing the circuit board pattern layout and the wiring from the controller.
4. Please check the latest technical material at the time of mass production.
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Package dimension
TC62D722FG: SSOP24-P-300-1.00B
Unit : mm
Weight : 0.32 g (Typ.)
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TC62D722FNG: HTSSOP24-P-300-0.65
Unit : mm
Weight : 0.10 g (Typ.)
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Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Application Circuits
The application circuits shown in this document are provided for reference purposes only. Thorough
evaluation is required, especially at the mass production design stage.
Toshiba does not grant any license to any industrial property rights by providing these examples of
application circuits.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
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TC62D722CFG/CFNG
IC Usage Considerations
Notes on handling of ICs
[1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded,
even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury
by explosion or combustion.
[2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of
over current and/or IC failure. The IC will fully break down when used under conditions that exceed its
absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs
from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or
ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings,
such as fuse capacity, fusing time and insertion circuit location, are required.
[3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current resulting from the inrush
current at power ON or the negative current resulting from the back electromotive force at power OFF. IC
breakdown may cause injury, smoke or ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the
protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or
ignition.
[4] Do not insert devices in the wrong orientation or incorrectly.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding
the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by
explosion or combustion.
In addition, do not use any device that is applied the current with inserting in the wrong orientation or
incorrectly even just one time.
[5] Carefully select external components (such as inputs and negative feedback capacitors) and load
components (such as speakers), for example, power amp and regulator.
If there is a large amount of leakage current such as input or negative feedback condenser, the IC output
DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage,
overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from
the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC
that inputs output DC voltage to a speaker directly.
Points to remember on handling of ICs
(1) Heat Radiation Design
In using an IC with large current flow such as power amp, regulator or driver, please design the device so
that heat is appropriately radiated, not to exceed the specified junction temperature (TJ) at any time and
condition. These ICs generate heat even during normal use. An inadequate IC heat radiation design can
lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design
the device taking into considerate the effect of IC heat radiation with peripheral components.
(2) Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the
motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is
small, the device’s motor power supply and output pins might be exposed to conditions beyond
maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in system design.
(3) Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal shutdown
circuits operate against the over temperature, clear the heat generation status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings
can cause the thermal shutdown circuit to not operate properly or IC breakdown before operation.
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RESTRICTIONS ON PRODUCT USE
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in this document, and related hardware, software and systems (collectively “Product”) without notice.
 This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
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responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product,
or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all
relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for
Product and the precautions and conditions set forth in the “TOSHIBA Semiconductor Reliability Handbook” and (b) the instructions for
the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product
design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or
applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams,
programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for
such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR APPLICATIONS.
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equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
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products (mass destruction weapons). Product and related software and technology may be controlled under the Japanese Foreign
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noncompliance with applicable laws and regulations.
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