TCA62746AFG/AFNG TOSHIBA CMOS Integrated Circuit Silicon Monolithic TCA62746AFG,TCA62746AFNG 16-Output Constant Current LED Driver with Output Open/Short Detection The TCA62746 series are LED drivers with sink type constant circuit output, making them ideal for controlling LED modules and displays. The current value of the 16-output is configurable using one external resistor. In addition, these drivers are equipped with a function for detecting the output voltage when the output load LEDs open or short, and which then outputs the result as serial data. These drivers consist of a 16-constant current output block, a 16-bit shift register, a 16-bit latch and a 16-bit AND-gate. The suffix (G) appended to the part number represents a Lead (Pb)-Free product. TCA62746AFG TCA62746AFNG Features • 16-output built-in • Output open detection (OOD) function : When in detection mode, outputs the detection results via SOUT. • Output short detection (OSD) function : When in detection mode, outputs the detection results via SOUT. • Output current setting range : 2 to 50 mA × 16-constant current output • Current accuracy (@ REXT = 1.56 kΩ, VO = 1.0 V, VDD = 5.0 V) : Between outputs: ± 1% (typ.) Between devices: ± 3% (typ.) • Control data format: serial-in, parallel-out • I/O logic: TTL level (Schmitt trigger input) • Data transfer frequency: fMAX = 25 MHz (max) • Power supply voltage: VDD = 4.5 to 5.5 V • Operation temperature range: Topr = −40 to 85°C Weight SSOP24-P-300-1.00B : 0.32 g (typ.) SSOP24-P-300-0.65A : 0.14 g (typ.) • Constant current output voltage: VO = 17V (max) • Output delay circuit built-in: Internal data reset circuit for power-on resetting (POR) • Backward compatible to TB62706B and TB62726A series drivers • Package: FG type: SSOP24-P-300-1.00B FNG type: SSOP24-P-300-0.65A Caution This device is sensitive to electrostatic discharge. Please handle with care. The terminals which are marginal to electro static discharge are shown in the following table. (Please refer to page 22 for details.) ESD test MM Model Marginal terminals (MM Model Internal Standard ±200V) 5,6,7,8,9,10,11,12,13,14,15,16,19,20 * ESD test HBM Model Internal Standard (±2000V) is OK 1 2007-05-22 TCA62746AFG/AFNG Pin Assignment (top view) As shown below, this series has the same pin assignments as the TB62706B and TB62726A series: GND VDD SIN REXT SCK SOUT SLAT OE OUT0 OUT15 OUT1 OUT14 OUT2 OUT13 OUT3 OUT12 OUT4 OUT11 OUT5 OUT10 OUT6 OUT9 OUT7 OUT8 Note1: Short circuiting an output pin to a power supply pin (VDD or VLED*), or short-circuiting the REXT pin to the GND pin will likely exceed the rating, which in turn may result in smoldering and/or permanent damage. Please keep this in mind when determining the wiring layout for the power supply and GND pins. *VLED: LED power supply 2 2007-05-22 TCA62746AFG/AFNG OUT0 OUT1 OOD OOD Block Diagram OUT15 OUT0 OUT1 OUT15 OSD OSD OSD 3.0 V OOD 16 0.3 V 16 VDD Constant current outputs Delay1 Delay15 B.G POR GND OE SLAT REXT OE OOD/OSD controller ST-OUT Q15 Q0 Q1 16-bit D-latch D0 D1 D15 G SIN D0 Q15 Q0 Q1 16-bit shift register ST D0~D15 SCK OSD S 16-bit MUX OOD R Q15 R SOUT DO 16 3 2007-05-22 TCA62746AFG/AFNG Truth Table SCK SLAT OE SIN OUT0 … OUT7 … OUT15 *1 SOUT H L Dn Dn … Dn − 7 … Dn − 15 Dn − 15 L L Dn + 1 No Change Dn − 14 H L Dn + 2 Dn + 2 … Dn − 5 … Dn − 13 Dn − 13 - *2 L Dn + 3 Dn + 2 … Dn − 5 … Dn − 13 Dn − 13 - *2 H Dn + 3 OFF Dn − 13 Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to "L" the respective output will be OFF. Note2: “-“ is irrelevant to the truth table. Timing Chart n=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H SCK L H SIN L H SLAT L H OE L ON OUT0 OFF ON OUT1 OFF ON OUT2 OFF ON OUT15 OFF H SOUT L Note 1: Note 2: The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit. Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT pin is set to “H” the latch circuit does not hold data. The data will instead pass onto output. When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to the data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of the data. 4 2007-05-22 TCA62746AFG/AFNG Pin Functions Pin No Pin Name I/O Function 1 GND ⎯ 2 SIN I The serial data input pin. 3 SCK I The serial data transfer clock input pin. Also used for OOD/OSD mode settings. 4 SLAT I The latch signal input pin. Data is saved at L level. Also used for OOD/OSD mode settings. 5 OUT0 O A sink type constant current output pin. 6 OUT1 O A sink type constant current output pin. 7 OUT2 O A sink type constant current output pin. 8 OUT3 O A sink type constant current output pin. 9 OUT4 O A sink type constant current output pin. 10 OUT5 O A sink type constant current output pin. 11 OUT6 O A sink type constant current output pin. 12 OUT7 O A sink type constant current output pin. 13 OUT8 O A sink type constant current output pin. 14 OUT9 O A sink type constant current output pin. 15 OUT10 O A sink type constant current output pin. 16 OUT11 O A sink type constant current output pin. 17 OUT12 O A sink type constant current output pin. 18 OUT13 O A sink type constant current output pin. 19 OUT14 O A sink type constant current output pin. 20 OUT15 O A sink type constant current output pin. 21 OE I The constant current output enable signal input pin. During the “H” level, the output will be forced off. Also used for OOD/OSD mode settings. 22 SOUT O The serial data output pin. This pin outputs the OD/OSD detection result data. 23 REXT ⎯ The constant current value setting resistor connection pin. 24 VDD ⎯ The power supply input pin. The ground pin. 5 2007-05-22 TCA62746AFG/AFNG Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating *1 Unit Power supply voltage VDD −0.4 to 6.0 V IO 55 mA VIN −0.3 to VDD + 0.3 *2 V O u t p u t Logic c u r r e n t input voltage v o l t a g e VO −0.3 to 17 V Operating temperature Topr −40 to 85 °C Storage temperature Tstg −55 to 150 °C resistance Rth(j-a) 94(AFG type When mounted PCB)/120(AFNG type When mounted PCB) *3 °C/W PD 1.32(AFG type When mounted PCB)/1.04(AFNG type When mounted PCB) *3,4 W O u t p u t Thermal Power dissipation Note1: Voltage is ground referenced. Note2: However, do not exceed 6V. Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming) Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each degree (1°C) that the ambient temperature is exceeded (Ta = 25°C). Recommended Operating Conditions DC Items (Unless otherwise specified, Ta = −40°C to 85°C) Characteristics Symbol Test Conditions Min Typ. Max Unit Power supply voltage VDD ⎯ 4.5 ⎯ 5.5 V O u t p u t v o l ta ge wh e n O F F VO (OFF) OUTn ⎯ ⎯ 16 V Output voltage when ON VO (ON) OUTn 0.7 ⎯ 4 V High level logic input voltage VIH ⎯ 2.0 ⎯ VDD V ⎯ Low level logic input voltage VIL GND ⎯ 0.8 V High level SOUT output current IOH VDD = 5 V ⎯ ⎯ −1 mA Low level SOUT output current IOL VDD = 5 V ⎯ ⎯ 1 mA Constant current output IO OUTn 2 ⎯ 50 mA AC Items (Unless otherwise specified, VDD = 4.5 to 5.5 V, Ta = −40°C to 85°C) Characteristics Symbol Test Circuits Test Conditions Min Typ. Max Unit Serial data transfer frequency fSCK 7 ⎯ ⎯ ⎯ 25 MHz Clock pulse width twSCK 7 SCK = “H” or “L” 20 ⎯ ⎯ ns Latch pulse width twSLAT 7 SLAT = “H” 20 ⎯ ⎯ ns twOE1 7 OE = “H” or “L” ,REXT = 500 Ω 100 ⎯ ⎯ ns twOE2 ⎯ When error is detected *1 2 ⎯ ⎯ µs tHOLD1 7 ⎯ 5 ⎯ ⎯ ns tHOLD2 7 ⎯ 5 ⎯ ⎯ ns tHOLD3 7 ⎯ 10 ⎯ ⎯ ns tHOLD4 7 ⎯ 10 ⎯ ⎯ ns tSETUP1 7 ⎯ 5 ⎯ ⎯ ns tSETUP2 7 ⎯ 5 ⎯ ⎯ ns tSETUP3 7 ⎯ 10 ⎯ ⎯ ns tSETUP4 7 ⎯ 10 ⎯ ⎯ ns Maximum clock rise time tr 7 *2 ⎯ ⎯ 500 ns Maximum clock fall time tf 7 *2 ⎯ ⎯ 500 ns Enable H S o e l t pulse d u t p width i t m i m e e Note1: Please refer to page 16 for details of the error detection. Note2: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform, it may not be possible to achieve the timing required for data transfer. Please keep these timing conditions in mind when designing your application. 6 2007-05-22 TCA62746AFG/AFNG Electrical Characteristics (Unless otherwise specified, VDD = 4.5 to 5.5 V and Ta = 25°C) Characteristics Symbol Test Circuits High level logic output voltage VOH 1 Low level logic output voltage VOL High level logic input current Low level logic input current Min Typ. Max Unit IOH = −1 mA, SOUT VDD − 0.4 ⎯ ⎯ V 1 IOH = +1 mA, SOUT ⎯ ⎯ 0.4 V IIH 2 VIN = VDD, OE , SIN, SCK ⎯ ⎯ 1 µA IIL 3 VIN = GND, SLAT , SIN, SCK ⎯ ⎯ −1 µA IDD1 4 VO = 16 V, No REXT SCK = “L”, OE = “H” ⎯ 0.1 0.5 mA IDD2 4 REXT = 1.56 kΩ, All output OFF ⎯ ⎯ 7.0 mA IDD3 4 REXT = 500 Ω, All output OFF ⎯ ⎯ 14.0 mA IDD4 4 REXT = 1.2 kΩ, All output ON ⎯ ⎯ 7.0 mA IDD5 4 REXT = 500 Ω, All output ON ⎯ ⎯ 14.0 mA IO1 5 VDD = 5.0V, VO = 1.0 V, REXT = 1.56 kΩ 14.1 15 15.9 mA IO2 5 VDD = 5.0V, VO = 1.0 V, REXT = 500 Ω 44.2 47 49.8 mA Output OFF leak current IOK 5 VO = 16 V, REXT = 1.56 kΩ, All output OFF ⎯ ⎯ 0.5 µA Constant current error ∆IO 5 VDD = 5.0V, VO = 1.0 V, REXT = 1.56 kΩ, OUT0 to OUT15 ⎯ ±1 ±3 % Constant current power supply voltage regulation %VDD 5 VDD = 4.5 to 5.5V, VO = 1.0 V, ⎯ ±1 ±4 %/V Constant current output voltage r e g u l a t i o n %VO 5 ⎯ ±1 ±4 %/V P u l l - u p RUP 3 OE 250 500 800 kΩ RDOWN 2 SLAT 250 500 800 kΩ Min Typ. Max Unit Power supply current Constant current output r e s i s t o r Pull-down resistor Test Conditions REXT = 1.56 kΩ, OUT0 to OUT15 VDD = 5.0V, VO = 1.0 to 3.0 V, REXT =1.56 kΩ, OUT0 to OUT15 Electrical Characteristics during OOD/OSD Mode (Unless otherwise specified, VDD = 4.5 to 5.5 V and Ta = 25°C) Characteristics Symbol Test Circuits Test Conditions O O D v o l t a g e VOOD 6 REXT = 464 Ω~11.5 kΩ ⎯ 0.30 0.40 V O S D v o l t a g e VOSD 6 REXT = 464 Ω~11.5 kΩ 2.85 3.0 ⎯ V 7 2007-05-22 TCA62746AFG/AFNG Switching Characteristics (Unless otherwise specified, Ta = 25°C and VDD = 5.0 V) Characteristics Pr o pa ga ti o n delay time Symbol Test Circuits SCK- OUT0 tpLH1 7 SLAT - OUT0 tpLH2 OE - OUT0 Test Conditions Min Typ. Max SLAT = “H”, OE = “L” ⎯ 20 100 7 OE = “L” ⎯ 20 100 tpLH3 7 SLAT = “H” ⎯ 20 100 SCK-SOUT tpLH 7 5 10 ⎯ SCK- OUT0 tpHL1 7 SLAT = “H”, OE = “L” ⎯ 50 100 SLAT - OUT0 tpHL2 7 OE = “L” ⎯ 50 100 OE - OUT0 tpHL3 7 SLAT = “H” ⎯ 50 100 SCK-SOUT tpHL 7 15 20 ⎯ ⎯ ⎯ Unit ns O u t p u t r i s e t i m e tor 7 10 to 90% of voltage waveform ⎯ 30 150 ns O u t p u t f a l l t i m e tof 7 90 to 10% of voltage waveform ⎯ 70 150 ns Output delay t i m e tDLY (ON) 7 OUTn - OUT(n + 1) between adjacent outputs ⎯ 20 ⎯ ns Output delay t i m e tDLY (OFF) 7 ⎯ 20 ⎯ ns OUTn - OUT(n + 1) between adjacent outputs 8 2007-05-22 TCA62746AFG/AFNG I/O Equivalent Circuits 2. OE 1. SCK, SIN VDD VDD (SCK) (SIN) OE GND GND 3. SLAT 4. SOUT VDD VDD SLAT SOUT GND GND 5. OUT0 to OUT15 OUT0 to OUT15 GND 9 2007-05-22 TCA62746AFG/AFNG Test Circuits Test Circuit1: High level logic input voltage / Low level logic input voltage SCK VDD OUT0 SIN F.G SLAT OUT7 OE OUT15 SOUT IO = -1mA~1mA V VDD = 4.5~5.5 V GND REXT REXT CL = 10.5 pF VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) Test Circuit2: High level logic input current / Pull-down resistor VIN = VDD A SCK VDD OUT0 SIN A SLAT A OUT7 OE A OUT15 VDD = 4.5~5.5 V SOUT CL = 10.5 pF GND REXT REXT Test Circuit3: Low level logic input current / Pull-up resistor A OUT0 SIN SLAT OUT7 OE OUT15 REXT GND SOUT 10 VDD = 4.5~5.5 V A VDD CL = 10.5 pF A SCK REXT A 2007-05-22 TCA62746AFG/AFNG Test Circuit4: Power supply current SCK F.G VDD OUT0 SIN SLAT OUT7 OE OUT15 A GND SOUT CL = 10.5 pF VDD = 4.5~5.5V REXT REXT = 1.56kΩ, 500Ω VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) Test Circuit5: Constant current output / Output OFF leak current / Constant current error Test Circuit5: Constant current power supply voltage regulation / Constant current output voltage regulation SCK OUT0 A OUT7 A OUT15 A SIN SLAT OE GND CL = 10.5 pF SOUT VDD = 4.5~5.5V REXT REXT = 1.56kΩ, 500Ω VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) VO = 1V, 3V, 16V F.G VDD Test Circuit6: OOD voltage / OSD voltage SCK F.G VDD OUT0 SIN V SLAT OUT7 OE V OUT15 V VDD = 4.5 V~5.5 V VO2 SOUT VO1 = 1 V GND CL = 10.5 pF REXT REXT = 464Ω , 11.5kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) All output terminals is set to turning on, only one output terminal is connected with the VO2 power supply, and VO2 is changed. VOOD/VOSD is confirmed by the error detection result from SOUT. 11 2007-05-22 TCA62746AFG/AFNG Test Circuit7: Switching Characteristics RL = 85 Ω VDD SCK OUT0 CL SIN SLAT RL OUT7 OE CL RL OUT15 GND SOUT CL = 10.5 pF REXT = 500Ω CL = 10.5 pF REXT VLED =5V VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) VDD = 4.5~5.5 V F.G Output Delay Circuit This is designed for high speed switching between outputs and is intended to have the effect of reducing switching noise by reducing the di/dt when all outputs are ON or OFF at the same time.There is a switching time lag (20 ns typ.) between adjacent outputs. The equivalent circuit chart of the delay circuit is shown in the following. OE OUT0 D0 ×1 OUT1 D1 Delay ×2 OUT2 D2 Delay Delay ×15 OUT15 D15 Delay Delay 12 2007-05-22 TCA62746AFG/AFNG Timing Waveforms 1. SCK, SIN, SOUT twSCK SCK 50% 50% tSETUP1 SIN 90% 50% twSCK 50% 90% 10% 10% tr tf 50% tHOLD1 SOUT 50% tpLH/tpHL 2. SCK, SIN, SLAT , OE , OUT0 SCK 50% 50% SIN tHOLD2 SLAT tSETUP2 50% 50% twSLAT twOE1 50% OE OUT0 50% 50% tpHL1/tpLH1 tpHL2/tpLH2 3. OUT0 twOE1 50% 50% OE tpLH3 tpHL3 OFF 90% 50% 50% 90% OUT0 10% 10% ON tor tof 13 2007-05-22 TCA62746AFG/AFNG 4. OOD Mode/OSD Mode twsck SCK 50% 50% 50% tSETUP3 tHOLD3 OE 50% 50% tSETUP4 SLAT 50% tHOLD4 50% 5. OOD/OSD Read Mode SCK OE 50% 50% 50% 50% twOE2 14 2007-05-22 TCA62746AFG/AFNG PWM grayscale control This IC is possible to PWM grayscale control by the input of the PWM signal to the EN terminal. When PWM grayscale control is done, we recommend the LED power-supply voltage to be set to become the satiety region of the constant current characteristic. When using this IC outside the saturation area, PWM grayscale control cannot be normally done. Switching to Open Circuit Detection (OOD) and Short Circuit Detection (OSD) Modes Switching to OSD mode 1 2 3 4 5 6 OE H L H H H H SLAT L L L H L L SCK The signal sequence set to be in the OSD mode. Here, the SLAT active pulse would not latch any data. Switching to OOD mode 1 2 3 4 5 6 OE H L H H H H SLAT L L L L L H SCK The signal sequence set to be in the OOD mode. Here, the SLAT active pulse would not latch any data. 15 2007-05-22 TCA62746AFG/AFNG Reading Error Status Code n> =3 1 2 3 SCK MIN 2 µs H OE L L L H SOUT Bit 15 H H H H Error status code Bit Bit Bit Bit Bit 14 13 12 11 10 When the above signal sequence is set in the OOD and OSD modes, the error state code can be read through the terminal SOUT. Error state code of OOD detection mode Error state code State of output terminal 0 1 Open circuit Normal Error state code State of output terminal 0 1 Short circuit Normal VOOD ≥ VO VOOD < VO Error state code of OSD detection mode VOSD ≤ VO VOSD > VO Description In the OOD and OSD modes, the state of OE must be switched from “H” to “L”. And, then, This IC would execute Open-/Short-circuit Detection as well as enabling output ports to drive current. At least three clock must be inputs at the “L” state of OE and the third clock should be at least 2 µs after the falling edge of OE . the detected error status into the built-in shift register is done by rising edge of this third clock. When OE is “L", the serial data cannot be input from the terminal SIN. When OE is changed from “L" to “H", the error state code is output from the terminal SOUT synchronizing with the clock. Switching to Normal Mode 1 2 3 4 5 6 OE H L H H H H SLAT L L L L L L SCK “L” level The signal sequence set to be in the Normal mode. 16 2007-05-22 TCA62746AFG/AFNG Timing chart of error detection mode (OSD mode) SOUT, 0 SIN, 0 TCA62746, 0 SIN, 1 SOUT, 1 SIN, 2 TCA62746, 1 SOUT, 2 TCA62746, 2 SOUT, N-1 TCA62746, N-2 TCA62746, N-1 SCK SLAT OE 1 2 3 4 5 N × 16 CLK 6 N × 15 CLK 3 CLK or more 1 2 3 4 5 6 SCK SIN SIN, 0 2 1 0 Don’t care N × 16-1 2CLK 2 µs SLAT OE SOUT, 0 15 14 SOUT, 1 31 30 SOUT, N-1 A. Switching to Error detection mode B. Setting of output terminal that does the error 17 N ×16-1 C. Detection the error D. Reading back the error status code Error: 0, Normal: 1 E. Switching to Normal 2007-05-22 TCA62746AFG/AFNG Reference data *This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design. Set output current – Duty cycle graph IO - Duty 60 50 50 40 40 IO (mA) IO (mA) IO - Duty 60 30 30 20 20 VDD=5.5V VO=1.0V Ta=25°C ON PCB 10 TCA62746AFG TCA62746FG VDD=5.5V VO=1.0V Ta=55°C ON PCB 10 TCA62746AFNG TCA62746FNG All output ON TCA62746AFG TCA62746FG TCA62746AFNG TCA62746FNG All output ON 0 0 0 20 40 60 80 100 0 20 40 Duty - Turn on rate (%) 60 80 100 Duty - Turn on rate (%) P D - Ta IO - Duty 1.4 60 TCA62746FG TCA62746AFG 1.2 TCA62746AFNG TCA62746FNG 50 1.0 P D (W) IO (mA) 40 30 20 0.6 0.4 VDD=5.5V VO=1.0V Ta=80°C ON PCB 10 0.8 TCA62746FG TCA62746AFG 0.2 TCA62746FNG TCA62746AFNG ON PCB All output ON 0 0.0 0 20 40 60 80 100 0 Duty - Turn on rate (%) 10 20 30 40 50 60 70 80 Ta (℃) 18 2007-05-22 90 TCA62746AFG/AFNG Reference data *This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design. Output Current – REXT Resistor IO - REXT 50 Theoretical value 45 IO (A) = (1.23(V) ÷ REXT (Ω)) × 19 40 IO (mA) 35 30 25 20 15 10 VDD=5.0V VO=1.0V Ta=25°C 5 0 0 1 2 3 4 5 6 7 REXT (kΩ) 8 9 10 11 12 Constant current characteristic IO - VO 60 VDD=5.0V VO=1.0V Ta=25°C 50 IO (mA) 40 30 20 10 0 0.0 0.5 1.0 1.5 VO (V) 19 2.0 2.5 3.0 2007-05-22 TCA62746AFG/AFNG Package Dimensions Weight: 0.32 g (typ.) 20 2007-05-22 TCA62746AFG/AFNG Package Dimensions Weight: 0.14 g (typ.) 21 2007-05-22 TCA62746AFG/AFNG Serge resisting The terminals which are weak to electro static discharge are shown in the following table. MM Model ESD test Result (Internal Standard ±200V) pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 - Serge Standard VDD VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND GND + Serge TEST Result 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 200V 22 Standard VDD VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND VDD,GND GND TEST Result 200V 200V 200V 200V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 160V 200V 200V 200V 200V 2007-05-22 TCA62746AFG/AFNG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. 23 2007-05-22 TCA62746AFG/AFNG IC Usage Considerations Notes on handling of ICs [1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. [4] Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [5] Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. 24 2007-05-22 TCA62746AFG/AFNG 25 2007-05-22