ANADIGICS AWC6325

AWC6325
HELP3ETM Dual-band Cellular & PCS CDMA
3.4 V Linear Power Amplifier Module
PRELIMINARY DATA SHEET - Rev 1.3
FEATURES
and linearity, which greatly reduces the total current
drawn from the battery. This feature, in conjunction
with selectable operating modes, enables significant
improvements in overall power added efficiency of
the AWC6325 across the entire dynamic range of
operating powers. APT requires use of an external
variable voltage supply (DC-DC converter), which is
used to provide the variable voltage to Vcc pad of the
amplifier. A low-leakage shutdown mode increases
standby time. This PA has built-in directional couplers
for each band, with a common coupler output port
CPL_OUT. The 3 mm x 5 mm x 0.9 mm surface mount
package incorporates matching networks optimized
for output power, efficiency and linearity in a 50 Ω
system. The device is manufactured on an advanced
InGaP HBT MMIC technology offering state-of-the-art
reliability, temperature stability, and ruggedness.
• InGaP HBT Technology
• High Efficiency:
• 37 % @ POUT = +28 dBm
• 20 % @ POUT = +16 dBm
• 10 % @ POUT = +10 dBm
• Low Quiescent Current: 4 mA
• Internal Voltage Regulation
• Built-in Directional Coupler
• Common VMODE Control Line
• Suitable for SMPS and average power tracking
systems with variable supply voltages
• APT can reduce TS.09 average power
consumption more than 25%
• Reduced External Component Count
• Thin Package: 0.9 mm
• RoHS Compliant Package, 260 oC MSL-3
APPLICATIONS
• Dual-band Wireless Handsets and Data Devices
for CDMA/EVDO networks:
• Cellular BC 0 and 10
1
14 GND
Bias Control
Voltage Regulation
RFIN_CELL 2
• PCS BC 1 and 14
PRODUCT DESCRIPTION
VEN_CELL
CPL
VMODE1 3
AWC6325 addresses the demand for increased
integration in dual-band handsets for CDMA networks.
The small footprint 3 mm x 5 mm x 0.9 mm surface
mount RoHS compliant package contains independent
RF PA paths to ensure optimal performance in both
frequency bands in less board area than two single
band PAs. The package pinout was chosen to enable
handset manufacturers to independently provide
bias to both power amplifiers and simplify control
with common mode pins. The AWC6325 is part of
ANADIGICS’ 3rd generation of High-Efficiency-atLow-Power (HELP3E™) family of power amplifiers,
which deliver low quiescent currents and significantly
greater efficiency through selectable bias modes for
high, medium and low power operation. The AWC6325
is designed for use both with and without average
power tracking (APT). APT can be used to optimize
the Vcc level for the desired output power level
12 VCC
VBATT 4
11 VCCA
VMODE2 5
10 CPLOUT
RFIN_PCS 6
VEN_PCS 7
05/2012
13 RFOUT_CELL
CPL
Bias Control
Voltage Regulation
GND at Slug (pad)
Figure 1: Block Diagram
9 GND
8 RFOUT_PCS
AWC6325
VMODE1
CPLOUT
VMODE2
Figure 2: Pinout
Table 1: Pin Description
PIN
DESCRIPTION
1
VEN_CELL
Enable Voltage for Cell Band
2
RFIN_CELL
RF Input for Cell Band
3
VMODE1
Mode Control Voltage 1
Battery Voltage
4
VBATT
5
VMODE2
Mode Control Voltage 2
6
RFIN_PCS
RF Input for PCS Band
7
VEN_PCS
Enable Voltage for PCS Band
8
RFOUT_PCS
9
GND
10
CPLOUT
11
VCCA
12
VCC
13
14
2
NAME
RF Output for PCS Band
Ground
Coupler Output Port
Supply Voltage A
Supply Voltage
RFOUT_CELL RF Output for Cell Band
GND
Ground
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
AWC6325
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER
MIN
MAX
UNIT
Supply Voltage (VBATT, VCC, VCCA)
0
+5
V
Mode Control Voltage (VMODE1,2, VEN)
0
+3.5
V
RF Input Power (PIN)
-
+10
dBm
-40
+150
°C
Storage Temperature (TSTG)
Stresses in excess of the absolute ratings may cause permanent damage.
Functional operation is not implied under these conditions. Exposure
to absolute ratings for extended periods of time may adversely affect
reliability.
Table 3: Operating Ranges
PARAMETER
MIN
TYP
MAX
UNITS
Operating Frequency (f)
814
1850
-
849
1915
MHz
Supply Voltage (VCC, VCCA)
+0.8
+3.4
+4.35
V
Battery Voltage (VBATT)
+3.2
+3.4
+4.35
V
Enable Voltage (VEN_CELL, VEN_PCS)
+1.35
0
+1.8
0
+3.1
+0.5
V
PA “on”
PA “shut down”
Mode Control Voltage (VMODE1,2)
+1.35
0
+1.8
0
+3.1
+0.5
V
Logic High
Logic Low
Cellular RF Output Power CDMA
CDMA, HPM
CDMA, MPM
CDMA, LPM
27.5 (1)
-
28.0
16.0
10.0
-
dBm
CDMA 2000, RC-1
PCS RF Output Power CDMA
CDMA, HPM
CDMA, MPM
CDMA, LPM
27.5 (1)
-
28.0
16.0
10.0
-
dBm
CDMA 2000, RC-1
-30
-
+90
°C
Case Temperature (TC)
COMMENTS
Cellular BC0 & 10
PCS BC1 & 14
The device may be operated safely over these conditions; however, parametric performance is guaranteed only
over the conditions defined in the electrical specifications.
Notes:
(1)For operation at VCC = +3.2 V, POUT is derated by 0.5 dB.
3
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
AWC6325
Table 4: Electrical Specifications - Cellular Band (BC 0, 10)
(TC = +25 °C, VBATT = VCC = +3.4 V, VEN_CELL = +1.8 V, 50 Ω system, CDMA2000 RC-1 waveform)
PARAMETER
MIN
TYP
MAX
UNIT
25
14
7
28
17
12
31
19
14
Adjacent Channel Power
at ± 885 kHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
-
-48.5
-52
-53.5
Adjacent Channel Power
at ± 1.98 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
-
Power-Added Efficiency (1)
-
Quiescent Current (Icq)
Mode Control Current
COMMENTS
POUT
VMODE1
VMODE2
dB
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
-46.5
-46.5
-46.5
dBc
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
-58
-59
-68
-56
-56
-56
dBc
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
37.5
19.5
10
-
%
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
-
4
-
mA
through VCC pins, VMODE1,2 = +1.8 V
-
0.5
-
mA
through VMODE pin, VMODE1,2 = +1.8 V
BATT Current
-
1.5
-
mA
through VBATT pin, VMODE1,2 = +1.8V
Enable Current
-
0.3
-
mA
through VEN_CELL pin, VMODE1,2 = +1.8 V
Total Decoder Current on
VBATT (in Shutdown mode)
-
7
-
µA
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
HBT Leakage Current (VCC)
(Shutdown mode)
-
<1
-
mA
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
Noise In Receive Band
-
-133
-
Harmonics
2fO
3fO, 4fO
-
-
-35
-35
dBc
Input Impedence
-
2.5:1
-
VSWR
Coupling Factor
-
22
-
dB
Gain
Spurious Output Level
(all spurious outputs)
Load mismatch stress with no
permanent degradation or failure
dBm/Hz 869 MHz to 894 MHz
-
-
-65
dBc
8:1
-
-
VSWR
POUT < +28 dBm
POUT < +28 dBm
In-band load VSWR < 5:1
Out-of-band load VSWR < 10:1
Applies over all operating conditions
Applies over full operating range
Notes:
(1) PAE and ACP measured at 836.5 MHz.
4
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
AWC6325
Table 5: Electrical Specifications - PCS Band (BC 1, 14)
(TC = +25 °C, VBATT = VCC = +3.4 V, VEN_PCS = +1.8 V, 50 Ω system, CDMA2000 RC-1 waveform)
PARAMETER
MIN
TYP
MAX
UNIT
24
10
7
26.5
13
9
30
16
12
Adjacent Channel Power
at ± 1.25 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
-
-48
-52.5
-53
Adjacent Channel Power
at ± 1.98 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
-
Adjacent Channel Power
at ± 2.25 MHz offset (1)
Primary Channel BW = 1.23 MHz
Adjacent Channel BW = 30 kHz
COMMENTS
POUT
VMODE1
VMODE2
dB
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
-46.5
-46.5
-46.5
dBc
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
-55
-60
-63
-54
-54
-54
dBc
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
-
-59.5
-63.5
-67.5
-56.5
-57
-57
dBc
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
Power-Added Efficiency (1)
-
37
20
10
-
%
+28 dBm
+16 dBm
+10 dBm
0V
1.8 V
1.8 V
0V
0V
1.8 V
Quiescent Current (Icq)
-
4
-
mA
through VCC pins, VMODE1,2 = +1.8 V
Mode Control Current
-
0.5
-
mA
through VMODE pin, VMODE1,2 = +1.8 V
BATT Current
-
1.5
-
mA
through VBATT pin, VMODE1,2 = +1.8V
Enable Current
-
0.3
-
mA
through VEN_PCS pin, VMODE1,2 = +1.8 V
Total Decoder Current on VBATT
(in Shutdown mode)
-
7
-
µA
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
HBT Leakage Current on VCC
(in Shutdown mode)
-
<1
-
µA
VBATT = +4.35 V, VCC = +4.35 V,
VEN_CELL = 0 V, VMODE1,2 = 0 V
Noise In Receive Band
-
-133
-
Harmonics
2fO
3fO, 4fO
-
-
-30
-30
dBc
Input Impedence
-
-
2:1
VSWR
Coupling Factor
-
22
-
dB
Gain
Spurious Output Level
(all spurious outputs)
Load mismatch stress with no
permanent degradation or failure
dBm/Hz 1930 MHz to 1990 MHz
-
-
-65
dBc
8:1
-
-
VSWR
POUT < +28 dBm
POUT < +28 dBm
In-band load VSWR < 5:1
Out-of-band load VSWR < 10:1
Applies over all operating conditions
Applies over full operating range
Notes:
(1) ACPRs and Efficiency measured at 1880 MHz.
5
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
AWC6325
APPLICATION INFORMATION
To ensure proper performance, refer to all related
Application Notes on the ANADIGICS web site:
http://www.anadigics.com
Shutdown Mode
The power amplifier may be placed in a shutdown
mode by applying logic low levels (see Operating
Ranges table) to the VENABLE and VMODE pads.
Bias Modes
The power amplifier may be placed in Low, Medium,
or High Bias modes by applying the appropriate logic
level (see Operating Ranges table) to the VMODE pin.
The Bias Control table lists the recommended modes
of operation for various applications.
Vcontrols
Venable/Vmode(s)
On Sequence Start
T_0N = 0µ
Rise/Fall Max 1µS
Defined at 10% to 90%
of Min/Max Voltage
Off Sequence Start
T_0FF = 0µ
ON Sequence
OFF Sequence
RFIN_CELL,PCS
notes 1,2
VEN_CELL,PCS
VCC, VCCA
note 1
T_0N+1µS
T_0N+3µS
T_0FF+2µS T_0FF+3µS
Referenced After 90% of Rise
Time
Referenced Before10% of Fall
Time
Figure 3: Recommended ON/OFF Timing Sequence
Notes:
(1) Level might be changed after RF is ON.
(2) RF OFF defined as PIN ≤ -30 dBm.
(3) Switching simultaneously between VMODE and VEN is not recommended.
Table 6: Bias Control
APPLICATION
POUT
LEVELS
BIAS
MODE
VEN_CELL
VEN_PCS
VMODE1
VMODE2
VCC
VBATT
Low Bias Mode
< +10 dBm
Low
+1.8 V
+1.8 V
+1.8 V
0.8 - 4.35 V
> 3.2 V
Medium Bias Mode
> +10 dBm
< +16 dBm
Medium
+1.8 V
+1.8 V
0V
0.8 - 4.35 V
> 3.2 V
High Bias Mode
> +16 dBm
High
+1.8 V
0V
0V
1.3 - 4.35 V
> 3.2 V
-
Shutdown
0V
0V
0V
3.2 - 4.35 V
>3.2 V
Shutdown
6
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
AWC6325
VEN_CELL
1
14
Bias Control
Voltage Regulation
RFIN_CELL
CPL
2
RFOUT_CELL
12
3
VMODE1
13
VCC
1000 pF
VBATT
2.2 µF
VMODE2
RFIN_PCS
VEN_PCS
68pF
4
11
68 pF
5
10
CPL
6
7
Bias Control
Voltage Regulation
2.2 µF
CPLOUT
9
8
GND at Slug (pad)
Figure 4: Application Circuit
7
VCCA
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
RFOUT_PCS
AWC6325
PACKAGE OUTLINE
Figure 5: Package Outline - 14 Pin 3 mm x 5 mm x 0.9 mm Surface Mount Module
Pin 1 Identifier
Date Code
YY= Year WW= Work Week
6325
Part Number
LLLLLNN
Lot Number
YYWWCC
Country Code(CC)
Figure 6: Branding Specification
8
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
AWC6325
PCB BOARD Design GuidELINES
Refer to Figure 7 for the recommended PCB metal
design, soldermask design, and stencil print patterns
when assembling with ANADIGICS modules.
It is important to note that the PCB metal design is
dependent upon several factors: the electrical and
thermal performance requirements of the product,
and the PCB-to-device interconnect pattern. The
PCB metal design recommendations primarily deal
with the PCB-to-device interconnection. Specific
board-level electrical and thermal performance requirements will be dictated by the physical geometry
of the specific application and are the responsibility
of the end product manufacturer.
Figure 7: PCB Board Design Guidelines
9
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
AWC6325
Figure 8: Carrier Tape Drawing
LL
0%
FU
10
75
%
50
%
25
%
Ø177.8
MIN.
Ø50.8
±0.2 Ø54.2
±0.1
MADE IN USA
(2X)SLOT 3.0±.1
12.4±.
(3X)1.78±.25
Ø13.0±0.2
DIMENSIONS ARE IN MILLIMETERS
Ø20.6±0.13
CENTER HOLE DETAIL
ENLARGED FOR CLARITY
NOTES:
1. MATERIAL:
BLACK CARBON POLYSTYRENE
SURFACE RESISTIVITY:
1X10 4 TO 1X10 5 ohms/square
DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
Figure 9: Reel Drawing
10
PRELIMINARY DATA SHEET - Rev 1.3
05/2012
AWC6325
ORDERING INFORMATION
ORDER NUMBER
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
COMPONENT PACKAGING
AWC6325Q7
-30 C to +90 C
RoHS Compliant 14 Pin
3 mm x 5 mm x 0.9 mm
Surface Mount Module
Tape and Reel, 2500 pieces per Reel
AWC6325P9
-30 C to +90 C
RoHS Compliant 14 Pin
3 mm x 5 mm x 0.9 mm
Surface Mount Module
Partial Tape and Reel
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A.
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice.
The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to
change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed
to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers
to verify that the information they are using is current before placing orders.
warning
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product
in any such application without written consent is prohibited.
11
PRELIMINARY DATA SHEET - Rev 1.3
05/2012