L6398 High voltage high and low side driver Features ■ High voltage rail up to 600 V ■ dV/dt immunity ±50 V/ns in full temperature range ■ Driver current capability: – 290 mA source, – 430 mA sink $)0 ■ Switching times 75/35 ns rise/fall with 1 nF load ■ 3.3 V, 5 V TTL/CMOS input comparators with hysteresis ■ Integrated bootstrap diode ■ Fixed 320 ns dead-time ■ Interlocking function ■ Compact and simplified layout ■ Bill of material reduction ■ Flexible, easy and fast design 3/ Description The L6398 is a high-voltage device manufactured with the BCD “OFF-LINE” technology. It is a single chip half-bridge gate driver for N-channel power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing microcontroller/DSP. Applications ■ Motor driver for home appliances, factory automation, industrial drives and fans. Table 1. April 2011 Device summary Order codes Package Packaging L6398N DIP-8 Tube L6398D SO-8 Tube L6398DTR SO-8 Tape and reel Doc ID 18199 Rev 3 1/16 www.st.com 16 Contents L6398 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2/16 Doc ID 18199 Rev 3 L6398 Block diagram 1 Block diagram Figure 1. Block diagram #005453"1%3*7&3 7$$ 67 %&5&$5*0/ 7 '-0"5*/(4536$563& GSPN-7( )*/ )7( %3*7&3 -0(*$ 4 3 4)005 5)306() 13&7&/5*0/ )7( 065 7$$ %&"%5*.& (/% #005 67 %&5&$5*0/ -&7&4)*'5&3 -*/ -7( %3*7&3 -7( !-V Doc ID 18199 Rev 3 3/16 Pin connection 2 L6398 Pin connection Figure 2. Pin connection (top view) -*/ #005 )*/ )7( 7$$ 065 (/% -7( !-V Table 2. Pin description Pin n # Pin name Type 1 LIN I Low side driver logic input (active low) 2 HIN I High side driver logic input (active high) 3 VCC P Lower section supply voltage 4 GND P Ground 5 LVG (1) O Low side driver output 6 OUT P High side (floating) common voltage O High side driver output P Bootstrapped supply voltage (1) 7 HVG 8 BOOT Function 1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. 4/16 Doc ID 18199 Rev 3 L6398 3 Truth table Truth table Table 3. Truth table Input Output LIN HIN LVG HVG H L L L L H L L L L H L H H L H Doc ID 18199 Rev 3 5/16 Electrical data L6398 4 Electrical data 4.1 Absolute maximum ratings Table 4. Absolute maximum rating Value Symbol Parameter Unit Min Max Vcc Supply voltage -0.3 21 V Vout Output voltage Vboot - 21 Vboot + 0.3 V Vboot Bootstrap voltage -0.3 620 V Vhvg High side gate output voltage Vout - 0.3 Vboot + 0.3 V Vlvg Low side gate output voltage -0.3 Vcc + 0.3 V Logic input voltage -0.3 15 V Allowed output slew rate 50 V/ns Ptot Total power dissipation (TA = 25 °C) 800 mW TJ Junction temperature 150 °C Tstg Storage temperature 150 °C Vi dVout/dt -50 Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 1 kV (human body model) 4.2 Thermal data Table 5. Thermal data Symbol Rth(JA) 4.3 Parameter Thermal resistance junction to ambient DIP-8 Unit 150 100 °C/W Recommended operating conditions Table 6. Recommended operating conditions Symbol Pin Vcc 3 VBO (1) 8-6 Vout 6 Parameter Test condition Min Max Unit Supply voltage 10 20 V Floating supply voltage 9.8 20 V 580 V 800 kHz 125 °C Output voltage fsw Switching frequency TJ Junction temperature - 11 (2) HVG, LVG load CL = 1 nF 1. VBO = Vboot - Vout 2. LVG off. Vcc = 10 V Logic is operational if Vboot > 5 V 6/16 SO-8 Doc ID 18199 Rev 3 -40 L6398 Electrical characteristics 5 Electrical characteristics 5.1 AC operation Table 7. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) Symbol ton toff Pin 1, 2 vs 5, 7 DT tr tf Parameter Test condition High/low side driver turn-on Vout = 0 V propagation delay Vboot = Vcc CL = 1 nF High/low side driver turn-off VIN = 0 to 3.3 V propagation delay See Figure 3 Min Typ Max Unit 50 125 200 ns 50 125 200 ns 225 320 415 ns Dead time (1) CL = 1 nF Rise time CL = 1 nF 75 120 ns Fall time CL = 1 nF 35 70 ns 5, 7 1. See Figure 4 on page 9. Figure 3. Timing LIN 50% 50% tr tf 90% LVG 10% 10% ton HIN 90% toff 50% 50% tr tf 90% HVG 90% 10% 10% ton toff Doc ID 18199 Rev 3 7/16 Electrical characteristics L6398 5.2 DC operation Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) Symbol Pin Vcc_hys Parameter Test condition Min Typ Max Unit 1.2 1.5 1.8 V Vcc UV turn ON threshold 9 9.5 10 V Vcc UV turn OFF threshold 7.6 8 8.4 V Vcc UV hysteresis Vcc_thON Vcc_thOFF 3 Iqccu Undervoltage quiescent supply current Vcc = 7 V LIN = 5 V; HIN = GND; 90 150 μA Iqcc Quiescent current Vcc = 15 V LIN = 5 V; HIN = GND; 380 440 μA Bootstrapped supply voltage section (1) VBO_hys VBO_thON VBO_thOFF 8 VBO UV hysteresis 0.8 1 1.2 V VBO UV turn ON threshold 8.2 9 9.8 V VBO UV turn OFF threshold 7.3 8 8.7 V IQBOU Undervoltage VBO quiescent current VBO = 7 V, LIN = HIN = 5V 30 60 μA IQBO VBO quiescent current VBO = 15 V, LIN = HIN = 5V 190 240 μA High voltage leakage current Vhvg = Vout = Vboot = 600 V 10 μA ILK Bootstrap driver on resistance RDS(on) (2) LVG ON 120 Ω Driving buffers section Iso Isi 5, 7 High/low side source short circuit current VIN = Vih (tp < 10 μs) 200 290 mA High/low side sink short circuit current VIN = Vil (tp < 10 μs) 250 430 mA Logic inputs Vil Low logic level voltage High logic level voltage Vih Vil_S 0.8 V 1, 2 1, 2 IHINh 2.25 Single input voltage LIN and HIN connected together and floating HIN logic “1” input bias current HIN = 15 V HIN logic “0” input bias current HIN = 0 V 110 V 175 0.8 V 260 μA 1 μA 20 μA 1 μA 2 IHINl ILINl LIN logic “0” input bias current LIN = 0 V 3 6 1 ILINh LIN logic “1” input bias current LIN = 15 V 1. VBO = Vboot - Vout 2. RDSON is tested in the following way: RDSON = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. 8/16 Doc ID 18199 Rev 3 L6398 Waveforms definitions Figure 4. Dead time and interlocking waveforms definitions G HIN INTE RLO CKIN CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME RLO CKIN G LIN INTE 6 Waveforms definitions LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected togheter and driven by just one control signal Doc ID 18199 Rev 3 9/16 Typical application diagram L6398 7 Typical application diagram Figure 5. Application diagram 7$$ #005453"1%3*7&3 67 %&5&$5*0/ 7 '-0"5*/(4536$563& GSPN-7( -*/ #005 67 %&5&$5*0/ )7 )7( %3*7&3 -0(*$ -&7&4)*'5&3 '30.$0/530--&3 4 $CPPU )7( 065 3 4)005 5)306() 13&7&/5*0/ 50-0"% '30.$0/530--&3 )*/ (/% 7$$ %&"%5*.& -7( %3*7&3 -7( !-V 10/16 Doc ID 18199 Rev 3 L6398 8 Bootstrap driver Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 6). In the L6398 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 7. An internal charge pump (Figure 7) provides the DMOS driving voltage. 8.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1 Q gate C EXT = ------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: Equation 2 CBOOT >>> CEXT e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 190 μA, so if HVG TON is 5 ms, CBOOT has to supply 1 μC to CEXT. This charge on a 1 μF capacitor means a voltage drop of 1V. The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value: 120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Equation 3 Q gate V drop = I ch arg e R dson → V drop = ------------------ R dson T ch arg e Doc ID 18199 Rev 3 11/16 Bootstrap driver L6398 where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 μs. In fact: Equation 4 30nC V drop = --------------- ⋅ 120Ω ∼ 0.7V 5μs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 6. Bootstrap driver with high voltage fast recovery diode DBOOT VCC BOOT H.V. HVG CBOOT OUT TO LOAD LVG Figure 7. Bootstrap driver with internal charge pump BOOT VCC H.V. HVG CBOOT OUT TO LOAD LVG 12/16 Doc ID 18199 Rev 3 L6398 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 9. DIP-8 mechanical data mm. inch Dim. Min A Typ Max Min 3.32 Typ Max 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 3.81 Z Figure 8. 1.52 0.125 0.150 0.060 Package dimensions Doc ID 18199 Rev 3 13/16 Package mechanical data L6398 Table 1. SO-8 mechanical data mm. inch Dim. Min Typ Max Min Typ Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 (1) 4.80 5.00 0.189 0.197 E 3.80 4.00 0.15 0.157 D e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k 0° (min.), 8° (max.) ddd 0.10 0.004 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). Figure 9. 14/16 Package dimensions Doc ID 18199 Rev 3 L6398 10 Revision history Revision history Table 10. Document revision history Date Revision Changes 14-Dec-2010 1 First release. 16-Feb-2011 2 Updated Table 8. 01-Apr-2011 3 Typo in coverpage Doc ID 18199 Rev 3 15/16 L6398 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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