L6391 High-voltage high and low side driver Features ■ High voltage rail up to 600 V ■ dV/dt immunity ± 50 V/nsec in full temperature range ■ Driver current capability: – 290 mA source, – 430 mA sink ■ Switching times 75/35 nsec rise/fall with 1 nF load ■ 3.3 V, 5 V TTL/CMOS inputs with hysteresis Description ■ Integrated bootstrap diode ■ Comparator for fault protections ■ Smart shut-down function ■ Adjustable dead-time The L6391 is a high-voltage device manufactured with the BCD “OFF-LINE” technology. It is a single chip half-bridge gate driver for N-channel power MOSFET or IGBT. ■ Interlocking function ■ Compact and simplified layout ■ Bill of material reduction ■ Effective fault protection ■ Flexible, easy and fast design The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing microcontroller/DSP. An integrated comparator is available for protections against overcurrent, overtemperature, etc. Applications ■ Motor driver for home appliances, factory automation, industrial drives and fans. ■ HID ballasts, power supply units. Table 1. Device summary Order codes Package Packaging L6391N DIP-14 Tube L6391D SO-14 Tube L6391DTR SO-14 Tape and reel December 2010 Doc ID 17892 Rev 1 1/21 www.st.com 21 Contents L6391 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Smart shut down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 Doc ID 17892 Rev 1 L6391 1 Block diagram Block diagram Figure 1. Block diagram "//4342!0$2)6%2 6## &,/!4).'3425#452% FROM,6' 56 $%4%#4)/. 56 $%4%#4)/. (6' $2)6%2 3 ,%6%, 3()&4%2 (). 2 (6' ,/')# 6 3(//4 4(2/5'( 02%6%.4)/. ,). "//4 /54 6## ,6' $2)6%2 ,6 ' 3$/$ 6 3-!24 3$ #/-0!2!4/2 #0 #0 $4 '.$ $%!$ 4)-% !-V Doc ID 17892 Rev 1 3/21 Pin connection 2 L6391 Pin connection Figure 2. Pin connection (top view) #005 )7( )*/ 065 7$$ /$ -7( /$ $1 (/% $1 -*/ 4%0% %5 !-V Table 2. Pin description Pin n # Pin name Type Function 1 LIN I 2 SD/OD (1) I/O 3 HIN I High side driver logic input (active high) 4 VCC P Lower section supply voltage 5 DT I Dead time setting 6 NC 7 GND P Ground 8 CP- I Comparator negative input 9 CP+ I Comparator positive input 10 LVG (1) O Low side driver output 11 NC 12 OUT P High side (floating) common voltage 13 HVG (1) O High side driver output 14 BOOT P Bootstrapped supply voltage Low side driver logic input (active low) Shut down logic input (active low)/open drain comparator output Not connected Not connected 1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/21 Doc ID 17892 Rev 1 L6391 3 Truth table Truth table Table 3. Truth table Input Note: Output SD LIN HIN LVG HVG L X X L L H H L L L H L H L L H L L H L H H H L H X: don't care Doc ID 17892 Rev 1 5/21 Electrical data L6391 4 Electrical data 4.1 Absolute maximum ratings Table 4. Absolute maximum rating Value Symbol Parameter Unit Min Max Vcc Supply voltage -0.3 21 V Vout Output voltage Vboot - 21 Vboot + 0.3 V Vboot Bootstrap voltage -0.3 620 V Vhvg High side gate output voltage Vout - 0.3 Vboot + 0.3 V Vlvg Low side gate output voltage -0.3 Vcc + 0.3 V Vcp- Comparator negative input voltage -0.3 Vcc + 0.3 V Vcp+ Comparator positive input voltage -0.3 Vcc + 0.3 V Vi Logic input voltage -0.3 15 V VOD Open drain voltage -0.3 15 V Allowed output slew rate 50 V/ns Ptot Total power dissipation (TA = 25 °C) 800 mW TJ Junction temperature 150 °C Tstg Storage temperature 150 °C dVout/dt -50 Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 1 kV (human body model) 4.2 Thermal data Table 5. Symbol Rth(JA) 6/21 Thermal data Parameter Thermal resistance junction to ambient Doc ID 17892 Rev 1 SO-14 DIP-14 Unit 165 100 °C/W L6391 4.3 Electrical data Recommended operating conditions Table 6. Recommended operating conditions Symbol Pin Vcc 4 VBO (1) 14-12 Parameter Test condition Min Max Unit Supply voltage 12.5 20 V Floating supply voltage 12.4 20 V 580 V -9 (2) Vout 12 DC output voltage VCP- 8 Comparator negative input voltage VCP+ [ 2.5 V VCC (3) V VCP+ 9 Comparator positive input voltage VCP- [ 2.5 V VCC (3) V fsw Switching frequency HVG, LVG load CL = 1 nF 800 kHz TJ Junction temperature 125 °C -40 1. VBO = Vboot - Vout 2. LVG off. Vcc = 12.5 V Logic is operational if Vboot > 5 V 3. At least one of the comparator's input must be lower than 2.5 V to guarantee proper operation. Doc ID 17892 Rev 1 7/21 Electrical characteristics L6391 5 Electrical characteristics 5.1 AC operation Table 7. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) Symbol ton toff tsd Pin Parameter Test condition High/low side driver turn-on Vout = 0 V 1 vs 10 propagation delay Vboot = Vcc 3 vs 13 High/low side driver turn-off CL = 1 nF propagation delay Vi = 0 to 3.3 V 2 vs Shutdown to high/low side See Figure 3. 10, 13 driver propagation delay tisd Comparator triggering to Measured applying a voltage step from 0 high/low side driver turn-off V to 3.3 V to pin CP+; CP-=0.5 V propagation delay MT Delay matching, HS and LS turn-on/off DT 5 Matching dead time (2) MDT tr tf Dead time setting range (1) Typ Max Unit 50 125 200 ns 50 125 200 ns 50 125 200 ns 200 250 ns 30 ns RDT = 0Ω, CL = 1 nF 0.1 RDT = 37kΩ, CL = 1 nF, CDT = 100 nF 0.48 0.6 0.72 µs RDT = 136kΩ, CL = 1 nF, CDT = 100 nF 1.35 1.6 1.85 µs RDT = 260kΩ, CL = 1 nF, CDT = 100 nF 2.6 3.0 3.4 µs RDT = 0Ω, CL = 1 nF 80 ns RDT = 37kΩ, CL = 1 nF, CDT = 100 nF 120 ns RDT = 136kΩ, CL = 1 nF, CDT = 100 nF 250 ns RDT = 260kΩ, CL = 1 nF, CDT = 100 nF 400 ns 0.18 0.25 µs Rise time CL = 1 nF 75 120 ns Fall time CL = 1 nF 35 70 ns 10,13 1. See Figure 4 on page 9 2. MDT = | DTLH - DTHL | see Figure 5 on page 12 8/21 Min Doc ID 17892 Rev 1 L6391 Electrical characteristics Figure 3. Timing 50% LIN 50% tr tf 90% LVG 90% 10% 10% ton toff 50% HIN 50% tr tf 90% HVG 90% 10% 10% ton toff 50% SD tf 90% LVG/HVG 10% tsd Typical dead time vs. DT resistor value $SSUR[LPDWHGIRUPXODIRU 5GWFDOFXODWLRQW\S '7XV Figure 4. 5GW>Nȍ@ Â'7>V@ 5GWN2KP Doc ID 17892 Rev 1 9/21 Electrical characteristics L6391 5.2 DC operation Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) Symbol Pin Min Typ Max Unit Vcc UV hysteresis 1.2 1.5 1.8 V Vcc_thON Vcc UV turn ON threshold 11.5 12 12.5 V Vcc_thOFF Vcc UV turn OFF threshold 10 10.5 11 V Undervoltage quiescent supply current Vcc = 9.5 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 Ω; CP+=GND; CP-=5 V 100 150 μA Quiescent current Vcc = 15 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 Ω; CP+=GND; CP-=5 V 500 1000 μA Vcc_hys Iqccu 4 Iqcc Parameter Test condition Bootstrapped supply voltage section (1) VBO_hys VBO UV hysteresis 1.2 1.5 1.8 V VBO_thON VBO UV turn ON threshold 10.6 11.5 12.4 V VBO_thOFF VBO UV turn OFF threshold 9.1 10 10.9 V IQBOU VBO = 9 V SD = 5 V; LIN and Undervoltage VBO quiescent HIN = 5 V; 14-12 current RDT = 0 Ω; CP+=GND; CP-=5 V 70 110 μA IQBO VBO = 15 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 Ω; CP+=GND; CP-=5 V 200 VBO quiescent current High voltage leakage current Vhvg = Vout = Vboot = 600 V ILK Bootstrap driver on resistance (2) RDS(on) μA 10 LVG ON μA 120 Ω Driving buffers section Iso Isi 10/21 10, 13 High/low side source short circuit current VIN = Vih (tp < 10 μs) 200 290 mA High/low side sink short circuit current VIN = Vil (tp < 10 μs) 250 430 mA Doc ID 17892 Rev 1 L6391 Electrical characteristics Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued) Symbol Pin Parameter Test condition Min Typ Max Unit 0.8 V Logic inputs Vil Low logic level voltage 1, 2, 3 Vih High logic level voltage Single input voltage LIN and HIN connected together and floating HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “0” input bias current LIN = 0 V ILINh LIN logic “1” input bias current LIN = 15 V ISDh SD logic “1” input bias current SD = 15 V SD logic “0” input bias current SD = 0 V Vil_S 1, 3 2.25 IHINh 110 V 175 0.8 V 260 μA 1 μA 20 μA 1 μA 100 μA 1 μA Max Unit 15 mV 1 μA 0.5 V 130 ns 3 3 6 1 10 40 2 ISDl 1. VBO = Vboot - Vout 2. RDSON is tested in the following way: RDSON = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. Table 9. Sense comparator (VCC = 15 V, TJ = +25 °C) Symbol Pin Vio 8, 9 Input offset voltage Iib 8, 9 Input bias current VCP+ = 1 V, VCP- = 0.5 V Vol 2 Open drain low level output voltage Iod = - 3 mA VCP+=1V; VCP-=0.5V; Comparator delay Rpull=100 kΩ to 5 V on SD/OD pin; VCP-=0.5V; voltage step on CP+ = 0 ÷ 3.3V, 90 Slew rate CL = 180 pF; Rpu = 5 kΩ 60 td_comp SR 2 Parameter Test conditions Min Typ -15 Doc ID 17892 Rev 1 V/μs 11/21 Waveforms definitions L6391 6 Waveforms definitions Figure 5. Dead time and interlocking waveforms definitions INTE R LOC KING HIN INTE R CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME LOC KING LIN LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected togheter and driven by just one control signal 12/21 Doc ID 17892 Rev 1 gate driver outputs OFF (HALF-BRIDGE TRI-STATE) L6391 7 Smart shut down function Smart shut down function L6391 integrates a comparator committed to the fault sensing function. The comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function. The output signal of the comparator is fed to an integrated MOSFET with the open drain output available on pin 2, shared with the SD input. When the comparator triggers, the device is set in shut down state and both its outputs are set to low level leaving the halfbridge in tri-state. Figure 6. Smart shut down timing waveforms CP- CP+ PROTECTION HIN/LIN HVG/LVG SD/OD upper threshold lower threshold 1 2 open drain gate (internal) real disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold TIME CONSTANTS 1 = (RON_OD // RSD) 2 = RSD CSD CSD SHUT DOWN CIRCUIT VBIAS RSD FROM/TO CONTROLLER SD/OD CSD Doc ID 17892 Rev 1 RON_OD SMART SD LOGIC 13/21 Smart shut down function L6391 In common over-current protection architectures the comparator output is usually connected to the SD input and an RC network is connected to this SD/OD line in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Differently from the common fault detection systems, L6391 Smart shut down architecture allows to immediately turn-off the outputs gate driver in case of fault, by minimizing the propagation delay between the fault detection event and the actual outputs switch-off. In fact the time delay between the fault and the outputs turn off is no more dependent on the RC value of the external network connected to the pin. In the smart shut down circuitry, the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. At the same time the internal logic turns on the open drain output and holds it on until the SD voltage goes below the SD logic input lower threshold. The Smart shut down system provides the possibility to increase the time constant of the external RC network (that is the disable time after the fault event) up to very large values without increasing the delay time of the protection. Any external signal provided to the SD pin is not latched and can be used as control signal in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal is applied to the SD input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa. 14/21 Doc ID 17892 Rev 1 Doc ID 17892 Rev 1 '30.50 $0/530--&3 %5 (/% 4%0% -*/ '30.$0/530--&3 7#*"4 )*/ '30.$0/530--&3 7$$ 7 67 %&5&$5*0/ 4."35 4% GSPN-7( 5*.& %&"% 4)005 5)306() 13&7&/5*0/ -0(*$ #005453"1%3*7&3 $0.1"3"503 -&7&4)*'5&3 7 67 %&5&$5*0/ '-0"5*/(4536$563& 3 4 7$$ -7( %3*7&3 )7( %3*7&3 $1 $1 -7( 065 )7( #005 7#*"4 )7 50-0"% $CPPU Figure 7. 7$$ 8 L6391 Typical application diagram Typical application diagram Application diagram !-V 15/21 Bootstrap driver 9 L6391 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 8). In the L6391 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 9. An internal charge pump (Figure 9) provides the DMOS driving voltage. 9.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1 Q gate C EXT = ------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: Equation 2 CBOOT >>> CEXT e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 200 μA, so if HVG TON is 5 ms, CBOOT has to supply 1 μC to CEXT. This charge on a 1 μF capacitor means a voltage drop of 1V. The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value: 120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. 16/21 Doc ID 17892 Rev 1 L6391 Bootstrap driver The following equation is useful to compute the drop on the bootstrap DMOS: Equation 3 Q gate V drop = I ch arg e R dson → V drop = ------------------ R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 μs. In fact: Equation 4 30nC V drop = --------------- ⋅ 120Ω ∼ 0.7V 5μs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 8. Bootstrap driver with high voltage fast recovery diode DBOOT VCC BOOT H.V. HVG CBOOT OUT TO LOAD LVG Figure 9. Bootstrap driver with internal charge pump BOOT VCC H.V. HVG CBOOT OUT TO LOAD LVG b Doc ID 17892 Rev 1 17/21 Package mechanical data 10 L6391 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 10. DIP-14 mechanical data mm. inch Dim. Min a1 0.51 B 1.39 Typ Max Typ Max 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z 3.3 1.27 0.130 2.54 Figure 10. Package dimensions 18/21 Min Doc ID 17892 Rev 1 0.050 0.100 L6391 Package mechanical data Table 11. SO-14 mechanical data mm. inch Dim. Min Typ A a1 Max Min Typ 1.75 0.1 0.2 a2 Max 0.068 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.68 S 0.026 8° (max.) Figure 11. Package dimensions Doc ID 17892 Rev 1 19/21 Revision history 11 L6391 Revision history Table 12. 20/21 Document revision history Date Revision 14-Dec-2010 1 Changes First release Doc ID 17892 Rev 1 L6391 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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