L6387E High-voltage high and low side driver Features ■ High voltage rail up to 600V ■ dV/dt immunity ±50V/nsec in full temperature range ■ Driver current capability: – 400mA source, – 650mA sink Switching times 50/30 nsec rise/fall with 1nF load ■ CMOS/TTL Schmitt trigger inputs with hysteresis and pull down ■ Internal bootstrap diode ■ Outputs in phase with inputs ■ Interlocking function The L6387E is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has a Driver structure that enables to drive independent referenced N Channel Power MOS or IGBT. The high side (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. Block diagram BOOTSTRAP DRIVER VCC 3 8 2 HVG DRIVER LOGIC LEVEL SHIFTER Cboot HVG 7 S OUT VCC LIN Vboot H.V. UV DETECTION R HIN SO-8 Description ■ Figure 1. DIP-8 1 LVG DRIVER 6 TO LOAD 5 LVG 4 GND D00IN1135 October 2007 Rev 1 1/15 www.st.com 15 Contents L6387E Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Input logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 L6387E Electrical data 1 Electrical data 1.1 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit Vout Output voltage -3 to Vboot -18 V Vcc Supply voltage - 0.3 to +18 V Vboot Floating supply voltage -1 to 618 V Vhvg High side gate output voltage -1 to Vboot V Vlvg Low side gate output voltage -0.3 to Vcc +0.3 V Logic input voltage -0.3 to Vcc +0.3 V Allowed output slew rate 50 V/ns Total power dissipation (TJ = 85 °C) 750 mW Tj Junction temperature 150 °C Ts Storage temperature -50 to 150 °C Vi dVout/dt Ptot Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model) 1.2 Thermal data Table 2. Thermal data Symbol Rth(JA) 1.3 Parameter Thermal Resistance Junction to ambient SO-8 DIP-8 Unit 150 100 °C/W Recommended operating conditions Table 3. Recommended operating conditions Symbol Pin Vout 6 VBS (2) 8 TJ 3 Test condition Min Typ Max Unit Output voltage (1) 580 V Floating supply voltage (1) 17 V 400 kHz 17 V 125 °C Switching frequency fsw Vcc Parameter HVG,LVG load CL = 1nF Supply voltage Junction temperature -45 1. If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V 2. VBS = Vboot - Vout 3/15 Pin connection 2 L6387E Pin connection Figure 2. Pin connection (Top view) LIN 1 8 Vboot HIN 2 7 HVG VCC 3 6 OUT GND 4 5 LVG D97IN517A Table 4. Pin description N° Pin Type Function 1 LIN I Low side driver logic input 2 HIN I High side driver logic input 3 Vcc 4 GND 5 LVG (1) O Low side driver output 6 VOUT O High side driver floating reference 7 HVG (1) O High side driver output 8 Vboot Low voltage power supply Ground Bootstrap supply voltage 1. The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. 4/15 L6387E Electrical characteristics 3 Electrical characteristics 3.1 AC operation Table 5. Symbol 3.2 AC operation electrical characteristcs (VCC = 15V; TJ = 25°C) Pin Parameter Test condition Min Typ Max Unit ton 1 vs 5 High/low side driver turn-on 2 vs 7 propagation delay Vout = 0V 110 ns toff 1 vs 5 High/low side driver turn-off 2 vs 7 propagation delay Vout = 0V 105 ns tr 5, 7 Rise time CL = 1000pF 50 ns tf 5, 7 Fall time CL = 1000pF 30 ns DC operation Table 6. Symbol DC operation electrical characteristcs (VCC = 15V; TJ = 25°C) Pin Parameter Test condition Min Typ Max Unit 17 V Low supply voltage section Vcc Supply voltage Vccth1 Vcc UV turn on threshold 5.5 6 6.5 V Vccth2 Vcc UV turn off threshold 5 5.5 6 V Vcchys Vcc UV hysteresis 3 0.5 V Iqccu Undervoltage quiescent supply current Vcc ≤ 9V 150 220 µA Iqcc Quiescent current Vcc = 15V 250 320 µA Rdson Bootstrap driver on resistance(1) Vcc ≥ 12.5V 125 Ω Bootstrapped supply voltage section VBS IQBS Bootstrap supply voltage 8 ILK VBS quiescent current High voltage leakage current 17 V HVG ON 100 µA Vhvg = Vout = Vboot = 600V 10 µA High/low side driver Iso Isi Source short circuit current VIN = Vih (tp < 10µs) 300 400 mA Sink short circuit current VIN = Vil (tp < 10µs) 450 650 mA 5,7 5/15 Input logic L6387E Table 6. Symbol DC operation electrical characteristcs (continued)(VCC = 15V; TJ = 25°C) Pin Parameter Test condition Min Typ Max Unit 1.5 V Logic inputs Low level logic threshold voltage Vil Vih 1,2 High level logic threshold voltage 3.6 Iih High level logic input current VIN = 15V Iil Low level logic input current VIN = 0V V 50 70 mA 1 mA 1. RDS(on) is tested in the following way: ( V CC – V CBOOT1 ) – ( V CC – V CBOOT2 ) R DSON = -----------------------------------------------------------------------------------------------------I 1 ( V CC ,V CBOOT1 ) – I 2 ( V CC ,V CBOOT2 ) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 4 Input logic L6387E Input Logic is VCC (17V) compatible. An interlocking features is offered (see truth table below) to avoid undesired simultaneous turn ON of both Power Switches driven. Table 7. Input logic HIN 0 0 1 1 LIN 0 1 0 1 HVG 0 0 1 0 LVG 0 1 0 0 Input Output 6/15 L6387E 5 Bootstrap driver Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 3 a). In the L6387E a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 3 b. An internal charge pump (Figure 3 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. 5.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Q gate C EXT = -------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to supply 1µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson → V drop = ------------------- R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. 7/15 Bootstrap driver L6387E For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5µs. In fact: 30nC V drop = --------------- ⋅ 125Ω ∼ 0.8V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 3. Bootstrap driver DBOOT VS VBOOT H.V. HVG CBOOT VOUT TO LOAD LVG a VBOOT VS H.V. HVG CBOOT VOUT TO LOAD LVG b 8/15 D99IN1056 L6387E Typical characteristic Figure 4. Typical rise and fall times vs load capacitance time (nsec) D99IN1054 250 Figure 5. Quiescent current vs supply voltage Iq (µA) 104 D99IN1055 200 Tr 103 150 Tf 100 102 50 0 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25˚C Tamb Figure 6. Turn on time vs temperature Figure 7. 4 6 8 10 12 14 16 VS(V) Turn Off time vs temperature 250 @ Vcc = 15V @ Vcc = 15V 200 200 150 Toff (ns) Ton (ns) 2 0 250 Typ. 100 50 150 Typ. 100 50 0 -45 Figure 8. -25 0 25 50 Tj (°C) 75 100 0 125 Output source current vs temperature -45 Figure 9. -25 0 25 50 Tj (°C) 75 100 125 Output sink current vs temperature 1000 1000 @ Vcc = 15V @ Vcc = 15V 800 current (mA) 800 current (mA) 6 Typical characteristic 600 Typ. 400 200 600 Typ. 400 200 0 0 -45 -25 0 25 50 Tj (°C) 75 100 125 -45 -25 0 25 50 Tj (°C) 75 100 125 9/15 Package mechanical data 7 L6387E Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 10/15 L6387E Package mechanical data Figure 10. DIP-8 mechanical data and package dimensions mm inch DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 DIP-8 0.060 11/15 Package mechanical data L6387E Figure 11. SO-8 mechanical data and package dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.750 MAX. 0.0689 A1 0.100 0.250 0.0039 A2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 D (1) E (2) E1 0.0098 4.800 4.900 5.000 0.1890 0.1929 0.1969 5.800 6.000 6.200 0.2283 0.2362 0.2441 3.900 4.000 0.1496 0.1535 0.1575 3.800 e 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 L 0.400 1.270 0.0157 0.0500 L1 k ccc 1.040 0˚ OUTLINE AND MECHANICAL DATA 0.0409 8˚ 0.100 0˚ 8˚ 0.0039 Notes: 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. SO-8 0016023 D 12/15 L6387E 8 Order codes Order codes Table 8. Order codes Part number Package Packaging L6387E DIP-8 Tube L6387ED SO-8 Tube L6387ED013TR SO-8 Tape and reel 13/15 Revision history 9 L6387E Revision history Table 9. 14/15 Document revision history Date Revision 11-Oct-2007 1 Changes First release L6387E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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