L6384E High-voltage half bridge driver Features ■ High voltage rail up to 600V ■ dV/dt immunity ±50V/nsec in full temperature range ■ Driver current capability: – 400mA source, – 650mA sink SO-8 Description ■ Switching times 50/30 nsec rise/fall with 1nF load ■ CMOS/TTL Schmitt trigger inputs with hysteresis and pull down ■ Shut down input ■ Dead time setting ■ Under voltage lock out ■ Integrated bootstrap diode ■ Clamping on VCC ■ SO-8/DIP-8 packages Figure 1. DIP-8 The L6384E is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has an Half - Bridge Driver structure that enables to drive N-channel Power MOS or IGBT. The High Side (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. Matched delays between Low and High Side Section simplify high frequency operation. Dead time setting can be readily accomplished by means of an external resistor. Block diagram H.V. VCC 2 8 VBOOT BOOTSTRAP DRIVER HVG DRIVER UV DETECTION R IN 1 7 OUT LOGIC LEVEL SHIFTER VCC Idt DEAD TIME LVG DRIVER DT/SD 3 S CBOOT HVG VCC 6 5 LVG 4 GND LOAD Vthi D97IN518A October 2007 Rev 1 1/17 www.st.com 17 Contents L6384E Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 3.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 L6384E Electrical data 1 Electrical data 1.1 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol Vout Vcc Is Parameter Output voltage Value Unit -3 to Vboot -18 V Supply voltage (1) - 0.3 to 14.6 V Supply current (1) 25 mA Vboot Floating supply voltage -1 to 618 V Vhvg High side gate output voltage -1 to Vboot V Vlvg Low side gate output voltage -0.3 to Vcc +0.3 V Logic input voltage -0.3 to Vcc +0.3 V Shut down/dead time voltage -0.3 to Vcc +0.3 V Allowed output slew rate 50 V/ns Ptot Total power dissipation (Tj = 85 °C) 750 mW TJ Junction temperature 150 °C Ts Storage temperature -50 to 150 °C Vi Vsd dVout/dt 1. The device has an internal Clamping Zener between GND and the Vcc pin, It must not be supplied by a Low Impedence Voltage Source. Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model) 1.2 Thermal data Table 2. Symbol Rth(JA) Thermal data Parameter Thermal Resistance Junction to ambient SO-8 DIP-8 Unit 150 100 °C/W 3/17 Electrical data 1.3 L6384E Recommended operating conditions Table 3. Recommended operating conditions Symbol Pin Vout 6 VBS (2) 8 Tj 2 Test condition Min Max Unit (1) 580 V Floating Supply Voltage (1) 17 V 400 kHz Vclamp V 125 °C HVG,LVG load CL = 1nF Supply Voltage Junction Temperature -45 1. If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V. 2. VBS = Vboot - Vout 4/17 Typ Output Voltage Switching Frequency fsw Vcc Parameter L6384E 2 Pin connection Pin connection Figure 2. Pin connection (Top view) IN 1 8 VBOOT VCC 2 7 HVG DT/SD 3 6 VOUT GND 4 5 LVG D97IN519 Table 4. Pin description N° Pin Type Function 1 IN I Logic Input: it is in phase with HVG and in opposition of phase with LVG. It is compatible to VCC voltage. [Vil Max = 1.5V, Vih Min = 3.6V] 2 Vcc Supply input voltage: there is an internal clamp [Typ. 15.6V] 3 DT/SD 4 GND Ground 5 LVG O Low Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max on the pin (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. 6 Vout O High Side Driver Floating Reference: layout care has to be taken to avoid below ground spikes on this pin. O High Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit gurantees 0.3V max between this pin and Vout (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. 7 8 HVG Vboot I High impedance pin with two functionalities. When pulled lower than Vdt [Typ. 0.5V] the device is shut down. A voltage higher than Vdt sets the dead time between high side gate driver and low side gate driver. The dead time value can be set forcing a certain voltage level on the pin or connecting a resistor between pin 3 and ground. Care must be taken to avoid below threshold spikes on pin 3 that can cause undesired shut down of the IC. For this reason the connection of the components between pin 3 and ground has to be as short as possible. This pin can not be left floating for the same reason. The pin has not be pulled through a low impedance to VCC, because of the drop on the current source that feeds Rdt. The operative range is: Vdt....270K ⋅ Idt, that allows a dt range of 0.4 - 3.1µs. Bootstrap Supply Voltage: it is the high side driver floating supply. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named "bootstrap driver" (a patented structure). This structure can replace the external bootstrap diode. 5/17 Electrical characteristics L6384E 3 Electrical characteristics 3.1 AC operation Table 5. Symbol 3.2 AC operation electrical characteristcs (VCC = 14.4V; TJ = 25°C) Pin Parameter ton 1 vs High/low side driver turn-on 5,7 propagation delay tonsd 3 vs Shut down input propagation 5,7 delay toff 1 vs High/low side driver turn-off 5,7 propagation delay Test condition Min Typ Max 200+ dt Vout = 0V Rdt= 47kΩ Unit ns 220 280 ns Vout = 0V Rdt = 47kΩ 250 300 ns Vout = 0V Rdt = 146kΩ 200 250 ns Vout = 0V Rdt = 270kΩ 170 200 ns tr 5,7 Rise time CL = 1000pF 50 ns tf 5,7 Fall time CL = 1000pF 30 ns DC operation Table 6. Symbol DC operation electrical characteristcs (VCC = 14.4V; TJ = 25°C) Pin Parameter Test condition Min Typ Max Unit 14.6 15.6 16.6 V Supply voltage section Vclamp 2 Supply voltage clamping Vccth1 2 VCC UV turn on threshold 11.5 12 12.5 V VCC UV turn off threshold 9.5 10 10.5 V Vccth2 Is = 5mA VCC UV Hysteresis Vcchys 2 2 V µA Iqccu Undervoltage quiescent supply current Vcc ≤ 11V 150 Iqcc Quiescent current Vin = 0 380 500 µA 17 V Bootstrapped supply voltage section Vboot Bootstrap supply voltage IQBS Quiescent current IN = HIGH 200 µA High voltage leakage current Vhvg = Vout = Vboot = 600V 10 µA Bootstrap driver on resistance (1) Vcc ≥12.5V; IN = LOW ILK Rdson 6/17 8 125 Ω L6384E Electrical characteristics Table 6. Symbol DC operation electrical characteristcs (continued)(VCC = 14.4V; TJ = 25°C) Pin Parameter Test condition Min Typ Max Unit High/Low side driver Iso Source short circuit current VIN = Vih (tp < 10µs) 300 400 mA Sink short circuit current VIN = Vil (tp < 10µs) 500 650 mA 5,7 Isi Logic inputs Low level logic threshold voltage Vil Vih 1,3 1.5 High level logic threshold voltage 3.6 Iih High level logic input current VIN = 15V Iil Low level logic input current Iref dt Vdt 3 3 vs Dead time setting range (2) 5,7 3 V 50 VIN = 0V Dead time setting current Rdt = 47kΩ Rdt = 146kΩ Rdt = 270kΩ 0.4 Shutdown threshold V 70 µA 1 µA 28 µA 0.5 1.5 2.7 µs µs µs 3.1 0.5 V 1. RDS(on) is tested in the following way: ( V CC – V CBOOT1 ) – ( V CC – V CBOOT2 ) R DSON = -----------------------------------------------------------------------------------------------------I 1 ( V CC ,V CBOOT1 ) – I 2 ( V CC ,V CBOOT2 ) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 2. Pin 3 is a high impedence pin. Therefore dt can be set also forcing a certain voltage V3 on this pin. The dead time is the same obtained with a Rdt if it is: Rdt × Iref = V3. 3.3 Timing diagram Figure 3. Input/output timing diagram IN SD HVG LVG D99IN1017 7/17 Bootstrap driver 4 L6384E Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6384E a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. 4.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Q gate C EXT = -------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to supply 1µC to CEXT. This charge on a 1µF capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson → V drop = ------------------- R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. 8/17 L6384E Bootstrap driver For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5µs. In fact: 30nC V drop = --------------- ⋅ 125Ω ∼ 0.8V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 4. Bootstrap driver DBOOT VS VBOOT VBOOT VS H.V. H.V. HVG HVG CBOOT VOUT TO LOAD TO LOAD LVG a CBOOT VOUT LVG b D99IN1067 9/17 Typical characteristic 5 L6384E Typical characteristic Figure 5. Typical rise and fall times vs load capacitance time (nsec) D99IN1015 250 Figure 6. Quiescent current vs supply voltage Iq (µA) 104 D99IN1016 200 Tr 103 150 Tf 100 102 50 0 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25˚C Tamb Figure 7. Dead time vs resistance 0 2 Figure 8. 4 6 8 10 12 14 VS(V) Driver propagation delay vs temperature 400 3.5 @ Vcc = 14.4V @ Vcc = 14.4V 3.0 300 Ton,Toff (ns) dt (µs) 2.5 2.0 Typ. 1.5 1.0 @ Rdt = 47kOhm Typ. 200 100 Typ. @ Rdt = 270kOhm Typ. @ Rdt = 146kOhm 0.5 0.0 50 Figure 9. 100 150 200 Rdt (kΩ) 250 0 300 Dead time vs temperature -45 0 25 50 Tj (°C) 75 100 125 Figure 10. Shutdown threshold vs temperature 1 3 2.5 -25 Typ. R=270K 0.8 @ Vcc = 14.4V @ Vcc = 14.4V 0.6 Vdt (V) dt (µs) 2 1.5 Typ. R=146K Typ. R=47K 1 Typ. 0.2 0.5 0 -45 -25 0 25 50 Tj (°C) 10/17 0.4 75 100 125 0 -45 -25 0 25 50 Tj (°C) 75 100 125 L6384E Typical characteristic Figure 11. Vcc UV turn On vs temperature Figure 12. Output source current vs temperature 1000 15 800 Current (mA) Vccth1 (V) 14 13 12 Typ. 11 @ Vcc = 14.4V 600 Typ. 400 200 10 -45 -25 0 25 50 Tj (°C) 75 100 0 -45 125 Figure 13. Vcc UV turn Off vs temperature -25 0 25 50 Tj (°C) 75 100 125 Figure 14. Output sink current vs temperature 13 1000 12 800 Current (mA) Vccth2 (V) @ Vcc = 14.4V 11 10 Typ. 9 Typ. 600 400 200 8 0 -45 -25 0 25 50 Tj (°C) 75 100 125 -45 -25 0 25 50 Tj (°C) 75 100 125 11/17 Package mechanical data 6 L6384E Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 12/17 L6384E Package mechanical data Figure 15. DIP-8 mechanical data and package dimensions mm inch DIM. MIN. A TYP. MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 DIP-8 0.060 13/17 Package mechanical data L6384E Figure 16. SO-8 mechanical data and package dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 1.750 MAX. 0.0689 A1 0.100 0.250 0.0039 A2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.0098 0.230 0.0067 0.0091 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(2) 3.800 3.900 4.000 0.1496 0.1535 0.1575 D (1) e 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 L 0.400 1.270 0.0157 0.0500 L1 k ccc 1.040 0˚ OUTLINE AND MECHANICAL DATA 0.0409 8˚ 0.100 0˚ 8˚ 0.0039 Notes: 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. SO-8 0016023 D 14/17 L6384E 7 Order codes Order codes Table 7. Order codes Part number Package Packaging L6384E DIP-8 Tube L6384ED SO-8 Tube L6384ED013TR SO-8 Tape and reel 15/17 Revision history 8 L6384E Revision history Table 8. 16/17 Document revision history Date Revision 12-Oct-2007 1 Changes First release L6384E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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