PRM48BH480 X 250A00 PRM™ Regulator FEATURES 48V input (38V to 55V), non‐isolated ZVS buck‐boost regulator 20V to 55V adjustable output range 250W output power in 0.57in2 footprint 96.7% typical efficiency, at full load 1670 W/in3 (102 W/cm3) Power Density 5.28 MHrs MTBF (MIL‐HDBK‐217Plus Parts Count) Pin selectable operating mode Adaptive Loop Remote Sense / Slave Half VIChip Package 22.0mm x 16.5mm x 6.73mm TYPICAL APPLICATIONS PRODUCT RATINGS High Density Power Supply DC-DC rail outputs High Density ATE system DC-DC power Telecom NPU and ASIC core power Communications Systems Non-isolated and isolated power converters VIN = 38V to 55V POUT = 250W VOUT= 48V (20V to 55V Trim) IOUT = 5.21A DESCRIPTION The VIChip™ PRM™ Regulator is a high efficiency converter, operating from a 38 to 55 Vdc input to generate a regulated 20 to 55 Vdc output. The ZVS buck – boost topology enables high switching frequency (~1.03 MHz) operation with high conversion efficiency. High switching frequency reduces the size of reactive components enabling power density up to 1670 W/in3. The Half VIChip package is compatible with standard pick-and-place and surface mount assembly processes with a planar thermal interface area and superior thermal conductivity. In a Factorized Power Architecture™ system, the PRM and downstream VTM™ current multiplier minimize distribution and conversion losses in a high power solution, providing an isolated, regulated output voltage. The PRM48BH480[x]250A00 has two selectable modes of regulation depending on the application requirements. In Adaptive Loop operation, the PRM48BH480[x]250A00 utilizes a unique feed-forward scheme that enables precise regulation of an isolated POL voltage without the need for remote sensing and voltage feedback. In Remote Sense operation, the internal regulation circuitry is disabled, and an external control loop and current sensor maintain regulation. This affords flexibility in the design of both voltage and current compensation loops to optimize performance in the end application. -1- Rev. 1.0 11/2012 PRM48BH480 X 250A00 TYPICAL APPLICATIONS PRM ENABLE ON/OFF CONTROL VAUX SGND RTRIM RAL VTM REF/ REF_EN TRIM AL VC SHARE/ CONTROL NODE VT VOUT VTM Startup Pulse VC Adaptive Loop Temperature Feedback TM PC IFB VINVIN 38V36V to 55V to 75V +OUT COUT SGND +IN +OUT -IN -OUT +IN LF VF: 20V to 55V CIN CF SGND -OUT -IN PRIMARY GND SECONDARY SEC_GND ISOLATION BOUNDRY SGND Typical Application: PRM48BH480[x]250A00 + VTM Adaptive Loop Configuration Voltage Sense VREF IN OUT SGND VOLTAGE SENSE AND ERROR AMPLIFIER (SINGLE ENDED) GND PRM ENABLE VAUX REF/ REF_EN TRIM ON/OFF CONTROL SGND SGND AL VC SHARE/ CONTROL NODE VT SGND VOLTAGE REFERENCE WITH SOFT START +IN SGND +IN LF -OUT COUT SGND External Current Sense and Feedback -IN GND VOUT PC -IN +OUT CIN +OUT V- VOUT +IN VIN VIN 38V to 55V 36V to 75V VC TM V+ IFB VTM VTM Startup Pulse CF -OUT -IN PRIMARY [1] SECONDARY ISOLATION BOUNDRY [1] GND SGND Typical Application: PRM48BH480[x]250A00 + VTM non-Isolated Remote Sense Configuration [1] Non-Isolated Configuration: –Out connected to -IN -2- Rev. 1.0 11/2012 PRM48BH480 X 250A00 PIN CONFIGURATION PIN DESCRIPTIONS Pin Signal Name Type SHARE (Adaptive Loop / Slave operation) BIDIR Parallel sharing control bus for master-Slave configuration. CONTROL NODE (Remote Sense operation) INPUT Modulator control node input. Driven by external error amplifier in Remote Sense operation. A3 VT (Adaptive Loop operation) INPUT VTM TM input for temperature compensation. Leave disconnected for Remote Sense operation. B2 ENABLE BIDIR Enables power supply when allowed to float high. 5.0V during normal operation. B4 VAUX OUTPUT C1 TRIM INPUT Selects operating mode. Adjusts output voltage in Adaptive Loop operation. C3 IFB (Remote Sense operation) INPUT Current sense input for current limit and overcurrent protection in Remote Sense operation. Leave disconnected for Adaptive Loop operation. D2 NC n/a D4 SGND INPUT NC n/a REF (Adaptive Loop operation) Number A1 E1 Function 9.0V auxiliary bias voltage. Do not connect this pin. Signal ground, reference for analog controls. Kelvin connected internally to –IN and -OUT. Do not connect this pin. OUTPUT Reference voltage for internal error amplifier in Adaptive Loop operation. REF_EN (Remote Sense operation) OUTPUT Powers and enables external control circuit voltage reference in Remote Sense operation. F2 AL (Adaptive Loop operation) INPUT Adaptive Loop gain control. Sets the magnitude of the Adaptive Loop load line in Adaptive Loop operation. Leave disconnected for Remote Sense operation. F4 VC OUTPUT Bias voltage to power VTM module during start up G1,G2 +IN INPUT POWER Positive input power terminal G3,G4 +OUT OUTPUT POWER Positive output power terminal H1,H2 -IN INPUT POWER RETURN Negative input power terminal. Connected internally to –OUT. H3,H4 -OUT OUTPUT POWER RETURN Negative output power terminal. Connected internally to -IN. E3 -3- Rev. 1.0 11/2012 PRM48BH480 X 250A00 PART ORDERING INFORMATION PART ORDERING INFORMATION Device Type Input Voltage Range Package Type Output Voltage x 10 Temperature Grade Output Power Revision Version PRM 48B H 480 T 250 A 00 PRM = PRM 48B = 38V – 55V H = Half VIC SMD 480 = 48V T = -40 to 125 °C M = -55 to 125 °C 250 = 250W A 00 = AL / RS STANDARD MODELS PART NUMBER PRM48BH480T250A00 PRM48BH480M250A00 VIN PACKAGE TYPE VOUT TEMPERATURE 38V – 55V Half VIC SMD 48V (20V to 55V) -55 to 125 °C -4- -40 to 125 °C POWER VERSION 250W AL / RS (Pin Selectable) Rev. 1.0 11/2012 PRM48BH480 X 250A00 ABSOLUTE MAXIMUM RATINGS The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. Operating beyond rated operating conditions for extended period of time may affect device reliability. All voltages are specified relative to SGND unless otherwise noted. Positive pin current represents current flowing out of the pin. ABSOLUTE MAXIMUM RATINGS Parameter Comments SHARE / CONTROL NODE ………………………………………………………………………........................................................................................................................................... ENABLE ………………………………………………………………………........................................................................................................................................... Min Max Unit -0.3 10.5 V +/- 10 mA -0.3 +IN to –IN Continuous, non-Operating ............................................................................................................................................................................................... -1 100ms, non-Operating ....................................................................................................................................................................................................... -0.5 VAUX 5.5 V +/- 10 mA 80 V 100 V 10.5 V +/- 100 mA +/- 100 mA ……………………………………………………………………….......................................................................................................................................... SGND ……………………………………………………………………….......................................................................................................................................... IFB ……………………………………………………………………….......................................................................................................................................... -0.5 5.7 V ……………………………………………………………………….......................................................................................................................................... -0.3 3.6 V Remote Sense Operation .................................................................................................................................................................................................. 10 mA Adaptive Loop Operation ................................................................................................................................................................................................... 3.4 mA REF / REF_EN TRIM ………………………………………………………………………........................................................................................................................................... -0.3 3.6 V AL ………………………………………………………………………........................................................................................................................................... -0.3 3.6 V VT ………………………………………………………………………........................................................................................................................................... -0.3 4.8 V -0.5 18 V VC to –OUT ………………………………………………………………………........................................................................................................................................... +/- 1.8 A +OUT to –OUT ………………………………………………………………………........................................................................................................................................... Output Current ………………………………………………………………………........................................................................................................................................... Internal Operating Temperature Storage Temperature -1 62 V 7.3 A TGrade……………………………………………………........................................................................................................................................................ -40 125 ºC M Grade …………………………………………………....................................................................................................................................................... -55 125 ºC T Grade …………………………………………………........................................................................................................................................................ -40 125 ºC M Grade …………………………………………………........................................................................................................................................................ -65 125 ºC -5- Rev. 1.0 11/2012 PRM48BH480 X 250A00 ELECTRICAL SPECIFICATIONS ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions, and trim from 20 V to 55 V, unless otherwise noted; Boldface specifications apply over the temperature range of -40ºC < TINT < 125ºC; All Other specifications are at TINT = 25ºC unless otherwise noted. Attribute Symbol Conditions / Notes Min Typ 38 48 Max Unit POWER INPUT SPECIFICATION Input Voltage Range VIN Slew Rate VIN dVIN/dt Continuous, operating 0 ≤ VIN ≤ 55V 0.001 55 V 1000 V/ms Initialization Voltage VINIT Internal micro controller initialization voltage 10 Initialization Delay tINIT From VIN first crossing VINIT 7.0 9.0 No Load Power Dissipation PNL ENABLE HIGH, VIN = 48 V 2.4 3.5 W Input Quiescent Current IQC ENABLE LOW, VIN = 48V 14.5 20 mA 5.4 5.6 5.0 V ms Input Current IIN_DC IOUT = 5.21A, VIN =48 V, VOUT = 48 V Input Capacitance (Internal) CIN_INT Effective value, VIN = 48 V (see Fig. 13) 2 F A 3 mΩ Input Capacitance (Internal) ESR RCIN Effective value, VIN =48 V Output Current IOUT Standalone and Master operation, see Figure 1, SOA 5.21 A Output Power POUT Standalone and Master operation, see Figure 1, SOA 250 W Switching Frequency FSW 1.065 MHz 1.065 MHz POWER OUTPUT SPECIFICATION Turn-ON Delay Startup Sequence Timeout Efficiency Ambient Efficiency Hot Efficiency Over Temperature Output Discharge current tON tSTARTUP_SEQ ηAMB ηHOT η IOD VIN = 48V VOUT = 48V, IOUT = 2.61A, TINT = 25°C 0.935 Over line, load, trim and temperature, exclusive of burst mode 0.70 From VIN first crossing VIN_UVLO+_SUPV to ENABLE high; tINIT expired From ENABLE released to ENABLE high, VIN applied, tOFF, and tiNIT expired From ENABLE high to startup sequence complete 1.03 20 µs 17 ms VIN = 48V, VOUT = 48V, IOUT = 5.21A, TINT = 25°C 95.7 96.7 % VIN = 48V, VOUT = 48V, IOUT = 2.61A, TINT = 25°C 94.7 95.7 % VIN = 38V to 55V , VOUT = 48V, IOUT = 5.21A, TINT = 25°C 95.0 VIN = 38V to 55V , IOUT = 5.21A, TINT = 25°C, over trim 92.0 VIN = 48V, VOUT = 48V, IOUT = 5.21A, TINT = 100°C 95.5 96.5 % VIN = 48V, VOUT = 48V, IOUT = 2.61A, TINT = 100°C 94.5 95.8 % VIN = 38V to 55V , VOUT = 48V, IOUT = 5.21A, TINT = 100°C 95.0 % VIN = 38V to 55V , IOUT = 5.21A, TINT = 100°C, over trim 91.5 % >50% load and VOUT =48 V; over temperature 94.5 % >50% load; over temperature and trim 89.0 Average Value % % % 0.5 Output Voltage Ripple VOUT_PP Output Inductance (Parasitic) LOUT_PAR Frequency @ 1.00 MHz, Simulated J-Lead model Output Capacitance (Internal) COUT_INT Effective value, VOUT = 48 V (see Fig. 13) 2 F Effective value, VOUT = 48 V 3 mΩ Output Capacitance (Internal) ESR RCOUT VIN =48 V, VOUT = 48 V, IOUT =5.21A, COUT_EXT = 0 F, 20 MHz BW -6- 1000 mA 1500 2.5 mV nH Rev. 1.0 11/2012 PRM48BH480 X 250A00 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions, and trim from 20 V to 55 V, unless otherwise noted; Boldface specifications apply over the temperature range of -40ºC < TINT < 125ºC; All Other specifications are at TINT = 25ºC unless otherwise noted. POWER OUTPUT SPECIFICATIONS: ADAPTIVE LOOP OPERATION Output Voltage Setpoint Output Voltage Trim Range Output Voltage Rise Time VOUT_SET No load, trim Inactive, Adaptive Loop load line inactive VOUT tRISE_VOUT 47.04 48 20 From soft start initiated to output voltage settled 1.7 48.96 V 55 V 1.8 1.90 ms Output Voltage Load Regulation VOUT_REG_LOAD Adaptive Loop load line inactive 0.02 0.2 % Output Voltage Line Regulation VOUT_REG_LINE Adaptive Loop load line inactive 0.02 0.2 % 0.2 % 3 % 5 % 7.3 A Total Regulation Error VOUT_REG_TOTAL PRM Output Voltage, Adaptive Loop load line inactive VTM output voltage, total Adaptive Loop regulation, VOUT = 48 V, trim inactive Total AL Regulation Error Output Current Limit VOUT_REG_AL ILIMIT VIN = 48V, VOUT = 48V, TINT = 25°C, Constant current limit after supervisory limit detection time tLIM_SUPV 5.7 Over line, load, trim and temperature 5.2 A 47 F 2mΩ ≤ ESR ≤ 200mΩ, See Figure 31 25 F 10% ↔ 100% load step, 10 A/µsec, 0 uF Cout, deviation from initial setpoint 4.8 V CLOAD_ALEL 0.1Ω ≤ ESR ≤1.0Ω, See Figure 31, total capacitance (CLOAD_ALEL + CLOAD_CER) ≤ 47uF Load Capacitance (Ceramic) CLOAD_CER Load Transient Recovery Time VTRANS tTRANS 6.5 7.3 Load Capacitance (Electrolytic) Load Transient Voltage Deviation 1 VTM output voltage, total Adaptive Loop regulation, trim active, exclusive of external resistor tolerances 10% to100% load step, 10 A/µsec, 0 uF Cout, Recovery to 90% of final value, Adaptive Loop load line inactive 100 s 10% to 100% load step, 10 A/µsec, 0 uF Cout, Recovery to 90% of final value, Adaptive Loop load line active, VAL=1.25V 500 s POWER OUTPUT SPECIFICATIONS: SLAVE OPERATION Rated Current Within an Array Rated Power Within an Array Current Sharing Difference (Master to Slave) Current Sharing Difference (Slave to Slave) Maximum Array Size IOUT_ARRAY POUT_ARRAY IOUT_SHARE_MS IOUT_SHARE_SS NPRMS_PARALLEL Slave operation within an array, up to 5°C case temperature differential, master-slave configuration 4.16 A Slave operation within an array, up to 30°C case temperature differential, master-slave configuration 3.6 A Slave operation within an array, up to 5°C case temperature differential, master-slave configuration 200 W Slave operation within an array, up to 30°C case temperature differential, master-slave configuration 175 W Equal input, and output voltage at full load; VIN = 48 V, VOUT = 48 V 15 % Equal input and output voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C ≤ 5°C part-part temp mismatch 15 % Equal input, and output voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp. mismatch 20 % Equal input, output, and SHARE voltage at full load; VIN = 48 V, VOUT = 48 V 5 % Equal input, output and SHARE voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 5°C part-part temp mismatch 10 % Equal input, output, and SHARE voltage at full load; Over line and trim, with25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp mismatch 15 % Maximum number of parallel devices, master-slave configuration 5 PRMs POWER OUTPUT SPECIFICATIONS: REMOTE SENSE OPERATION Output Voltage Range VOUT Rated Current Within an Array IOUT_ARRAY Rated Power Within an Array POUT_ARRAY Current Sharing Difference Maximum Array Size IOUT_SHARE_RS NPRMS_PARALLEL 55 V Remote Sense operation within an array, up to 5°C case temperature differential 20 4.7 A Remote Sense operation within an array, up to 30°C case temperature differential 3.6 A Remote Sense operation within an array, up to 5°C case temperature differential 225 W Remote Sense operation within an array, up to 30°C case temperature differential 175 W Equal input, output, and CONTROL NODE voltage at full load; VIN = 48 V, VOUT = 48 V 5 % Equal input, output and CONTROL NODE voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 5°C part-part temp mismatch 10 % Equal input, output, and CONTROL NODE voltage at full load; Over line and trim, with 25°C ≤ TC ≤ 100°C and ≤ 30°C part-part temp. mismatch (worst case) 15 % Maximum number of parallel devices, Remote Sense configuration, CONTROL NODE externally driven 10 PRMs -7- Rev. 1.0 11/2012 PRM48BH480 X 250A00 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions, and trim from 20 V to 55 V, unless otherwise noted; Boldface specifications apply over the temperature range of -40ºC < TINT < 125ºC; All Other specifications are at TINT = 25ºC unless otherwise noted. POWERTRAIN PROTECTIONS Input Undervoltage Turn-ON VIN_UVLO+ Input Undervoltage Turn-OFF VIN_UVLO- Input Undervoltage Hysteresis VUVLO_HYST 24.5 Instantaneous powertrain shutdown, detected after tBLNK (VIN_UVLO+) - (VIN_UVLO-) 22.0 1.8 2.2 56.0 62.6 Input Overvoltage Turn-ON VIN_OVLO+ Input Overvoltage Turn-OFF VIN_OVLO- Input Overvoltage Hysteresis VOVLO_HYST (VIN_OVLO+) - (VIN_OVLO-) 0.7 Output Overvoltage Threshold VOUT_OVP+ Instantaneous powertrain shutdown, detected after tBLNK 56.0 Minimum Current Limited Vout VOUT_UVP Overtemperature Shutdown Setpoint TINT_OTP Output Power Limit Instantaneous powertrain shutdown, detected after tBLNK Instantaneous powertrain shutdown, detected after tBLNK PPROT 26.0 22.7 63.6 V V 2.5 V V 67.3 V 1.0 1.4 V 57.9 60.0 V 12 V 125 ºC 250 W Short Circuit Vout Threshold VSC_VOUT 8.8 V Short Circuit Vout Recovery Threshold VSC_VOUTR 9.5 V Short Circuit CONTROL NODE Threshold VSC_VCN 7.2 V Short Circuit CONTROL NODE Recovery Threshold VSC_VCN 6.9 V Short Circuit Timeout tSC Short circuit fault detected after VSC_VOUT and VSC_VCN thresholds persist for this time 5 ms Short Circuit Recovery Time tSCR Excludes tOFF 75 ms Overcurrent (IFB ), and Input Over/Undervoltage Blanking Time tBLNK Overtemperature, Output Overvoltage and ENABLE Shutdown Response Time (Hardware) tPROT 50 120 150 s s 2 POWERTRAIN SUPERVISORY LIMITS Input Undervoltage Turn-ON (Supervisory) VIN_UVLO+_SUPV Powertrain shutdown, after supervisory detection tLIM_SUPV Input Undervoltage Turn-OFF (Supervisory) VIN_UVLO-_SUPV Powertrain shutdown, after supervisory detection tLIM_SUPV 32.2 33.6 Input Undervoltage Hysteresis (Supervisory) VUVLO_HYST_SUPV (VIN_UVLO+_SUPV) - (VIN_UVLO-_SVPV) 1.9 2.2 56.0 57.7 Input Overvoltage Turn-ON (Supervisory) VIN_OVLO+_SUPV Powertrain shutdown after supervisory detection tLIM_SUPV Input Overvoltage Turn-OFF (Supervisory) VIN_OVLO-_SUPV Powertrain shutdown after supervisory detection tLIM_SUPV Input Overvoltage Hysteresis (Supervisory) VOVLO_HYST_SUPV Undertemperature Shutdown Setpoint (Supervisory) TINT_UTP Supervisory Limit Response Time tLIM_SUPV 35.8 37.0 V V 2.5 V V 58.9 60.0 V 1.2 1.7 V T Grade -40 ºC M Grade -55 ºC 150 s (VIN_OVLO+_SUPV) - (VIN_OVLO-_SUPV) 0.8 -8- Rev. 1.0 11/2012 PRM48BH480 X 250A00 SIGNAL SPECIFICATIONS Specifications apply over all line and load conditions, TINT = 25 ºC and output voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TINT < 125 ºC (T-grade). ENABLE • The ENABLE pin enables and disables the PRM • In PRM array configurations, ENABLE pins should be connected in order to synchronize startup • ENABLE is 5.0V with 1.8mA source capability during normal operation Signal Type State Regular Operation Analog Output Startup Startup Digital Input / Output Standby Digital Output Fault Attribute Symbol Min Typ Max Unit ENABLE voltage VENABLE 4.7 5.0 5.3 V ENABLE available current IENABLE_OP 1.8 ENABLE source current IENABLE_EN Minimum time to start Conditions / Notes After tOFF mA A 90 tOFF 13.5 ENABLE enable threshold VENABLE_EN ENABLE disable threshold VENABLE_DIS ENABLE resistance (external) RENABLE_EXT Resistance to SGND required to disable the PRM ENABLE sink current to SGND IENABLE_FAULT ENABLE voltage 1 V or above 0.97 15 16.5 ms 2.5 3.2 V 2.4 V 235 Ω 4 mA VAUX: AUXILARY VOLTAGE SOURCE • Intended to power auxiliary circuits • 9.0V during normal operation with 5mA source capability Signal Type State Regular Operation Analog Output Transition Attribute Symbol VAUX Voltage VVAUX VAUX Available Current IVAUX VAUX Voltage Ripple VVAUX_PP VAUX Capacitance (External) CVAUX_EXT VAUX Fault Response Time tFR_VAUX Conditions / Notes Min Typ Max Unit 8.6 9.0 9.5 V 5 Iout = 0A, CVAUX_EXT = 0. Maximum specification includes powertrain operation in burst mode. mA 100 From fault recognition to VAUX = 1.5 V 400 mV 0.04 F s 30 VC: VTM CONTROL • Pulsed voltage source used to power and synchronize downstream VTM during startup • 14 V, 10 ms typical voltage pulse Signal Type Analog Output State Startup Attribute Symbol Conditions / Notes Min Typ Max Unit 14 18 V 10 16 ms 0.25 V/s VC Voltage VVC_START Connected to VTM VC or equivalent, IVC = 115mA, CVC = 3.2uF 13 VC Available Current IVC_START VC =14 V, VIN > 20 V 200 VC duration VC Slew Rate ENABLE to VC delay tVC dVC/dt 7 Connected to VTM or equivalent, IVC = 115mA, CVC = 3.2uF tENABLE-VC mA 0.02 s 20 -9- Rev. 1.0 11/2012 PRM48BH480 X 250A00 SGND: SIGNAL GROUND • All control signals must be referenced to this pin, with the exception of VC • SGND is internally connected to –IN and –OUT Signal Type Analog Input / Output State Any Attribute Symbol Maximum Allowable Current Conditions / Notes ISGND Min Typ -100 Max Unit 100 mA TRIM • TRIM is used to select operating mode and trim the output voltage in Adaptive Loop operation • Internal pullup to VCC_INT through10kΩ resistor • When pulled below 0.45V during power up, Remote Sense / Slave operation is selected • When allowed to pull up above 0.55 during power up, Adaptive Loop operation is selected • Operating mode is latched during power up and cannot be changed unless input power is cycled Signal Type State Normal Operation Analog Input Mode Detect Attribute Symbol Internally generated VCC VCC_INT Internal Pullup Resistance to VCC_INT RTRIM_INT Mode Detection Delay Conditions / Notes Min Typ Max Unit 3.20 3.28 3.36 V 0.5% tolerance resistor 9.83 10 10.18 kΩ 100 140 200 µs 0.45 V tMODE_DETECT From ENABLE high to mode detected, after VIN first applied Remote Sense Enable Threshold VRS_MODE_EN Pull below this value during application of power to enable Remote Sense / Slave operation Remote Sense Disable Threshold VRS_MODE_DIS Pull above this value during application of power to enable Adaptive Loop operation 0.55 V TRIM (ADAPTIVE LOOP OPERATION ONLY) • Provides dynamic trim control over the PRM output voltage in Adaptive Loop operation • Sampled prior to every startup to detect if trim is active or inactive • Output voltage is equal to 20 times the voltage at the TRIM pin when applied TRIM voltage is within the active range • Trim state is latched during normal operation and cannot be changed until startup is initiated Signal Type State Startup Attribute VTRIM_EN Pull below this value during startup to enable trim control Trim Disable Threshold VTRIM_DIS Pull above this value during startup to disable trim control Minimum Trim Disable Resistance RTRIM_DIS_MIN Minimum TRIM resistance required to disable trim Min Typ 100 TRIM Pin Analog Range VTRIM_RANGE See Figure 26 1.00 VOUT referred trim resolution VOUT_RES Trim latency tTRIM_LAT Trim Bandwidth BW TRIM V MΩ From ENABLE high to TRIM sampled %ACC_TRIM 3.10 10 tENABLE_TRIM Trim Accuracy Unit V CTRIM_EXT GTRIM Max 3.20 Trim Sample Delay TRIM Gain Normal Operation Conditions / Notes Trim Enable Threshold Trim Capacitance (External) Analog Input Symbol 140 100 pF 200 µs 2.75 VOUT / VTRIM, VTRIM applied within active range 20 Vout accuracy, exclusive of external resistor tolerance 0.5 V/V 2 200 60 -3dB point - 10 - 120 % mV 240 1.2 s kHz Rev. 1.0 11/2012 PRM48BH480 X 250A00 AL: ADAPTIVE LOOP (ADAPTIVE LOOP OPERATION ONLY) • Provides Adaptive Loop load line programming in Adaptive Loop operation • Internal pullup to VCC_INT through10kΩ resistor • Sampled prior to every startup to detect if Adaptive Loop load line is active or inactive • Leave open to disable Adaptive Loop load line • Not used in Remote Sense operation Signal Type State Attribute Symbol AL Enable Threshold Startup VAL_EN AL Disable Threshold VAL_DIS Minimum AL Disable Resistance RAL_DIS_MIN AL Capacitance (External) tENABLE_AL Internally generated VCC VCC_INT Internal Pullup Resistance to VCC_INT RAL_INT AL Pin Analog Range VAL_RANGE AL Gain Normal Operation Min Typ Pull above this value to disable AL load line Minimum AL resistance required to disable AL load line GAL AL Load Line Accuracy %ACC_LL_AL AL load line resolution LLAL_RES Maximum output referred compensation VOUT_AL_MAX AL Latency tAL_LAT AL Bandwidth BW AL From ENABLE high to AL sampled 0.5 % tolerance resistor Max Unit 3.10 V 3.20 V 10 MΩ CAL_EXT AL Sample Delay Analog Input Conditions / Notes Pull below this value during startup to enable AL load line 100 pF 100 140 200 µs 3.20 3.28 3.36 V 9.83 10 10.18 kΩ 0 3.10 Positive correction slope, VT inactive 1.0 Full load slope accuracy exclusive of external resistor tolerance 0.5 2 3 120 -3dB point % mΩ Maximum increase from no load setpoint, VOUT ≤ 55V 60 V Ω/V 5 V 240 s 1.2 kHz VT: VTM TEMPERATURE (ADAPTIVE LOOP OPERATION ONLY) • VTM temperature compensation for Adaptive Loop regulation • Adjusts the slope of the Adaptive Loop load line to account for changes in VTM output resistance over temperature • Connect to TM pin of compatible downstream VTM to enable temperature compensation • Leave disconnected to disable temperature compensation Signal Type Analog Input State Normal Operation Attribute Symbol Internal Resistance to SGND RVT_INT Conditions / Notes VVT_EN VT Disable Threshold VVT_DIS Pull below this value to disable VT temperature compensation VT Disable Default Temperature TVT_DIS Default AL temperature setting when VT disabled VT analog range VVT_OP VT Resolution Typ Max 80 VT Enable Threshold VT Temperature Coefficient Min Unit kΩ 2.1 1.9 V V 25 2.18 °C 3.98 V TCVT VT within active range, referenced to 2.98V 30 %/V TCVT VTM TM voltage applied, .01V/°K, referenced to 25C 0.3 %/C TCVT_RES VT Latency tVT_LAT Bandwidth BW VT - 11 - VTM TM voltage applied, .01V/°K 0.4 60 -3dB point 120 °C 240 1.5 s kHz Rev. 1.0 11/2012 PRM48BH480 X 250A00 REF / REF_EN REF: REFERENCE (ADAPTIVE LOOP OPERATION ONLY) • Functions as REF pin in Adaptive Loop operation • REF represents the internal voltage reference for the voltage control circuit • VOUT approximately equal to 20 times REF voltage Signal Type State Attribute REF Voltage REF to VOUT Scale Factor Regular Operation Analog Output Transition Symbol VREF GREF_VOUT REF Resistance (External) RREF_EXT REF Capacitance (External) CREF_EXT REF Voltage Ripple VREF_PP ENABLE to REF Delay VAUX to REF Delay tENABLE_REF tVAUX_REF Conditions / Notes Min Typ Max Unit VOUT = 48V, Trim inactive 2.4 V VOUT / VREF 20 V/V 10 MΩ 200 pF includes burst mode, 20MHz BW 25 ENABLE low to REF low 120 s 1 ms VAUX = 8.1 V to REF soft start ramp initiated mV REF_EN: REFERENCE ENABLE (REMOTE SENSE AND SLAVE OPERATION ONLY) • Functions as REF_EN pin in Remote Sense and Slave operation • REF_EN signals successful startup and powertrain ready to operate • Intended to power and enable the external feedback circuit reference in Remote Sense operation • 3.25V, 4mA regulated voltage source Signal Type State Regular Operation Analog Output Transition Attribute Symbol REF_EN Voltage VREF_EN REF_EN Source Impedance ROUT_REF_EN REF_EN Available Current Conditions / Notes REF_EN unloaded IREF_EN Min Typ Max Unit 2.72 3.25 3.37 V 50 100 Ω 4 mA REF_EN Capacitance (External) CREF_EN_EXT includes burst mode, 20MHz BW REF_EN Voltage Ripple VREF_EN_PP includes burst mode 25 mV ENABLE low to REF_EN low 1 ms VAUX = 8.1 V to REF_EN high 1 ms ENABLE to REF_EN Delay VAUX to REF_EN Delay tENABLE_REF_EN tVAUX_REF_EN - 12 - 0.1 Rev. 1.0 11/2012 F PRM48BH480 X 250A00 SHARE / CONTROL NODE SHARE (ADAPTIVE LOOP AND SLAVE OPERATION ONLY) • Functions as SHARE pin in master slave array configuration • Current share bus for array operation (master/slave scheme) • Sources current and provides SHARE signal in master operation • Sinks constant current when externally driven in active range (Slave operation) Signal Type Analog Output Analog Input State Standalone / Master Operation Slave Operation Attribute Symbol SHARE Voltage Active Range VSHARE SHARE Available Current ISHARE SHARE Resistance to SGND RSHARE SHARE Sink Current ISHARE_SINK Conditions / Notes Min Typ 0.79 VSHARE > 0.79V Max Unit 7.40 V 2.5 mA 93.3 VSHARE > 0.79V kΩ 0.25 0.50 0.75 mA Min Typ Max Unit 7.40 V 2.5 mA 0.75 mA CONTROL NODE (REMOTE SENSE OPERATION ONLY) • Functions as CONTROL NODE pin in Remote Sense operation • Modulator control node voltage sets power train timing • Driven by external error amplifier in Remote Sense operation • Sinks constant current when externally driven in active range • Sources current, and clamps voltage to 0.79V when pulled below active range Signal Type State Attribute CONTROL NODE Voltage Active Range Analog Input Regular Operation Symbol Conditions / Notes VCN 0.79 CONTROL NODE Source Current ICN_LOW VCN < 0.79V CONTROL NODE Sink Current ICN_SINK VCN > 0.79V CONTROL NODE Resistance to SGND 0.25 0.50 93.3 RCN kΩ IFB: CURRENT FEEDBACK (REMOTE SENSE OPERATION ONLY) • Functions as IFB pin in Remote Sense operation • A voltage proportional to the PRM output current must be supplied externally to the IFB pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp) • Overcurrent protection trip will cause instantaneous powertrain shutdown, detected after tBLNK •Not used for Adaptive Loop operation Signal Type Analog Input State Regular Operation Attribute Symbol Current Limit (clamp) Threshold VIFB_IL Overcurrent Protection Threshold VIFB_OC IFB Input Impedance RIFB Current Limit Bandwidth BW IL Min Typ Max Unit VIN = 48V V; VOUT = 48V TINT = 25 °C Conditions / Notes 1.90 2.00 2.10 V Over Line, Trim, and Temperature 1.85 2.15 V Not Production Tested; Guaranteed by Design; TINT = 25 °C 2.58 2.80 V Not Production Tested; Guaranteed by Design; Over Line, Trim, and Temperature 2.09 2.17 V 2.17 kΩ 2.09 2.69 2.13 2.0 kHz NC: NO CONNECT • Reserved for factory use only • No connections should be made to these pins - 13 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 FUNCTIONAL BLOCK DIAGRAM +IN +OUT Q3 Q1 Cin Cout L -IN -OUT Q2 PGND Q4 Internal VCC Regulator 30.1k VCC Error Amplifer Modulator Enable 2.5mA Min 0.5mA 3.3V Linear Regulator Voltage Reference 3.3V SHARE/ CONTROL NODE 1.58k OTP 10k 10k VT 2.1k ENABLE VAUX 10k TRIM Control and Monitoring NC 1000pF NC AL Overvoltage Lockout Undervoltage Lockout 10k 0.01uF 57.6k Current Limit 1000pF 35.7k IN Adaptive Loop 0.01uF 30.1 IFB 20k SGND 0.01uF REF/ REF_EN Output Overvoltage Protection VC 60.4k Output Short Circuit 2200pF 10 k 6800 pF OUT SGND SGND PGND - 14 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 HIGH LEVEL FUNCTIONAL STATE DIAGRAM Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles. Application of Vin VIN > UVLO+ STARTUP SEQUENCE STANDBY SEQUENCE tON expired ENABLE: 1.8mA to HIGH VC Pulse REF_EN active ENABLE rising edge ENABLE: 10uA to LOW tOFF expired ENABLE: 90uA to HIGH Adaptive loop and trim modes latched RS mode latched at first ENABLE after Vin applied only Powertrain Stopped ENABLE falling edge, Output OVP, or OTP detected Powertrain Active Input OVLO or UVLO, Output UVP, or UTP detected Fault Autorecovery ENABLE falling edge, Output OVP or OTP detected FAULT SEQUENCE ENABLE pulsed: 25mA to LOW Powertrain Stopped tSTARTUP_SEQ expired Input OVLO or UVLO, Output UVP, or UTP detected SUSTAINED OPERATION ENABLE: 1.8mA to HIGH Powertrain Active Short Circuit detected - 15 - Rev. 1.0 11/2012 - 16 - AL TRIM VAUX 2.4V 20V 48V 55V tAUX_REF TRIM Ignored 2 TRIM INACTIVE TRIM and AL pins sampled Soft Start tVC tENABLE_VC tOFF tON Micro‐controller initialized 1V 0V 1.0V 3.3V 2.75V VAUX VREF VOUT_MIN OUT_NOM VOUTV VOUT_OVP+ VOUT_MAX VC VVC_START ENABLE_EN ENABLE V OUTPUT INPUT ILIMIT VENABLE Iout VSHARE_MIN SHARE REF INPUT VINIT VSHARE_MAX +IN VIN_UVLO VIN_OVLO OUTPUT OUTPUT OUTPUT BIDIR BIDIR BIDIR INPUT 1 INPUT POWER ON AND UV TURN‐ON AL = 1V 3 AL ACTIVE FirstEnb: TR not low = not RS mode TR high = trim inactive for this enabled period AL not high = AL active for this enabled period tBLNK Vout increases by VAL * GAL * IOUT tBLNK tBLNK 4 INPUT OV tOFF Soft Start 5 INPUT OV RECOVERY TR high = trim inactive for this enabled period AL not high = AL active for this enabled period tPROT tPROT 8 9 FULL LOAD OUTPUT APPLIED OV Current sense activated, and output increase due to AL after tSTARTUP_SEQ expires AL = 1V tSTARTUP_SEQ tON 6 7 ENABLE ENABLE DISABLE RELEASE TR high = trim inactive for this enabled period AL not high = AL active for this enabled period PRM48BH480 X 250A00 TIMING DIAGRAMS (Adaptive Loop operation page 1) Module Inputs are shown in blue; Module Outputs are shown in brown. Rev. 1.0 11/2012 - 17 - VINIT ILIMIT INPUT 1V 3.3V 1V 2.4V 2.75V 20V 48V 55V tBLNK AL pin Ignored VOUT = VTRIM * 20 Micro‐controller Operating Mode initialized Trim and AL state detected AL 1V 3.3V TRIM 2.75V 2.4V INPUT VAUX VAUX OUTPUT VOUT_MIN REF VOUT VOUT_NOM VOUT_MAX VC VVC_START VENABLE_EN ENABLE VENABLE Iout VSHARE_MIN SHARE VSHARE_MAX +IN VIN_UVLO VIN_OVLO OUTPUT OUTPUT OUTPUT BIDIR BIDIR BIDIR INPUT tSC tSCR+tOFF FirstEnb: TR not low = not RS mode TR not high = trim active for this enabled period AL high = AL inactive for this enabled period 10 11 12 INPUT POWER ON AL OUTPUT AND UV TURN‐ON INACTIVE AND SHORT TRIM CIRCUIT ACTIVE tOFF 14 OT SHUTDOWN AND RECOVERY AL active Vout increase due to Iout and AL after tSTARTUP_SEQ expires VOUT clamped to 55V for VTRIM > 2.75V tSTARTUP_SEQ 13 ENABLE TOGGLING 15 OUTPUT POWER LIMIT PROTECTION tLIM_SUPV 16 CURRENT LIMIT EVENT tBLNK 17 INPUT POWER OFF AND UV TURN‐OFF TR high = trim inactive for this enabled period AL not high = AL active for this enabled period TR high = trim inactive for this enabled period AL not high = AL active for this enabled period TR not high = trim active for this enabled period AL high = AL inactive for this enabled period PRM48BH480 X 250A00 TIMING DIAGRAMS (Adaptive Loop operation page 2) Rev. 1.0 11/2012 VINIT VIN_UVLO VENABLE VIFB_IL - 18 - TRIM VAUX tVC tAUX_REF_EN tOFF tON Micro‐controller initialized VAUX VREF_EN REF_EN VOUT VOUT_OVP+ VC VVC_START VENABLE_EN ENABLE IFB VIFB_OC VCN_MIN CONTROL NODE VCN_MAX +IN VIN_OVLO 1 INPUT POWER ON AND UV TURN‐ON tBLNK tENABLE_REF_EN tBLNK 4 INPUT OV RECOVERY tENABLE_REF_EN tPROT 5 ENABLE DISABLE 6 ENABLE RELEASE tON TRIM ignored for all subsequent start up events until VIN is removed This blue shaded region is where trim voltage is a don’t care. RS operating mode is latched. TRIM is ignored until Vin is removed. t < tBLNK tBLNK 2 3 QUICK OC INPUT OV (t<tBLNK) First Enable: Trim Low = RS mode RS mode detected and latched tENABLE_REF_EN tPROT 8 7 FULL LOAD LOAD RELEASE AND APPLIED OUTPUT OV (SLOW F/B) PRM48BH480 X 250A00 TIMING DIAGRAMS (Remote Sense operation page 1) Rev. 1.0 11/2012 VENABLE VIFB_IL VIFB_OC - 19 - tOFF Micro‐controller initialized TRIM VAUX VAUX VREF_EN REF_EN VOUT VOUT_OVP+ VC VVC_START VENABLE_EN ENABLE IFB VCN_MIN CONTROL NODE VCN_MAX VINIT VIN_UVLO +IN VIN_OVLO 9 START UP WITH MINIMUM < dVIN/dt < 1.2V/ms <tBLNK tSC 10 OUTPUT SHORT CIRCUIT First Enable: Trim Low = RS mode RS mode detected and latched 12 CURRENT LIMIT EVENT This blue shaded region is where trim voltage is a don’t care. RS operating mode is latched. TRIM is ignored until Vin is removed. tSCR+tOFF 11 OUTPUT POWER LIMIT PROTECTION TRIM ignored for all subsequent start up events until VIN is removed tBLNK 13 INPUT UV PRM48BH480 X 250A00 TIMING DIAGRAMS (Remote Sense operation page 2) Rev. 1.0 11/2012 PRM48BH480 X 250A00 TYPICAL PERFORMANCE CHARACTERISTICS The following figures present typical performance at TC = 25ºC, unless otherwise noted. Efficiency & Power Dissipation VOUT = 20 V TCASE =-40 °C DC Safe Operating Area 6.0 300 100 250 95 10 90 8 85 6 80 4 2 12 200 Power 3.0 150 2.0 100 1.0 50 75 0 70 0.0 25 30 35 40 45 50 55 60 0 0 0.75 1.5 Output Voltage [V] Current 3.75 4.5 5.25 VIN: 48 V VIN: 55 V Figure 4: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 20 V, TCASE = -40 °C No Load Power Dissipation vs. Line Module Enabled - 48 Vout Efficiency & Power Dissipation VOUT = 20 V TCASE =25 °C 100 12 3.5 95 10 3 90 8 85 6 80 4 75 2 Efficiency [%] Power Dissipation [W] 3 Load Current [A] VIN: 38 V Power Figure 1 DC Safe Operating Area (SOA) 4 2.25 2.5 2 1.5 1 38 40 42 44 46 48 50 52 54 70 56 TCASE: ‐40°C TCASE: 25°C 0 0 Input Voltage [V] Power Dissipation [W] 20 Power Dissipation [W] 4.0 Efficiency [%] Output Current [A] 5.0 Output Power [W] Current 0.75 1.5 2.25 3 3.75 4.5 5.25 Load Current [A] VIN: 38 V TCASE: 100°C VIN: 48 V VIN: 55 V Figure 5: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 20 V, TCASE = 25 °C Figure 2: No Load Power Dissipation vs. VIN, module enabled No Load Power Dissipation vs. Line Module Disabled - ENABLE = Low Efficiency & Power Dissipation VOUT = 20 V TCASE =100 °C 100 1 14 95 12 90 10 85 8 80 6 0.6 75 4 0.5 70 2 0.8 0.7 65 0.4 38 40 42 44 46 48 50 52 54 TCASE: 25°C 0.75 1.5 2.25 3 3.75 4.5 5.25 Load Current [A] Input Voltage [V] TCASE: ‐40°C 0 0 56 Power Dissipation [W] Efficiency [%] Power Dissipation [W] 0.9 VIN: 38 V TCASE: 100°C VIN: 48 V VIN: 55 V Figure 6: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 20 V, TCASE = 100 °C Figure 3: No Load Power Dissipation vs. VIN, module disabled - 20 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Efficiency & Power Dissipation VOUT = 48 V TCASE =-40 °C 98 18 94 16 92 14 90 12 88 6 10 86 88 4 8 84 6 82 4 80 2 2 86 78 0 84 0 0.75 1.5 2.25 3 3.75 4.5 0 0 5.25 0.75 1.5 Load Current [A] VIN: 38 V VIN: 55 V VIN: 38 V Efficiency & Power Dissipation VOUT = 48 V TCASE =25 °C 98 2.25 3 3.75 4.5 5.25 Load Current [A] VIN: 48 V Figure 7: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 48 V, TCASE = -40 °C VIN: 48 V VIN: 55 V Figure 10: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 55 V, TCASE =-40 °C Efficiency & Power Dissipation VOUT = 55 V TCASE =25 °C 98 14 20 96 18 94 16 92 14 90 12 88 10 86 8 84 6 82 4 80 2 90 6 88 4 Power Dissipation [W] 8 92 Efficiency [%] 10 94 Power Dissipation [W] 12 96 2 86 78 0 84 0 0.75 1.5 2.25 3 3.75 4.5 0 0 5.25 0.75 1.5 Load Current [A] VIN: 38 V VIN: 48 V 3 3.75 4.5 5.25 Load Current [A] VIN: 55 V VIN: 38 V Figure 8: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 48 V, TCASE = 25 °C Efficiency & Power Dissipation VOUT = 48 V TCASE =100 °C 98 2.25 14 90 6 88 4 Efficiency [%] 8 92 Power Dissipation [W] 10 94 VIN: 55 V Efficiency & Power Dissipation VOUT = 55 V TCASE =100 °C 98 12 96 VIN: 48 V Figure 11: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 55 V, TCASE = 25 °C 20 96 18 94 16 92 14 90 12 88 10 86 8 84 6 82 4 80 2 Power Dissipation [W] Efficiency [%] Power Dissipation [W] 90 Efficiency [%] 8 92 Power Dissipation [W] 10 94 Efficiency [%] 20 96 12 96 Efficiency [%] Efficiency & Power Dissipation VOUT = 55 V TCASE =-40 °C 98 14 2 86 0 84 0 0.75 1.5 2.25 3 3.75 4.5 78 5.25 0 0 0.75 1.5 Load Current [A] VIN: 38 V VIN: 48 V 2.25 3 3.75 4.5 5.25 Load Current [A] VIN: 55 V VIN: 38 V Figure 9: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 48 V, TCASE = 100 °C VIN: 48 V VIN: 55 V Figure 12: Total efficiency and power dissipation vs. VIN and IOUT VOUT = 55 V, TCASE =100 °C - 21 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Output Power vs. SHARE / CONTROL NODE Voltage VIN = 48 V, VOUT = 48 V, TCASE = 25 °C Effective Internal Input and Output Capacitance vs. Applied Voltage 250 5.0 4.5 INPUT AND OUTPUT CAPACITANCE 200 3.5 Output Power [W] Effective Capacitance (µF) 4.0 3.0 2.5 2.0 1.5 150 100 50 1.0 0.5 0 0.0 0 5 10 15 20 25 30 35 40 45 50 2.5 55 3 3.5 4 4.5 5 5.5 6 6.5 7 VCONTROL_NODE [V] Applied Voltage [V] Typical Input and Output Capacitance (uF) Figure 13 Effective Internal Input and Output Capacitance vs. Voltage – Ceramic Type Figure 16 Output Power vs. SHARE / CONTROL NODE Voltage; VIN = 48 V, VOUT = 48 V, TCASE = 25 °C Power Train Switching Frequency and Periodic Input Charge vs. Input Voltage - Full Load SHARE / CONTROL NODE Voltage vs. Case Temperature VIN = 48 V VOUT = 48 V 1050 16 Switching Frequency (kHz)) 1025 6.5 14 975 10 950 8 925 Input Charge (µC) 6 900 4 875 2 850 0 VCONTROL NODE [V] 12 Total Input Charge per Switching Cycle [µC] Fsw [kHz] 6 1000 40 42 44 46 48 50 52 54 4.3 4.3 5.7 5 4.1 4 56 ‐40 Input Voltage [V] VOUT: 20 V 5.9 5.5 4.5 38 5.8 ‐20 0 20 40 60 80 100 Case Temperature [°C] VOUT: 48 V VOUT: 55 V IOUT: 2.08 A Figure 14: Power Train Switching Frequency and Periodic Input Charge vs. VIN, VOUT; IOUT = 5.21 A IOUT: 5.21 A Figure 17: Typical SHARE / CONTROL NODE Voltage vs. TCASE and IOUT; VIN = 48 V, VOUT =48 V Power Train Switching Frequency and Periodic Output Charge vs. Input Voltage - Full Load Fsw [kHz] 16 Switching Frequency (kHz)) 1025 14 1000 12 975 10 950 8 925 Output Charge (µC) 6 900 4 875 2 850 Total Output Charge per Switching Cycle [µC] 1050 0 38 40 42 44 46 48 50 52 54 56 Input Voltage [V] VOUT: 20 V VOUT: 48 V VOUT: 55 V Figure 15: Power Train Switching Frequency and Periodic Output Charge vs. VIN, VOUT; IOUT = 5.21 A - 22 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 DC Modulator Gain and Powertrain Equivalent Resistance vs. Output Current - Vout = 20 V GCN (dB) 5 120 125 100 100 80 rIN [Ω] GCN [dB] 7.5 Powertrain Equivalent Input Resistance vs. Output Current - Vout = 20 V 150 req [Ω] 10 2.5 75 0 50 40 25 20 0 0 ‐2.5 req (Ω) ‐5 0 0.75 1.5 2.25 3 3.75 4.5 60 5.25 0 0.75 1.5 Load Current[A] VIN: 38 V 2.25 3 3.75 4.5 5.25 Load Current[A] VIN: 48 V VIN: 38 V VIN: 55 V Figure 18 Powertrain Characteristics vs. IOUT, VIN Resistive Load, VOUT = 20V VIN: 55 V Powertrain Equivalent Input Resistance vs. Output Current - Vout = 48 V DC Modulator Gain and Powertrain Equivalent Resistance vs. Output Current - Vout = 48 V 10 VIN: 48 V Figure 21 Magnitude of powertrain dynamic input impedance vs. IOUT, VIN; VOUT = 20 V 50 300 0 200 ‐5 150 ‐10 100 40 rIN [Ω] 250 req [Ω] GCN [dB] GCN (dB) 5 30 20 ‐15 10 50 req (Ω) 0 0 ‐20 0 0.75 1.5 2.25 3 3.75 4.5 0 5.25 0.75 1.5 VIN: 38 V VIN: 48 V VIN: 38 V VIN: 55 V Figure 19 Powertrain Characteristics vs. IOUT, VIN Resistive Load, VOUT = 48V 3 3.75 4.5 5.25 GCN (dB) VIN: 55 V Powertrain Equivalent Input Resistance vs. Output Current - Vout = 55 V 50 300 250 200 ‐5 150 ‐10 100 rIN [Ω] 0 40 req [Ω] 5 VIN: 48 V Figure 22 Magnitude of powertrain dynamic input impedance vs. IOUT, VIN; VOUT = 48 V DC Modulator Gain and Powertrain Equivalent Resistance vs. Output Current - Vout = 55 V 10 GCN [dB] 2.25 Load Current[A] Load Current[A] 30 20 ‐15 10 50 req (Ω) ‐20 0 0 0.75 1.5 2.25 3 3.75 4.5 0 5.25 0 0.75 1.5 Load Current[A] VIN: 38 V VIN: 48 V 2.25 3 3.75 4.5 5.25 Load Current[A] VIN: 38 V VIN: 55 V Figure 20 Powertrain Characteristics vs. IOUT, VIN Resistive Load, VOUT = 55V VIN: 48 V VIN: 55 V Figure 23 Magnitude of powertrain dynamic input impedance vs. IOUT, VIN; VOUT = 55 V - 23 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 GENERAL CHARACTERISTICS Specifications apply over all line and load conditions, TINT = 25 ºC and output voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TINT < 125 ºC (T-grade). Attribute Symbol Conditions / Notes Min Typ Max Unit 21.8 22.0 22.3 mm (.86) (0.87) (.88) in 16.3 16.5 16.8 mm (0.64) (0.65) (0.66) in 6.48 6.73 6.98 mm (0.255) (0.265) (0.275) MECHANICAL Length Width Height L W H Volume Vol Weight W Lead Finish No heat sink in 2.44 cm3 (0.15) in3 7 g Nickel 0.51 2.03 Palladium 0.02 0.15 0.003 0.050 T Grade -40 125 M Grade -55 Gold m THERMAL Operating Internal Temperature Thermal Impedance TINT ºC 125 ºC θINT-CASE 2 ºC/W θINT-LEAD 9 ºC/W 5 Ws/ºC Thermal Capacity ASSEMBLY Peak Compressive Force Applied to Case (Z-axis) Storage Temperature Moisture Sensitivity Level ESD Rating Supported by J-Lead only TST MSL 3 lbs 5.33 lbs / in2 T Grade -40 125 ºC M Grade -65 125 ºC MSL 6, 245C Reflow MSL5, 225C Reflow Human Body Model, "JEDEC JESD 22-A114C.01" 1000 Charged Device Model, "JEDEC JESD 22-C101D" 400 V SOLDERING Peak Temperature During Reflow Under MSL 6 conditions above 245 ºC Under MSL 5 conditions above 225 ºC Maximum Time Above 217 ºC 150 s Peak Heating Rate During Reflow 1.5 2 ºC / s Peak Cooling Rate Post Reflow 2.5 3 ºC / s RELIABILITY AND AGENCY APPROVALS MTBF Telcordia Issue 2 - Method I Case 1; Ground Benign, Controlled 5.28 MHrs MIL-HDBK-217Plus Parts Count - 25C Ground Benign, Stationary, Indoors / Computer Profile 5.28 MHrs CTUVUS Agency Approvals / Standards EN60950-1, UL/CSA 60950-1 CE Mark Low Voltage Directive (2006/95/EC) ROHS 6 of 6 - 24 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 PIN FUNCTIONS VC: VTM Control +IN, -IN +OUT, -OUT This output pin is used to temporarily provide VCC voltage to connected VTMs during start up. The pulse is nominally 14V, 10 ms wide. A VTM can self-power once its input voltage reaches 26V. The PRM output must be checked to make sure it reaches this threshold voltage before the VC pulse expires. Output power pins. Module cannot sink current. TRIM ENABLE The TRIM pin is used to select the operating mode and to trim the PRM output when Adaptive Loop operating mode is selected. The TRIM pin has an internal pull-up to VCC_INT through a 10 kΩ resistor. Input power pins This pin turns the supply on and off. The pin is both an input and an output and can provide the following features: Delayed Start: upon application of voltage (>UVLO) to the module power input and after toff, the ENABLE pin will source a constant 90μA current. Output enable: When ENABLE is allowed to pull up above the enable threshold, the ENABLE pin will pull up to 5.0V with 1.8mA source capability, and the module will be enabled. Output disable: ENABLE may be pulled down externally in ‐ order to disable the module. Pull down resistance should be less than 235Ω to SGND. Fault detection flag: The ENABLE 5.0V voltage source is internally turned off when a fault condition is latched. Operating Mode Select: If TRIM is pulled below 0.45 V during the first startup after VIN is applied, Remote Sense / Slave operation is selected. Otherwise, Adaptive Loop operation is selected. This selection persists until VIN is removed from the part, and is not changed by fault or disable events. ENABLE control should be implemented using an open collector configuration. It is not recommended to drive this pin externally. Output Voltage Trim: Sets the output voltage of the PRM in Adaptive Loop operation. If TRIM is permitted to pull up to 3.20 V or higher during start up, trim is disabled, and the output is set to the nominal of 48V. If TRIM is held between 1.00 V to 2.75 V during start up, trim is enabled, and the output is scaled by a factor of 20 resulting in an output voltage range of 20 V to 55 V. This selection persists until the PRM is restarted with the ENABLE pin, or due to fault auto-recovery. VAUX: Auxiliary Voltage Source AL: Adaptive Loop (Adaptive Loop operation) Use this pin to power external devices with a non-isolated 9.0 V supply, with up to 5 mA load capability, switched with ENABLE input. Do not place a capacitor over 0.04 µF on this pin. This input pin allows you to set the Adaptive Loop load line. Every volt on this pin represents 1.0 Ω of positive output slope. There is an internal 10 kΩ pullup resistor to VCC_INT. If AL is permitted to pull up to 3.20 V or higher during start up, the Adaptive Loop load line is disabled. This selection persists until the PRM is restarted with the ENABLE pin, or due to fault auto-recovery. SGND: Signal Ground This is a low current pin which provides a Kelvin connection to the PRM’s internal signal ground. Use this pin as the ground reference for external circuitry and signals to avoid voltage drops caused by high currents on power returns. In array configurations, SGND pins should be star connected at a single point. A series resistor (~1Ω) to the star location is recommended to decouple return currents. VT: VTM Temperature (Adaptive Loop operation) This pin is used in the Adaptive Loop compensation algorithm to account for the VTM output resistance variation as a function of temperature. The VTM TM pin provides this voltage, scaled as the temperature in K (Kelvin) divided by 100, so 25 °C is 2.98 V. Leave disconnected or pull below 1.9V to disable. The adjustment is fixed at 0.3 %/°C relative to the value at 25 °C - 25 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 REF: Reference (Adaptive Loop operation) This output pin allows you to monitor the internal reference voltage in Adaptive Loop operation. During normal operation it represents the output voltage scaled by a factor of 20. In Adaptive Loop operation this pin is for monitoring purposes only and should not be driven or loaded externally. and the equivalent output resistance vary as a function of line, load and output voltage. As the load increases, the powertrain pole moves to higher frequency. As a result, the closed loop crossover frequency will be the highest at full load and lowest at minimum load. Figure 24 shows a reference AC small-signal model. + REF_EN: Reference Enable (Remote Sense operation) VIN In Remote Sense operation this pin outputs a regulated 3.25V, 4mA voltage source. It is enabled only after successful start up of the PRM powertrain REF_EN is intended to power the output current transducer and also the voltage reference for the external control loop. Powering the reference generator with REF_EN helps provide a controlled start up, since the output voltage of the system is able to track the reference level as it comes up. - CONTROL NODE (Remote Sense operation) In Remote Sense operation, this is the input to the modulator which determines the powertrain timing and ultimately the module output power. An internal 0.5 mA current sink is always active. The bi-directional buffer between CONTROL NODE and the modulator has two states. In normal operation, CONTROL NODE will be above the 0.79 V switching threshold, and will drive the modulator through the buffer. An internal 7.4V clamp determines the maximum output power that can be requested of the modulator. When CONTROL NODE falls below 0.79 V, the converter will stop switching. An internal circuit clamps the modulator input to 0.79 V, and a buffer will source up to 2.5 mA out of the pin at that clamp level. For this reason, the output impedance of the amplifier driving CONTROL NODE must be taken into account. A rail-to-rail operational amplifier with low output impedance is always recommended. + + VCN · GCN RCN ICN_Low COUT_INT rEQ_OUT - - SHARE (Adaptive Loop and Slave operation) This bus sets the output current level for all the PRM modules when operating in an array (master-slave configuration). Connect them together among the modules in the shared bus. One PRM should be configured as a master by connecting TRIM for Adaptive Loop operation. All other PRMs should be configured as slaves by pulling their respective TRIM pins low. This pin can be used to monitor the error voltage externally. 0 to 100% load is represented by a voltage between 0.79 V and 7.40. CIN_INT rEQ_IN Figure 24 – PRM48BH480[x]250A00 AC small signal model IFB: Current Feedback (Remote Sense operation) In Remote Sense operation, IFB is the input for the module output overcurrent protection and current limit features. A voltage proportional to the powertrain output current must be applied to IFB in order for overcurrent protection to operate properly. If the IFB voltage exceeds the IFB pin’s overcurrent protection threshold, the powertrain will stop switching. If the IFB voltage falls below the overcurrent protection threshold within tBLANK time, then the powertrain will immediately resume switching. Otherwise a fault is detected. The current limit threshold for the IFB pin is set lower than the protection threshold. When the IFB pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amplifier which overrides the modulator input maximum level. This causes the powertrain to maintain a constant output current. The bandwidth of this current limit integrator is significantly slower than that of the CONTROL NODE input. Therefore this current limit cannot be used in lieu of properly compensating the (external) control loop to avoid exceeding maximum current or power ratings for the device. The powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). Both the modulator gain - 26 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 DESIGN GUIDELINES The PRM48BH480[x]250A00 regulator is specifically designed to provide a controlled Factorized Bus distribution voltage for powering downstream VTM Transformer — fast, efficient, isolated, low noise Point-of-Load (POL) converters. The PRM48BH480[x]250A00 can be configured for two operating modes depending on the type of regulation required. To configure the part for Adaptive Loop operation, leave the TRIM pin disconnected, or apply a voltage/resistance within the specified range. The operating mode is detected and latched during the first start up after VIN is applied. This selection persists until VIN is removed from the part, and is not changed by fault or disable events. Changing the operating mode can only be done by removing VIN. DESIGN GUIDELINES (Adaptive Loop operation) In Adaptive Loop operation the regulation circuitry is enabled within the device and regulates the voltage at the output terminals. The PRM48BH480[x]250A00 has a programmable Adaptive Loop load line which can be used to compensate for downstream VTM output resistance allowing for precise point of load regulation without the need for remote sensing. In Remote Sense operation, the internal regulation circuitry is disabled and the voltage regulation circuitry is provided externally allowing for remote sensing directly at the point of load. In certain applications Remote Sense operation can improve regulation accuracy, and allow for operating with high amounts of load capacitance and optimizing load transient response. In Adaptive Loop operation, the internal voltage control circuitry is enabled and the voltage at the output terminals is regulated. The part is nominally set to provide a fixed 48V output, and the TRIM pin can be used to adjust the output over the range of 20 V to 55 V. When used with a VTM, the AL pin provides ability to program an Adaptive Loop load line to compensate for the output resistance (ROUT) of a downstream VTM, while the VT pin provides temperature compensation to account for changes in the VTM ROUT over temperature. Trim Mode and Output Trim Control (Adaptive Loop operation) Operating Mode Selection The operating mode is selected through use of the TRIM pin. When the part is first enabled after VIN is applied, the TRIM voltage is sampled. The TRIM pin has an internal pull up resistor to VCC_INT, so unless external circuitry pulls the pin voltage lower, it will float up to VCC_INT. If TRIM is pulled lower than 0.45V during the first startup after VIN is applied, the part will be configured for Remote Sense / Slave operation, where the internal voltage regulation circuitry is disabled. In this case, for all subsequent operation the part will output a voltage dependent on the SHARE / CONTROL NODE voltage provided externally (either from an external regulation circuit or master PRM). In Adaptive Loop operation, during any start up and after ENABLE transitions high, the TRIM pin voltage is sampled to determine if trim is active or inactive. If the sampled TRIM voltage is higher than 3.20V then the PRM will disable trim. In this case, for all subsequent operation the output voltage will be programmed to the nominal output of 48V and the TRIM pin will be ignored during normal operation. If the sampled TRIM voltage is between 1.0 V and 3.10 V then the PRM will activate trim mode and it will remain in this mode as long as the PRM is operating. This selection persists until the PRM is restarted with the ENABLE pin, or due to fault auto-recovery. To configure the part for Remote Sense or Slave operation, connect the TRIM pin to SGND. It is recommended to make this connection through a 0Ω jumper for troubleshooting purposes. If the sampled TRIM voltage is higher than 0.55V during the first startup after VIN is applied, then the part will be configured for Adaptive Loop operation, and the internal voltage regulation circuitry is enabled. The PRM will output a voltage dependent on the TRIM voltage, and will remain in this mode for as long as VIN is applied. - 27 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 PRM VOUT vs VTRIM VCCINT 60 60 Recommended Range 10K 50 50 40 40 30 30 20 20 Output Voltage (V) VTRIM Micro Controller RTRIM SGND 10 10 Figure 25: TRIM Connection Unspecified Operation The output as a function of VTRIM is defined by equation (1) for 1.00 V ≤ VTRIM ≤ 2.75 V, and allows for an output voltage ranging from 20V to 55V. The TRIM pin is pulled up internally to VCC_INT thorough a 10 kΩ resistor. VTRIM can be actively set with a DAC that is ground referenced to SGND. VTRIM can be passively set by connecting a resistor, RTRIM, from TRIM to SGND such that the voltage divider made with VCC_INT and the 10 kΩ pull up yields the desired VTRIM. The formula for calculating this resistor is provided in Equation (1a). ∙ 20 (1) ∙ ∙ ∙ _ _ _ 0 0 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 TRIM Pin Voltage (V) Output Voltage (V) AT Pin Resistor (KΩ) Figure 26: PRM VOUT vs. VTRIM When trim is enabled the voltage at this pin is sampled at 120 µs intervals to determine the trim level. The output can be dynamically trimmed during normal operation, however it is not recommended to use this pin in an external analog feedback loop. Refer to Table 1 for a summary of the TRIM pin functionality and the recommended voltage/resistance that should be applied to this pin. (1a) For 1.00 V≤ VTRIM ≤ 2.75 V Where VOUT_SET is the desired output voltage The output voltage tranfer function saturates for applied TRIM voltages above approximately 2.75V as illustrated in Figure 26 to prevent the output from being driven above its rated output voltage. When TRIM is set lower than 1.00 V the output voltage is not specified and stable operation is not guaranteed. TRIM PIN FUNCTION SUMMARY Operating State VTRIM RTRIM Remote Sense / Slave Operation <0.45V <1 kΩ Adaptive Loop Operation >0.55V[2] > 3 kΩ [2] Trim Active VOUT = 20* VTRIM 1.00 V to 2.75 V 4.32 kΩ to 49.9 kΩ Trim Inactive VOUT = 48V >3.2 V >10 MΩ Adaptive Loop Operation Trim Mode [2] It TRIM Pin Resistor (KΩ) TRIM Detected and Latched After application of VIN when ENABLE first transitions high After application of VIN when ENABLE first transitions high At every start up when ENABLE transitions high Table 1: TRIM Pin Function Summary is not recommended to configure TRIM with a voltage less than 1.00V in Adaptive Loop operation - 28 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 accordingly increases the output voltage of the PRM in order to regulate the PRM’s output resistance to a fixed negative resistance, RLL_AL, settable by way of the AL pin. RLL_AL should be sized to exactly cancel the ROUT of the VTM at 25°C. The AL engine is also able to account for the positive temperature coefficient of ROUT by way of its VT pin which will be explained shortly. Adaptive Loop Compensation (Adaptive Loop operation) A factorized power system naturally has a DC load line associated with it since the regulator stage (PRM) is positioned before the isolation and voltage transformation stage (VTM.) Consider for a moment a factorized power system that has the following parameters: VF = 40V KVTM=1/4 ROUT_VTM =10mohm @ 25°C PRM and VTM Output Voltage Adaptive Loop Comensation Example 3 2 Output Voltage %Difference From Nominal (%) At no load the output voltage at the load will be equal to 10V (VF • KVTM). With increasing load current, the output voltage at the load will drop at a rate proportional to the VTMs ROUT. It should be noted that the ROUT has a positive temperature coefficient and so the DC load line changes with temperature. If the presence of this load line is acceptable for your application, then the PRM can be configured by way of the TRIM pin alone. Please refer to the Trimming the Output Voltage section for details. In this case both the AL and VT pins should be left open. 1 Compensated VTM Output 0 Adaptive Loop compensation brings output into regulation ‐1 ‐2 ‐3 0 20 40 60 80 100 Load Current (%) VTM VOUT (Uncompensated) PRM VOUT VTM Vout (Regulated) Figure 27: Adaptive Loop Compensation Illustration If the presence of this load line is undesirable, the load line can be eliminated by way of the PRM’s Adaptive Loop (AL) engine. The AL engine measures the output current of the PRM and PRM ENABLE ON/OFF CONTROL VAUX SGND RTRIM RAL VTM REF/ REF_EN TRIM AL VC SHARE/ CONTROL NODE VT VOUT VTM Startup Pulse VC Adaptive Loop Temperature Feedback TM PC IFB VINVIN 38V36V to 55V to 75V +OUT COUT SGND +IN +OUT -IN -OUT +IN LF VF: 20V to 55V CIN CF SGND -OUT -IN PRIMARY GND SECONDARY ISOLATION BOUNDRY SEC_GND SGND Figure 28: PRM-VTM Adaptive Loop Example - 29 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Setting the Adaptive Loop Load Line (Adaptive Loop operation) To determine an appropriate value for the compensation slope (RLL_AL) it helps to reflect the VTM’s output resistance to the input side of the VTM. A resistance on the output side of the VTM is scaled by the VTMs transformer ratio (KVTM) squared as defined by equation (2): _ _ _ ∙ _ (2) When AL is enabled, the voltage at this pin is sampled at 120 µs intervals to determine the load line. The load line can be adjusted during normal operation, however it is not recommended to use this pin in an external analog feedback loop. Where ROUT_VTM is the VTM output resistance at 25°C KVTM is the VTM transformer ratio VIN/VOUT For our hypothetical VTM from above (with KVTM = 1/4 and ROUT_VTM = 10mΩ) the output resistance reflected over to the input would be equal to 160 mΩ. For this example, RLL_AL should be set to -160 mΩ to approximately cancel at 25°C the inherent load line from the VTM. Adaptive Loop Temperature Compensation (Adaptive Loop operation) RLL_AL is set by the voltage difference between the AL pin and SGND pin, VAL, per the following formula: R _ V ∙ 1.0 Ω/V (3) VAL ≤ 3.10V Where VAL is the voltage on the AL pin VAL is sampled by a 10-bit ADC, whose input is connected to VCC_INT through a 10 kΩ pull up resistor. This pull up disables the AL engine when the AL pin is left open. VAL can be actively set with a DAC that is ground referenced to SGND. VAL can be passively set by connecting a resistor, RAL, from AL to SGND such that the voltage divider made with VCC_INT and the 10 kΩ pull up yields the desired VAL. The formula for calculating this resistor is provided in Equation (4). ∙ _ (4) VCCINT Similar to TRIM, AL is sampled during every start up to determine if the Adaptive Loop load line is enabled or disabled. If the AL pin is allowed to pull up to 3.20V or higher during start up, then then the PRM will disable the Adaptive Loop load line as long as the PRM remains operating. In this case, for all subsequent operation the output voltage will be remain at the set voltage, and the AL pin will be ignored. This selection persists until the PRM is restarted with the ENABLE pin, or due to fault auto-recovery. By connecting the VT pin of the PRM to the VTM’s TM pin, the PRM is able to monitor the internal temperature of the VTM. Knowing the VTM’s internal temperature and the temperature coefficient of the VTM’s ROUT, which is preprogrammed into the PRM’s microcontroller, the AL engine is able to scale the nominal value of RLL_AL (set by the AL pin) to track the VTM’s ROUT over temperature. In this way the output resistance of the PRM can be tuned to cancel the output resistance of the VTM with the addition of a single resistor across the AL pin and a connection of the VTM’s TM pin to the PRM’s VT pin. The VTM TM voltage is equal to the VTM internal sensed temperature in Kelvin divided by 100. For a temperature range of -55 °C to 125 °C the TM voltage will range from 2.18 V to 3.98 V. The Adaptive Loop temperature compensation is pre-programed into the internal microcontroller and is 0.3 %/°C assuming the VT pin is connected to the TM pin of a compatible VTM The TM pin has an internal pull down to SGND, and temperature compensation is disabled for VT voltages less than 1.9V. To disable temperature compensation, leave the VT pin unconnected and open circuit. When disabled, the temperature defaults 25 °C. 10K AL VAL Micro Controller RAL SGND Figure 29: AL Connections - 30 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Stability Considerations and External Capacitance (Adaptive Loop operation) 20K VT 2.18V to 3.98V (-55C to 125C) In Adaptive Loop operation, the internal voltage regulation is enabled which has a pre-determined, fixed compensation network. The compensation is designed to be stable over a fixed set of operating and load conditions including load capacitance. VTM TM MICRO CONTROLLER 60.4k Besides internal output capacitors, external output capacitors also contribute to the closed loop frequency response, thus should be identified and understood, in order to maintain the control loop stability. This includes capacitance placed directly on the PRM output, as well as capacitance on the output of any downstream VTM (if used) reflected to its input. SGND Figure 30: VT Connections PRM and VTM Output Voltage Adaptive Loop With Temperature Compensation Output Voltage %Difference From Nominal (%) 3 Figure 32 illustrates the requirements for external capacitors of both the capacitance and ESR value. As shown in Figure 32 (a), the maximum capacitance value of ceramic capacitor is 25 µF, and the capacitance of a combination of ceramic and electrotype capacitors needs to be less than 47 µF. As shown in Figure 32 (b) and (c), the ESR value of electrotype capacitors needs to be between 0.1 Ω and 1.0 Ω; the ESR value of ceramic capacitors needs to be between 2 mΩ and 200 mΩ. 2 Compensation slope increases with temperature based on VT feedback 1 Compensated VTM Output 0 VTM ROUT increases with temperature ‐1 ‐2 ‐3 0 20 40 60 80 100 Load Current (%) VTM VOUT: 25C (Uncompensated) VTM Vout (Regulated) VTM VOUT: ‐55C (Uncompensated) VTM VOUT: 100C (Uncompensated) PRM VOU: 25C (VT = 2.98V) PRM VOUT: ‐55C (VT = 2.18V) PRM VOUT: 100C (VT = 3.73V) Figure 31: Adaptive Loop Temperature Compensation Illustration The discussion thus far only considered the case where the AL engine is used to compensate for the ROUT of the VTM. The AL engine can be more generally used to account for distribution resistances in both the factorized bus and the VTM’s output distribution bus. For more information on how to apply the AL engine towards this end please contact Vicor’s Applications Engineering department. CCER (uF) CCER ≤ 25 25 C CER + CEL < 47 ESR (Ohm) 0.1 ≤ ESR ≤ 1 1 ESR (Ohm) 0.02 ≤ ESR ≤ 0.2 0.2 0.02 0.1 22 47 ESREL CEL(uF) ESRCER (a) Maxium Capacitance limits (b) ESREL requirements (c) ESRCER requirements Figure 32: Output Capacitance Limits - 31 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Current Limit (Adaptive Loop operation) In Adaptive Loop operation, the current limit is controlled by the internal microcontroller. The current limit approximates a “brick-wall” limit where the output current is prevented from crossing the current limit threshold by reducing the output voltage. The current limit threshold is pre-programmed into the internal microcontroller and cannot be changed externally. When the internal sensed current crosses the current limit threshold, the current limit will be activated after the detection time tLIM_SUPV. Once activated, the microcontroller will reduce the error amplifier reference voltage (represented by REF) in order to maintain the output current at the limit value. Current limit is able to reduce the output down to VOUT_UVP, below which the device will shut down do to output under voltage protection. Figure 34: PRM Example 100% to 10% Load Transient Response, Adaptive Loop Load Line Disabled Soft Start Timing and Start up (Adaptive Loop operation) When the Adaptive Loop load line is enabled, the voltage will recover to the value determined by the set point and Adaptive Loop load line settings as illustrated in Figure 35. In Adaptive Loop operation, the PRM has an internal soft start sequence which is initiated at every start up. This allows the PRM to start into fully discharged load capacitance. The soft start sequence ramps the output by modulating the error amplifier reference voltage (REF). The result is that the PRM output will rise at a controlled rate until the final voltage setpoint is reached. The total ramp time is typically 1.8ms independent of the output trim level. This soft start ramp time is preprogrammed into the microcontroller and cannot be changed externally. Load Transient Response (Adaptive Loop Operation) In Adaptive Loop operation, response time is dependent on the internal compensation. When the Adaptive Loop load line is disabled, the PRM output voltage will recover to the initial set value as illustrated in Figure 33 and Figure 34. Figure 35: PRM Example 10% to 100% Load Transient Response, Adaptive Loop Load Line Enabled, VAL = 1.25V Actual response times are model dependent and will change based on the load step magnitude, load capacitance and operating conditions. Because the compensation is fixed internally the load transient response cannot be altered for Adaptive Loop operation. In order to improve the load transient response performance, the part can be configured for Remote Sense operation with an external voltage control loop optimized for the specific intended operating conditions. Remote Sense operation is described in a later section. Figure 33: PRM Example 10% to 100% Load Transient Response, Adaptive Loop Load Line Disabled - 32 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Arrays (Adaptive Loop / Slave operation) In Adaptive Loop operation a master-slave configuration is used for arrays. Up to 5 PRMs of the same type may be placed in parallel to expand the power capacity of the system. One PRM is designated as the master and contains the active control loop which considers control pin inputs and drives SHARE. The other PRMs listen to SHARE and act as slave powertrains only. The following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. One PRM must be designated as a master through configuring the TRIM pin voltage within the recommended range. All other PRMs must be designated as slave PRMs by tying TRIM pins to SGND. It is recommended to make this connection through a 0Ω jumper for troubleshooting purposes. All PRMs in the array must be powered from a common power source so that the input voltage to each PRM is the same. The IN pins of all PRMs must be connected together. An independent fuse for each PRM +IN connection is required to maintain safety certifications (see Fusing section). An independent inductor for each PRM +IN connection is recommended when used in an array, to control circulating currents among the PRM inputs and reduce the impact of beat frequencies. Mismatches in both inductance, and resistance from the common power source to each PRM should be minimized. ENABLE pins must be connected together for start up synchronization and proper fault response of the array. SHARE pins must be connected together to enable sharing. The bandwidth requirements of SHARE are low enough that the bus can be considered a lumped element, rather than a transmission line, and so star connections to the master PRM with stubs, as well as daisy chain connections are permitted. The resistances between slave unit SHARE pins and the master’s should be well matched, to avoid introducing additional sharing mismatches. The SHARE bus should not be routed under any PRM. SHARE bus parasitic capacitance to +IN or +OUT should be minimized. SGND of the master PRM is the reference for all control loop functions. The SGND pins of each slave PRMs should be connected to the SGND reference node on the board through a 1 Ω resistor. When operating within an array, the master PRM is rated for full power while the slave PRMs are de-rated to the array rated power and current values provided for Slave operation(POUT_ARRAY,IOUT_ARRAY). The number of PRMs required to achieve a given array capacity must consider these de-ratings to avoid overstressing any PRM in the array. Adaptive Loop design procedures above will hold for an array, in general, although some parameters must be scaled against the number of PRMs in the system. Arrays of more than 5 PRMs may be possible through use of external circuitry. Please contact Vicor Applications for assistance with array sizing above 5 units. - 33 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 DESIGN GUIDELINES (Remote Sense operation) In Remote Sense operation, the PRM48BH480[x]250A00 is an intelligent powertrain module designed to fully exploit external output voltage feedback and current sensing sub-circuits. These two external circuits are illustrated in Figure 36, which shows an example of the PRM in a standalone application with local voltage feedback and high side current sensing. In general, these circuits include a precision voltage reference, an operational amplifier which provides closed loop feedback compensation, and a high side current sense circuit which includes a shunt and current sense IC. The following design procedures refer to the circuit shown in Figure 36. Setting the operation) Output Voltage Level (Remote In Remote Sense operation, the internal current sensing is disabled, and an external current sense amplifier must be implemented to provide feedback to the IFB pin. The current limit and overcurrent protection set points are linked, and scale together against the current sense shunt, and the gain of the current sense amplifier. The output of the current sense IC provides the IFB voltage which has VIFB_IL and VIFB_OC thresholds for the two functions respectively. The set points are therefore defined by: I IL Sense V IFB _ IL RS GCS (6) and The output voltage setpoint is a function of the voltage reference and the output voltage sense ratio. With reference to Figure 36, R1 and R2 form the output voltage sensing divider which provides the scaled output voltage to the negative input of the error amplifier; a dedicated reference IC provides the reference voltage to the positive input of the error amplifier. Under normal operation, the error amplifier will keep the voltages at the inverting and non-inverting inputs equal, and therefore the output voltage is defined by: VOUT Vref Setting the Output Current Limit and Overcurrent Protection Level (Remote Sense operation) R1 R 2 R2 I OC VIFB _ OC RS GCS (7) where GCS is the gain of the current sense amplifier. (5) Note that the component R1 will also factor into the compensation as described in a later section. It is important to apply proper slew rate to the reference voltage rise when the control loop is initially enabled. The recommended range for reference rise time is 1 ms to 9 ms. The lower rise time limit will ensure optimized modulator timing performance during start up, and to allow the current limit feature (through IFB pin) to fully protect the device during power-up. The upper rise time limit is needed to guarantee a sufficient factorized bus voltage is provided to any downstream VTM input before the end of the VC pulse. - 34 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 C2 C1 R3 + Vref R2 R1 CONTROL PR NODE VAUX VS F1 +IN RS +OUT TM PRM Regulator CIN_EXT CIN_INT -IN IF REF_EN RE IFB Vref COUT_EXT COUT_INT -OUT SG SGND I sense IC Vref IC Figure 36: Remote Sense Example - 35 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Control Loop Compensation Requirements (Remote Sense operation) The system poles and zeros of the closed loop can then be defined as follows: In order to properly compensate the control loop, all components which contribute to the closed loop frequency response should be identified and understood. Figure 24 shows the AC small signal model for the module. Modulator DC gain GCN and powertrain equivalent resistance rEQ_OUT are shown. These modeling parameters will support a design cutoff frequency up to 50kHz. Standard Bode analysis should be used for calculating the error amplifier compensation and analyzing the closed loop stability. The recommended stability criteria are as follows: 1) Phase Margin > 45º : for the closed loop response, the phase should be greater than 45º where the gain crosses 0dB. 2) Gain Margin > 10dB : The closed loop gain should be lower than -10dB where the phase crosses 0º. 3) Gain Slope = -20dB/decade : The closed loop gain should have a slope of -20dB/decade at the crossover frequency. The compensation characteristics must be selected to meet these stability criteria. Refer to Figure 37 for a local sense, voltage-mode control example based on the configuration in Figure 36. In this example, it is assumed that the maximum crossover frequency (FCMAX) has been selected to occur between B and C. Type-2 compensation (Curve IJKL) is sufficient in this case. The following data must be gathered in order to proceed: Modulator Gain GCN: See Figures 18, 19, 20 Powertrain equivalent resistance rEQ: See Figures 18, 19, 20 Internal output capacitance: see Figure 13 External output capacitance value In the case of ceramic capacitors, the ESR can be considered low enough to push the associated zero well above the frequency of interest. Applications with high ESR capacitor may require a different type of compensation, or cascade control. Powertrain pole, assuming the external capacitor ESR is negligible: RCOUT _ EXT rEQ _ OUT RLOAD Main pole frequency: FP rEQ _ OUT RLOAD 1 2 π rEQ _ OUT RLOAD rEQ _ OUT RLOAD Compensation Mid‐Band Gain: G MB 20 log R3 R1 (8) Compensation Zero: FZ1 COUT _ INT COUT _ EXT 1 2 π R 3 C1 (9) Compensation Pole: FP 2 1 R C C 2 π 3 1 2 C1 C2 and for FP2>>FZ1 (C1 + C2 ≈ C1): FP 2 - 36 - 1 2 R3 C 2 (10) Rev. 1.0 11/2012 PRM48BH480 X 250A00 PRM open loop response, and is where the minimum crossover frequency FCMIN occurs. Based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore FCMIN will occur where EFG is equal and opposite of GMB. C1 can be selected using Equation (9) so that FZ1 occurs prior to FCMIN. Midband Gain Design: R1,R3 (Remote Sense operation) With reference to Figure 37: curve ABC is the: minimum output voltage in the application maximum input voltage expected in the application maximum load PRM open loop response, and is where the maximum crossover frequency occurs. In order for the maximum crossover frequency to occur at the design choice FCMAX, the compensation gain must be equal and opposite of the powertrain gain at this frequency. For stability purposes, the compensation should be in the Mid-band (J-K) at the crossover. Using Equation (8), the mid-band gain can be selected appropriately. High Frequency operation): Pole Design: C2 (Remote Sense Using Equation (10), C2 should be selected so that FP2 is at least one decade above FCMAX and prior to the gain bandwidth product of the operational amplifier (10MHz for this example). For applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. Compensation Zero Design :C1 (Remote Sense operation): With reference to Figure 37: curve EFG is the: maximum output voltage in the application minimum input voltage expected in the application minimum load in the application Open Loop Gain vs. Frequency 80 60 40 Gain (dB) 20 I Application's op-amp G·BW Compensation Gain F E PRM Open Loop Min Load B A PRM Open Loop Max Load J K L FCMIN 0 FCMAX -20 C G -40 Frequency, Log scale (y-intercept is application specific) Figure 37 – Reference asymptotic Bode plot for the considered system - 37 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Arrays (Remote Sense operation) In Remote Sense operation up to 10 PRMs of the same type may be placed in parallel to expand the power capacity of the system. All PRMs within the array are configured for Remote Sense operation and are driven by an external control circuit which considers the control inputs and drives the CONTROL NODE bus. The following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. All PRMs must be configured for Remote Sense operation by tying TRIM pins to SGND. It is recommended to make this connection through a 0Ω jumper for troubleshooting purposes. All PRMs in the array must be powered from a common power source so that the input voltage to each PRM is the same. An independent fuse for each PRM +IN connection is required to maintain safety certifications (see Fusing section). An independent inductor for each PRM +IN connection is recommended when used in an array, to control circulating currents among the PRM inputs and reduce the impact of beat frequencies. Mismatches in both inductance, and resistance from the common power source to each PRM should be minimized. ENABLE pins must be connected together for start up synchronization and proper fault response of the array. Reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules’ REF_EN pins have reached their operational voltage levels. A single external control circuit must be implemented as described in the Remote Sense operation design guidelines. The control circuit should drive the CONTROL NODE bus. CONTROL NODE pins must be connected together to enable sharing. The bandwidth requirements of CONTROL NODE are low enough that the bus can be considered a lumped element, rather than a transmission line, and so star connections as well as daisy chain connections are permitted. Each PRM must have its own local current shunt and current sense circuitry to drive its IFB pin. The resistances between CONTROL NODE pins should be well matched, to avoid introducing additional - 38 - sharing mismatches. The CONTROL NODE bus should not be routed under any PRM. Parasitic capacitance to +IN or +OUT should be minimized. One PRM should be designated to provide the SGND reference, VAUX, and REF_EN voltages for the external circuitry. The SGND pins of all other PRMs should be connected to the SGND reference node on the board through a 1 Ω resistor. When operating within an array, the PRMs are derated to the array rated power and current values provided for Remote Sense operation (POUT_ARRAY, IOUT_ARRAY). The number of PRMs required to achieve a given array capacity must consider these de-ratings to avoid overstressing any PRM in the array. When using VAUX to power external circuitry, total current draw including CONTROL NODE sink currents must be taken into account to ensure the maximum VAUX current is not exceeded. Arrays of more than 5 PRMs may require additional circuitry to provide the required source current. Contact Vicor Applications Engineering for more information. Rev. 1.0 11/2012 PRM48BH480 X 250A00 DESIGN GUIDELINES (General Operation) k k The following guidelines are general guidelines that apply to any mode of operation. Vout Vout d d FPA System Considerations There are a few system level design considerations that should be carefully considered when using a PRM and VTM to implement a Factorized Power Architecture (FPA) system The VC pin of the PRM should be directly connected to the VC pin of the VTM. The PRM and VTM coordinate the soft start sequence of the FPA system through this connection. If the VC pins are not connected the VTM will not start up. When the PRM is ready to start up, it applies a voltage on VC, which enables and powers the VTM’s powertrain. The PRM then proceeds to ramp up its output voltage. After approximately 10ms, VC returns to 0V and the VTM can then derive power directly from the factorized bus provided that the factorized bus voltage is above the minimum specified VTM operating input voltage when the VC pulse expires. All VTM faults latch the VTM powertrain off. Input power to the system as a whole must be recycled or the PRM should be disabled and enabled by way of its ENABLE pin in order to restart the system. It is recommended that the voltage on the factorized bus return to zero before the PRM is re-enabled. Otherwise the soft start of the system may be compromised. A RL filter should be placed between the PRM and VTM to locally isolate switching ripple currents that can interfere with module operation. It is important that the inductance have an impedance that is much greater than that of the PRM output capacitance and VTM input capacitance at the switching frequencies of the devices. A resistor should be placed in shunt to this inductor to dampen the resultant LC tank. For most cases 100nH in parallel with 10Ω is sufficient to isolate the switching ripple currents. Iout time time Iout time time (a) without Adaptive Loop (b) with Adaptive Loop Figure 38 – load step response example and “droop” vs. “kick” definition. (a) with Adaptive Loop; (b) without Adaptive Loop. 2 k ln d m 100 2 k 2 ln d (11) Burst Mode Operation: At light loads, the PRM will operate in a burst mode due to minimum timing constraints. An example burst operation waveform is illustrated in Figure 39. For very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. In this case the error amplifier will periodically drive SHARE/CONROL NODE below the switching threshold in order to maintain regulation. Switching will cease momentarily until the error amplifier once again drives SHARE/CONTROL NODE voltage above the threshold. Verifying Stability: A load step transient response can be used in order to estimate stability. Figure 38 illustrates an example of a load step response. Equation (11) can be used to predict the phase margin based on the ratio of the “kick” to “droop” (as defined in Fig. 38). Figure 39 – light load burst mode of operation - 39 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variable. The variability depends on many factors including input voltage, output voltages, load impedance, and error amplifier output impedance. In burst mode, the gain of the SHARE/CONTROL NODE input to the plant which is modeled in the previous sections is time varying. Therefore the small signal analysis cannot be directly applied to burst mode operation. Input and Output filter design Figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the PRM at full load under various input and output voltages conditions. Figure 13 provides the effective internal capacitance of the module. A conservative estimate of input and output peakpeak voltage ripple at nominal line and trim is provided by equation (12): QTOT V C INT I FL 0.4 f SW C EXT (12) QTOT is the total input (Fig. 14) or output (Fig. 15) charge per switching cycle at full load, while CINT is the module internal effective capacitance at the considered voltage (Fig. 13) and CEXT is the external effective capacitance at the considered voltage. Input filter stability The PRM can provide very high dynamic transients. It is therefore very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. For this purpose, the converter dynamic input impedance magnitude rEQ _ IN is provided in Figures 21, 22, 23. It is recommended to provide adequate design margin with respect to the stability conditions illustrated in the previous sections. Inductive source and local, external input decoupling capacitance with negligible ESR (i.e.: ceramic type) The voltage source impedance can be modeled as a series RLINE LLINE circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified: Rline (C IN _ INT Lline C IN _ EXT ) rEQ _ IN Rline rEQ _ IN (13) (14) It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance (14). However, RLINE cannot be made arbitrarily low otherwise equation (13) is violated and the system will show instability, due to under-damped RLC input network. Inductive source and local, external input decoupling capacitance with significant RCIN_EXT ESR (i.e.: electrolytic type) In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor LLINE. Notice that, the high performance ceramic capacitors CIN_INT within the PRM should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be rEQ _ IN RC IN _ EXT (15) Lline rEQ _ IN C IN _ EXT RC IN _ EXT (16) Equation (16) shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT) – the system will be under-damped and may even become destabilized. Again, an octave of design margin in satisfying (15) should be considered the minimum. Layout Considerations Application Note AN:005 details board layout recommendations using V•I Chip components, with details on good power connections, reducing EMI, and shielding of control signals and techniques to reference them to SGND. Avoid routing control signals (ENABLE, TRIM, AL etc.) directly underneath the PRM. It is critical that all control signals (aside from VC and VT) are referenced to SGND, both for routing and for pull-down and bypassing purposes. VC and VT provide control and feedback from a VTM, and must be referenced to – OUT of the PRM (-IN of the VTM) SGND is connected to –IN internally to the PRM. SGND should not be tied to any other ground in the system. - 40 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 Input Fuse Recommendations A fuse should be incorporated at the input to each PRM, in series with the +IN pin. A 10A or smaller input fuse (Littlefuse® NANO2® 451/453 series) is required to safety agency conditions of acceptability. Always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. Thermal Considerations V•IchipTM products are multi-chip modules whose temperature distribution varies greatly for each part number as well as with the input / output conditions, thermal management and environmental conditions. Maintaining the top of the PRM48BH480[x]250A00 case to less than 100ºC will keep all junctions within the V•I Chip module below 125ºC for most applications. The percent of total heat dissipated through the top surface versus through the J-lead is entirely dependent on the particular mechanical and thermal environment. The heat dissipated through the top surface is typically 60%. The heat dissipated through the J-lead onto the PCB board surface is typically 40%. Use 100% top surface dissipation when designing for a conservative cooling solution. It is not recommended to use a V•I Chip module for an extended period of time at full load without proper heat sinking. - 41 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 PRODUCT OUTLINE DRAWING AND REOMMENDED LAND PATTERN - 42 - Rev. 1.0 11/2012 PRM48BH480 X 250A00 REVISION HISTORY Revision 1.0 Date 11/12/2012 Description Final approved datasheet for initial release - 43 - Page Number(s) All Rev. 1.0 11/2012 PRM48BH480 X 250A00 Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. Specifications are subject to change without notice. Vicor’s Standard Terms and Conditions All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request. Product Warranty In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the “Express Limited Warranty”). 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Intellectual Property Notice Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: [email protected] Technical Support: [email protected] - 44 - Rev. 1.0 11/2012