PR045A480T040FP

PR045A480T040FP
®
PRM™
Regulator
S
C
NRTL
US
FEATURES
PRODUCT DESCRIPTION
•
•
•
•
•
•
•
The VI BRICK® PRM™ Regulator is a high efficiency converter, operating
from a 38 to 55 Vdc input to generate a regulated 5 to 55 Vdc output.
The ZVS buck – boost topology enables high switching frequency (~1
MHz) operation with high conversion efficiency. High switching
frequency reduces the size of reactive components enabling power
density up to 519 W/in3.
45 V (38 to 55), non-isolated ZVS buck-boost regulator
5 to 55 V adjustable output range
Building block for high efficiency DC-DC systems
400W output power in 2.08 in2 footprint
97% typical efficiency, at full load
519 W/in3 (31 W/cm3) Power Density
Flexible “Remote Sense” architecture optimizes
regulation / feedback loop design to fit application
requirements
• Current feedback signal allows dynamic adjustment of
current limit setpoint
• 3.61 MHrs MTBF (MIL-HDBK-217Plus Parts Count)
• 100 °C baseplate operation
TYPICAL APPLICATIONS
•
•
•
•
•
•
High Efficiency Server Processor and Memory Power
High Density ATE System DC-DC Power
Telecom NPU and ASIC Core Power
LED Drivers
High Density Power Supply DC-DC Rail Outputs
Non-isolated Power Converters
In a Factorized Power Architecture™ system, the PR045A480T040FP and
downstream VTM™ current multiplier minimize distribution and
conversion losses in a high power solution.
An external control loop and current sensor maintain regulation and
enable flexibility both in the design of voltage and current compensation
loops to control of output voltages and currents.
In combination, VI BRICK® PRMs and VTMs form a complete DC-DC
converter subsystem offering all of the unique benefits of Vicor’s
Factorized Power Architecture (FPA); high density, low noise operation,
architectural flexibility, extremely fast transient response, elimination of
bulk capacitance at the Point of Load (POL); in a thermally enhanced
package.
APPLICATION DIAGRAM
PRM
VTM
VTM
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 1 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
1.0 ABSOLUTE MAXIMUM RATINGS
The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. All
voltages are specified relative to SG unless otherwise noted. Positive pin current represents current flowing out of the pin.
PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MIN
MAX
UNIT
-0.3
10.5
V
±10
mA
IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
V
RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±10
mA
VC to –OUT . . . . . . . . . . . . . . . . . . . . . .
-0.5
5.7
V
VC to –OUT . . . . . . . . . . . . . . . . . . . . . .
±1
mA
+OUT to –OUT . . . . . . . . . . . . . . . . . . .
62
V
Output Current . . . . . . . . . . . . . . . . . . .
PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.3
TM . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+IN to–IN . . . . . . . . . . . . . . . . . . . . . . . .
-1
VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5
VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MIN
MAX
UNIT
±100
mA
-0.5
5.7
V
-0.3
5
V
SG . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-1
18
V
±1.8
A
62
V
±11
A
10.5
V
Operating Temperature (baseplate) . .
-40
100
°C
±100
mA
Storage Temerature . . . . . . . . . . . . . . .
-40
125
°C
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 2 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions, TC = 25 ºC and output voltage from 20 V to 55 V, unless otherwise noted.
Boldface specifications apply over the temperature range of -40 ºC < TC < 100 ºC (T-grade).
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
38
0.001
45
55
1000
2.4
4
8.5
V
V/ms
W
POWER INPUT SPECIFICATION
Input Voltage Range
VIN Slew Rate
No Load Power Dissipation
Input Quiescent Current
Input Current
Input Capacitance (Internal)
Input Capacitance (Internal) ESR
VIN
dVIN /dt
PNL
IQC
IIN_DC
CIN_INT
RCin
0 < VIN < 18 V
PC HIGH, VN = 45 V
PC LOW, VN = 45 V
IOUT = 8.33 A, VIN = 38 V, VOUT = 48 V
Effective value, VIN = 45 V (see Fig. 5)
4.5
10.9
4
1.5
11.0
mA
A
µF
mΩ
POWER OUTPUT SPECIFICATION
Output Voltage Range
VOUT
55
V
Output Current
IOUT
See Figure 16, SOA
8.33
A
Output Power
POUT
See Figure 16, SOA
400
W
Output Turn-ON Delay
TON
IOUT_SHARE
Current Sharing Difference
(exclusive of current limit)
Efficiency
η
Output Discharge current
IOD
Output Voltage Ripple
VOUT_PP
Output Inductance (Parasitic)
Output Capacitance (Internal)
Output Capacitance (Internal) ESR
LOUT_PAR
COUT_INT
RCout
5
From VIN applied, PC floating
From PC pin release, VIN applied, TOFF expired
Equal input, output and PR voltage at full load;
VIN = 45 V, VOUT = 48 V
Equal input, output and PR voltage at full load;
Over line and trim, with 25 °C < TC < 100 °C
but negligible part-part temp mismatch
Equal input, output and PR voltage at full load;
Over line and trim, with 25° C < TC < 100 °C and
<= 75 °C part-part temp. mismatch (worst case)
Nominal line, full load, VOUT = 48 V
50% load and VOUT = 48 V; over temperature
>50% load; over temperature
Section 4.0
COUT_EXT = 0 F, IOUT = 8.33 A, VIN = 45 V,
VOUT = 48 V, 20 MHz BW
Frequency @ 1 MHz, Simulated J-Lead model
Effective value, VOUT = 48 V (see Fig. 20)
48
20
96.5
94.8
90.0
µs
±10
%
±24
%
±35
%
97.4
%
%
%
mA
13
960
1500
1.9
4
1.5
mV
nH
µF
mΩ
POWERTRAIN PROTECTIONS
Input Undervoltage Turn-ON
VIN_UVLO
Input Undervoltage Turn-OFF
VIN_UVLO
Input Overvoltage Turn-ON
VIN_OVLO
Input Overvoltage Turn-OFF
VIN_OVLO
Overcurrent (IF) and Input
Over/Undervoltage Blanking Time
Output Overvoltage Threshold
Instantanous powertrain shutdown,
Instantanous powertrain shutdown,
latched after TBLNK
TBLNK
VOUT_OVLO+
Thermal Shutdown Setpoint
TJ_OTP
Overtemperature, Output Overvoltage
TPROT
35.75
latched after TBLNK
Instantaneous, latched shutdown
Instantaneous, latched shutdown; guaranteed by
design, not production tested; VTM = 4.03 V
37.13
V
31.97
33.56
V
55.91
57.24
V
58.44
59.91
V
50
120
150
µs
55.25
56.57
59.04
V
130
and PC Shutdown Response Time
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
°C
2
µs
Rev. 1.0
05/2012
Page 3 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
POWERTRAIN PROTECTIONS CONT.
Short Circuit Vout Threshold
VSC_VOUT
3.0
V
Short Circuit Vout Recovery Threshold
VSC_VOUTR
4.0
V
Short Circuit Vpr Threshold
VSC_VPR
7.2
V
Short Circuit Vpr Recovery Threshold
VSC_VPRR
7.1
V
20
ms
0.1
ms
Short Circuit Timeout
TSC
Short Circuit Recovery Time
TSCR
Output Power Limit
PPROT
Short circuit fault latched after VSC_VOUT
and VSC_VPR thresholds persist for this time
400
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
W
Rev. 1.0
05/2012
Page 4 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions, TC = 25 ºC and output voltage from 20 V to 55 V, unless otherwise noted.
Boldface specifications apply over the temperature range of -40 ºC < TC < 100 ºC (T-grade).
PRIMARY CONTROL
PC
• The PC pin enables and disables the PRM
• In PRM array configurations, PC pins should be connected in order to synchronize startup.
• It is a weak pull-down during any fault mode excluding short circuit. PC is a strong pull-down to SG if a short circuit fault is latched.
SIGNAL TYPE
Analog Output
STATE
MIN
TYP
MAX
5
5.3
PC Voltage
VPC
4.7
PC Available Current
IPC_OP
1.8
PC Source Current
IPC_EN
After TOFF
Minimum Time to Start
TOFF
Section 5.0
Digital Input / Output
Standby
PC Enable Threshold
VPC_EN
PC Disable Threshold
VPC_DIS
PC Resistance (External)
RPC_EXT
Fault
PC Sink Current to SG
IPC_SC
Fault
PC Sink Current to ~1V
IPC_FAULT
[Short Circuit Fault]
[All other Faults]
VOLTAGE SOURCE
CONDITIONS / NOTES
Regular
Startup
Digital Output
SYMBOL
Operation
Startup
Digital Output
ATTRIBUTE
1.75
V
mA
90
10.0
UNIT
µA
18.0
30.0
ms
2.50
3.20
V
2.40
Resistance to SG required
V
300
to disable the PRM
Short circuit, PC voltage 1 V or above
Temperature, over- and
Ω
25
mA
10
µA
undervoltage, overcurrent
VS
• Intended to power feedback components and/or auxiliary circuits.
• 9 V, 5 mA regulated voltage source
• With > 5% output load, VS ripple typically 100 mV
SIGNAL TYPE
STATE
Regular
ATTRIBUTE
SYMBOL
MIN
TYP
MAX
VS Voltage
VVS
8.55
9.00
9.45
VS Available Current
IVS
5
VS Voltage Ripple
VVS_PP
UNIT
V
mA
IOUT = 0A, CVS_EXT = 0. Maximum
Operation
Analog Output
CONDITIONS / NOTES
specification includes
100
400
mV
0.04
µF
powertrain operation in burst mode.
VS Capacitance
Transition
(External)
VS Fault Response Time
REFERENCE ENABLE
CVS_EXT
TFR_VS
From fault recognition to VS = 1.5 V
30
µs
RE
• RE signals successful startup and a powertrain that is ready for operation
• Regulated, delayed voltage source intended to power the feedback circuit voltage reference and current monitor
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
RE Voltage
VRE
Regular
RE Available Current
IRE
Operation
RE Regulation
%RE
Analog Output
Transition
CONDITIONS / NOTES
MIN
TYP
MAX
UNIT
3.0
3.3
3.6
V
8.0
across load and temperature
mA
±2.5
%
RE Voltage Ripple
VRE_PP
in burst mode
100
mV
PC to RE Delay
TPC_RE
Fault detected
100
µs
RE Capacitance
(External)
VS to RE Delay
0.1
CRE_EXT
TVS_RE
VS = 8.1 V to RE high, VIN > VIN_UVLO-
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
1
µF
ms
Rev. 1.0
05/2012
Page 5 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
CONTROL NODE
PR
• Modulator control node input
• Sinks constant current when externally driven in active range
• Sources current when pulled below active range
SIGNAL TYPE
STATE
ATTRIBUTE
PR Voltage Active
Range
Analog Input
Regular
Operation
CURRENT FEEDBACK
SYMBOL
CONDITIONS / NOTES
VPR
MIN
TYP
0.79
PR Source Current
IPR
VPR ≤ 0.79 V
PR Sink Current
IPR_LOW
VPR > 0.79 V
PR Resistance to SG
RPR
250
500
MAX
UNIT
7.40
V
2
mA
750
93.3
µA
kΩ
IF
• A voltage proportional to the PRM output current must be supplied externally to the IF pin in order for the device to properly protect overcurrent
events and to enable output current limit (clamp)
• Overcurrent protection trip will cause instantaneous powertrain disable, latched after TBLNK
SIGNAL TYPE
STATE
ATTRIBUTE
Current Limit (clamp)
Threshold
Regular
Analog Input
TEMP MONITOR
Operation
Overcurrent Protection
Threshold
SYMBOL
VIF_IL
IIF_OC
IF Input Impedance
RIF
Current Limit Bandwidth
BWIL
CONDITIONS / NOTES
VIN = 45 V; TJ = 25 °C
Not Production Tested; Guaranted
MIN
TYP
MAX
UNIT
1.90
2.00
2.10
V
2.58
2.69
2.80
V
2.11
2.13
2.15
by Design; TJ = 25 °C
2
kΩ
kHz
TM
• The TM pin monitors the internal temperature of the PRM analog control IC.
• "Power Good" flag to verify that the PRM is operating
SIGNAL TYPE
STATE
Regular
Analog Output
Digital Output [Fault Flag]
Operation
Fault
ATTRIBUTE
TM Voltage
VTM
TM Voltage reference
VTM_AMB
TM Voltage Ripple
VVS_PP
TM Available Current
ITM
TM Gain
ATM
TM Disabled Current
or Standby
SIGNAL GROUND
SYMBOL
ITM_DIS
CONDITIONS / NOTES
MIN
Full temperature range
2.12
TJ = 27 °C
2.94
Powertrain in burst mode
TYP
MAX
UNIT
4.04
V
3.00
3.06
V
200
mV
100
µA
DC state with TM Voltage +/- 0.5 V.
10
mV/°C
0.0
mA
This is a high impedance state.
SG
• All control signals must be referenced to this pin, with the exception of VC
• SG is internally connected to -IN and -OUT
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
Analog Input / Output
Any
Max Allowable Current
ISG
VTM CONTROL
VC
CONDITIONS / NOTES
MIN
TYP
-100
MAX
UNIT
100
mA
MAX
UNIT
• Pulsed voltage source used to power and synchronize downstream VTM
• If not used, must be resistively terminated to -OUT
SIGNAL TYPE
Analog Output
STATE
ATTRIBUTE
SYMBOL
Startup
VC Voltage
VVC
RVC_EXT = 68Ω
CONDITIONS / NOTES
MIN
13
VC Available Current
IVC
VC < = 14 V, VIN > 20 V
200
VC duration
TVC
VC Slew Rate
dVVC/dt
TYP
7
RVC = 1kΩ
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
V
mA
10
20
16
ms
V/µs
Rev. 1.0
05/2012
Page 6 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
4.0 FUNCTIONAL BLOCK DIAGRAM
+Vin
+Vout
Vcc
PC
PR Vout
Cin
Vcc
3.3V
Linear
Regulator
Internal
Vcc
Regulator
-Vin
Cout
3.3V
Q3
Q1
uC 8051
RE
L
-Vout
16V
+Vout
9V
Q4
Q2
Output
Discharge
(OD)
8.2V
PR
Modulator
PR
Var. Vclamp
[7.2-0.8]V
93.3k
Enable
2.5mA Min
VTM Vc Start up pulse
0.5mA
14V
VC
10ms
Vcc
100uA
Q
Q
SET
CLR
Fault Logic
TOFF
delay
S
Instant
latch
R
R
Vout
(OV)
5V
2mA max
3V
RE
Latch after
120us
RE
3.3V
Vin
(OV, UV)
Vs
9V
0.01uF
Enable
PC
10uA
PC
2.4V
SG
Current Limit
Overtemperature
Protection
TM
3 V @ 27°C
VIF_IL
Overcurrent
Protection
Temperature
dependent voltage
source
IF
2130
Vref
(130°C)
VIF_OC
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 7 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
5.0 HIGH LEVEL FUNCTIONAL STATE DIAGRAM
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
Application of
Vin
PC HIGH
and
Toff expiry
▶
STANDBY
SEQUENCE
PC: 10uA to LOW
▶
▶
▶
Toff Timeout
PC: 90uA to HIGH
Powertrain Stopped
Overtemp or Output
OVP
PC HIGH
and
Ton expiry
▶
STARTUP
SEQUENCE
PC: 1.8mA to HIGH
Ton timeout;
VC Pulse;
Powertrain Active
Delayed RE
Fault
removed
TBLNK
expiry
▶
BLANKING
PC: 1.8mA to HIGH
TBLNK Timeout
Powertrain Paused
▶
PC
falling
edge
Input OVP,
Input UVP,
or
OverCurrent Prot
▶
SUSTAINED
OPERATION
PC: 1.8mA to HIGH
Powertrain Active
▶
Short Removed:
Vout > VSC_VOUTR
or
Vpr < V SC_VPR_R
Vout < 1 V
And
TSCR expiry
Short Circuit:
Vout < VSC_Vout
and
Vpr > V SC_Vpr
▶
SHORT
CIRCUIT
PC: 1.8mA to HIGH
TSCR Timeout
Powertrain Stopped
IOD Output Discharge
PC
falling
edge
▶
OUTPUT DISCHARGE
PC: pulsed 25mA drive
LOW
TSC
expiry
▶
▶
TSC Timeout
Powertrain Active
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 8 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
6.0 TIMING DIAGRAMS
Module Inputs are shown in blue; Module Outputs are shown in brown; Timing diagrams assumes the following:
•
•
•
•
Single PRM (no array)
VS powers error amplifier
RE powers voltage reference and output current transducer
IOUT is sensed, scaled, and fed back to IF pin such that IF = 2.00 V at full load
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 9 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
6.0 TIMING DIAGRAMS CONT.
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 10 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
7.0 APPLICATIONS CHARACTERISTICS
The following figures present typical performance at TC = 25 ºC, unless otherwise noted. See associated figures for general trend data.
1
Power Dissipation [W]
6
5
4
3
2
1
0.8
0.6
0.4
0.2
0
0
40
42
44
46
48
50
52
54
38
40
42
44
Input Voltage [V]
25 ºC
100 ºC
Efficiency & Power Dissipation
VOUT= 20 V TCASE = -40 ºC
16
14
12
10
8
6
4
2
0
1
2
3
4
5
6
7
8
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
45
45
8
6
4
2
VIN:
1
2
12
10
8
6
4
3
4
5
6
7
8
Power Dissipation [W]
Efficiency [%]
18
14
2
38
38
45
55
4
5
6
7
8
9
38
45
38
55
45
55
Efficiency & Power Dissipation
VOUT= 20 V TCASE = 25 ºC
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
16
14
12
10
8
6
4
2
9
0
55
VIN:
1
2
3
4
5
6
7
8
9
Load Current [A]
Load Current [A]
VIN:
3
Figure 4 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 48 V, TCASE = -40 °C
16
1
16
10
55
Efficiency & Power Dissipation
VOUT= 55 V TCASE = -40 ºC
0
100 ºC
12
0
Figure 3 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 20 V, TCASE = -40 °C
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
25 ºC
Load Current [A]
38
55
54
14
9
Efficiency [%]
38
52
Efficiency & Power Dissipation
VOUT= 48 V TCASE = -40 ºC
Load Current [A]
VIN:
50
Figure 2 — No load power dissipation vs. VIN, module disabled
Power Dissipation [W]
Efficiency [%]
Figure 1 — No load power dissipation vs. VIN, module enabled
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
48
-40 ºC
TCASE :
Efficiency [%]
-40 ºC
TCASE :
46
Input Voltage [V]
Power Dissipation [W]
38
Power Dissipation [W]
Power Dissipation [W]
No Load Power Dissipation vs. Line
Module Disabled, PC=Low
No Load Power Dissipation vs. Line
Module Enabled - Nominal VOUT
45
Figure 5 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 55 V, TCASE = -40 °C
38
45
55
38
45
55
Figure 6 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 20 V, TCASE = 25 °C
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 11 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
16
14
12
10
8
6
4
Efficiency [%]
2
0
1
2
3
4
5
6
7
8
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
9
16
14
12
10
8
6
4
1
0
2
45
38
55
45
VIN:
55
Efficiency & Power Dissipation
VOUT= 20 V TCASE = 100 ºC
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
16
14
12
10
8
6
4
2
0
1
2
3
4
5
6
7
8
38
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
9
45
45
9
45
38
55
45
55
16
10
8
6
4
2
1
2
3
4
5
6
7
8
9
Efficiency & Power Dissipation
VOUT= 55 V TCASE = 100 ºC
38
45
38
55
45
55
Figure 10 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 48 V, TCASE = 100 °C
16
14
12
10
8
6
VPR vs. Case Temperature
VIN = 45 V; VOUT = 48 V
6.5
18
Power Dissipation [W]
Efficiency [%]
8
12
VIN:
55
Figure 9 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 20 V, TCASE = 100 °C
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
7
Load Current [A]
38
55
6
14
0
6
6.16
6.20
6.04
5.5
VPR [V]
38
5
Efficiency & Power Dissipation
VOUT= 48 V TCASE = 100 ºC
Load Current [A]
VIN:
4
Figure 8 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 55 V, TCASE = 25 °C
Power Dissipation [W]
Efficiency [%]
Figure 7 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 48 V, TCASE = 25 °C
Efficiency [%]
38
3
Load Current [A]
Load Current [A]
VIN:
18
Power Dissipation [W]
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
Efficiency & Power Dissipation
VOUT= 55 V TCASE = 25 ºC
Power Dissipation [W]
Efficiency & Power Dissipation
VOUT= 48 V TCASE = 25 ºC
Power Dissipation [W]
Efficiency [%]
7.0 APPLICATIONS CHARACTERISTICS CONT.
5
4.5
4.70
4.70
4.52
4
0
1
2
3
4
5
6
7
8
9
4
-40
-20
0
Load Current [A]
VIN:
38
45
55
38
20
40
60
80
100
Temperature [ºC]
45
55
Figure 11 — Total efficiency and power dissipation vs. VIN and IOUT,
VOUT = 55 V, TCASE = 100 °C
IOUT:
4.17
8.33
Figure 12 — Typical control node voltage vs. TCASE, IOUT;
VIN = 45 V, VOUT = 48 V
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 12 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
7.0 APPLICATIONS CHARACTERISTICS CONT.
Powertrain switching frequency and periodic
output charge vs. input voltage - Full load
fSW [kHz]
36
f sw
1000
32
975
28
950
24
925
20
900
16
875
12
µC
850
Total output charge
per switchingcycle [μC]
1025
8
4
825
0
800
38
40
42
44
46
48
50
52
54
56
Input Voltage [V]
VOUT:
Figure 13 — Typical output voltage ripple waveform, TCASE = 30 ºC, VIN =
45 V, VOUT = 48 V, IOUT = 8.33 A, no external capacitance.
400
8.33
320
20
6.25
240
900
16
875
12
4.17
160
µC
8
4
825
2.08
80
0.00
0
800
42
44
46
48
50
52
54
0
5
56
10
15
55
20
20
25
30
35
40
45
50
55
60
Output Voltage [V]
Input Voltage [V]
VOUT:
Output Power [W]
24
925
40
48
10.42
Output Current [A]
950
Total output charge
per switchingcycle [μC]
fSW [kHz]
32
28
38
20
DC Safe Operating Area
975
850
55
48
36
f sw
1000
20
Figure 14 — Powertrain switching frequency and periodic output charge
vs. VIN, VOUT; IOUT = 8.33 A
Powertrain switching frequency and periodic
output charge vs. input voltage - Full load
1025
55
55
48
20
48
Current
Figure 15 — Powertrain switching frequency and periodic input charge vs.
VIN, VOUT; IOUT = 8.33 A
Figure 16 — DC Output Safe Operating Area
DC modulator gain and powertrain equivalent
output resistance vs. output current - VOUT = 20V
DC modulator gain and powertrain equivalent
output resistance vs. output current - VOUT = 55V
14
8
12
250
10
Power
20
18
200
2
100
0
r eq_out
-2
GPR [dB]
4
req_out [W]
GPR [dB]
150
16
Gpr
6
14
10
12
8
10
8
6
50
4
0
2
6
r eq_out
req_out [W]
Gpr
4
2
-4
0
1
2
3
4
5
6
7
8
9
0
0
1
2
Output Current [A]
VOUT:
38
45
55
3
4
5
6
7
8
9
Output Current [A]
38
45
55
Figure 17 — Powertrain characteristics vs. IOUT; Resistive load, VOUT =
55 V, various VIN
VOUT:
38
45
55
38
45
55
Figure 18 — Powertrain characteristics vs. IOUT; Resistive load, VOUT = 20 V,
various VIN
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 13 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
7.0 APPLICATIONS CHARACTERISTICS CONT.
Gpr
10
90
9
80
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
GPR [dB]
8
60
6
50
4
40
30
2
req_out [Ω]
70
20
r eq_out
0
10
0
-2
0
1
2
3
4
5
6
7
8
Input Capacitance [µF]
12
Effective internal input (CIN_INT ) and output
(COUT_INT ) capacitance vs. applied voltage
0
0
9
0
5
10
15
20
25
Output Current [A]
VOUT:
38
45
45
55
Figure 19 — Powertrain characteristics vs. IOUT; Resistive load, VOUT = 48 V,
various VIN
Cin
40
45
50
55
Cout
Powertrain equivalent input resistance
vs. output current - VOUT = 55V
16
360
14
320
12
280
10
240
[W]
200
req_in
Output Power [W]
35
Figure 20 — Effective internal input and output capacitance vs. voltage –
ceramic type
Output Power vs. VPR
VIN = 45V, VOUT = 48V, TC=25ºC
400
30
Voltage [V]
38
55
9
Output Capacitance [µF]
DC modulator gain and powertrain equivalent
output resistance vs. output current - VOUT = 48V
160
120
8
6
4
80
2
40
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0
7.0
1
2
Typical min
Nominal
5
6
7
8
9
45
55
Figure 22 — Magnitude of powertrain dynamic input impedance vs. VIN,
IOUT; VOUT = 55 V
Powertrain equivalent input resistance
vs. output current - VOUT = 20V
Powertrain equivalent input resistance
vs. output current - VOUT = 48V
20
80
18
70
16
14
req_in [W]
60
req_in [W]
4
38
VIN:
Typical max
Figure 21 — Output Power vs. VPR; VIN = 45 V, VOUT = 48 V, TCASE = 25ºC
90
3
Output Current [A]
PR Voltage [V]
50
40
30
12
10
8
6
20
4
10
2
0
0
0
1
2
3
4
5
6
7
8
9
0
1
2
Output Current [A]
VIN:
38
45
3
4
5
6
7
8
9
Output Current [A]
55
Figure 23 — Magnitude of powertrain dynamic input impedance vs. VIN, IOUT;
VOUT = 20 V
VIN:
38
45
55
Figure 24 — Magnitude of powertrain dynamic input impedance vs. VIN, IOUT;
VOUT = 48 V
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 14 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
8.0 GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions, TC = 25 ºC and output voltage from 20 V to 55V, unless otherwise noted.
Boldface specifications apply over the temperature range of -40 ºC < TC< 100 ºC (T-grade).
ATTRIBUTE
SYMBOL
MECHANICAL
Length
Width
Height
Volume
Weight
Pin material
Underplate
Pin finish
L
W
H
Vol
W
CONDITIONS / NOTES
TJ
TC
SOLDERING
See application note
MAX
UNIT
mm/[in]
mm/[in]
mm/[in]
cm3/[in3]
g
100
200
150
300
µin
-40
-40
125
100
°C
°C
Ws/°C
°C/W
°C/W
°C/W
°C/W
23.8
8.8
3.0
0.40
0.36
Human Body Model,
"JEDEC JESD 22-A114C.01"
Charged Device Model,
"JEDEC JESD 22-C101D"
ESD Rating
TYP
48.6 / [1.91]
27.7 / [1.09]
9.5 / [0.37]
12.79 / [0.77]
30.4
No heatsink
C10200, copper full hard
Nickel
Pure matte tin,
whisker resistant chemistry
THERMAL
Operating junction temperature
Operating case temperature
Thermal capacity
Baseplate to ambient*
Baseplate to ambient, 1000 LFM*
Baseplate to sink; flat, greased surface
Baseplate to sink; flat, thermal pad
ASSEMBLY
MIN
1000
V
400
V
Soldering Methods and
Procedure for Vicor Power Modules
RELIABILITY AND AGENCY APPROVALS
Telcordia Issue 2 - Method I Case 1;
Ground Benign, Controlled
MTBF
Agency approvals / standards
2.27
MIL-HDBK-217 Plus Parts Count
25º C Ground Benign, Stationary,
3.56
Indoors / Computer Profile
CTUVUS
CE Mark
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
MHrs
MHrs
*Data based on part tested when mounted to Vicor evaluation board.
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 15 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
9.0 PRODUCT OUTLINE DRAWING AND RECOMMENDED PCB FOOTPRINT
Baseplate - Slotted Flange
Figure 25 — Module outline
Recommended PCB Pattern
(Component side shown)
Figure 26 — PCB mounting specifications
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 16 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
10.0 PRODUCT DETAILS AND DESIGN GUIDELINES
10.1 Control pins description and characteristics
Control node (PR) is the input to the control node which determines
the powertrain timing and ultimately the module output power (Figure
21). An internal 0.5 mA current sink is always active. The bi-directional
buffer between PR and the control node has two states. In normal
operation, PR will be above the 0.79 V switching threshold, and will
drive the control node through the buffer. An internal 7.4 V clamp
determines the maximum output power that can be requested of the
modulator.
When PR falls below 0.79 V, the converter will stop switching. An
internal circuit clamps the modulator input control node to 0.79 V, and
a buffer will source up to 2.5 mA out of the pin at that clamp level.
For this reason, the output impedance of the amplifier driving PR must
be taken into account. A rail-to-rail operational amplifier with low
output impedance is always recommended.
The powertrain small signal (plant) response consists of a single pole
determined by the load resistance, the powertrain equivalent output
resistance, and the total output capacitance (internal and external to
the module).
Both the modulator gain and the equivalent output resistance vary as a
function of line, load and output voltage, as shown in Figures 17, 18
and 19. As the load increases, the powertrain pole moves to higher
frequency.
As a result, the closed loop crossover frequency will be the highest at
full load and lowest at minimum load. Figure 31 shows a reference AC
small-signal model.
Current feedback (IF) is the input for the module output overcurrent
protection and current limit features (see functional block diagram in
section 4.0). A voltage proportional to the powertrain output current
must be applied to IF in order for overcurrent protection to operate
properly.
If the IF voltage exceeds the IF pin’s overcurrent protection threshold,
the powertrain will stop switching. If the IF voltage falls below the
overcurrent protection threshold within TBLANK time, then the
powertrain will immediately resumes switching. Otherwise a fault is
latched.
The current limit threshold for the IF pin is set lower than the
protection threshold. When the IF pin average voltage exceeds the
current limit threshold, an internal integrator will activate a clamp
amplifier which overrides the modulator input maximum level. This
causes the powertrain to maintain a constant output current.
The bandwidth of this current limit integrator is significantly slower
than that of the PR control node input. Therefore this current limit can
not be used in lieu of properly compensating the (external) PR control
loop to avoid exceeding maximum current or power ratings for the
device.
If the IF pin is not driven, it must be resistively terminated to SG. A
1kΩ resistor to SG is recommended in this case.
Figure 27 — PR045A480T040FP AC small signal model
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 17 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
In general, these circuits include a precision voltage reference, an
operational amplifier which provides closed loop feedback
compensation, and a high side current sense circuit which includes a
shunt and current sense IC.
VTM Control (VC) pin supplies an initial VCC voltage to downstream
VTMs, enabling them and synchronizing their startup with the PRM.
The VCC voltage is a pulse, typically 10 ms duration at 14 V.
If VC is not loaded by a VTM, it must be terminated with a 1kΩ
resistor to –VOut.
The following design procedures refer to the circuit shown in Figure
32.
Primary Control (PC) is both an input and an output. It can provide
the following features:
10.2.1 Setting the output voltage level
The output voltage setpoint is a function of the voltage reference and
the output voltage sense ratio. With reference to Fig. 26, R1 and R2
form the output voltage sensing divider which provides the scaled
output voltage to the negative input of the error amplifier; a dedicated
reference IC provides the reference voltage to the positive input of the
error amplifier. Under normal operation, the error amplifier will keep
the voltages at the inverting and non-inverting inputs equal, and
therefore the output voltage is defined by:
• Delayed start: upon application of voltage (>UVLO) to the module
power input and after TOFF, the PC pin will source a constant 90 µA
current.
• Output disable: PC may be pulled down externally in order to disable
the module. Pull down resistance should be less than 300 Ω to SG.
• Fault detection flag: The PC 5 V voltage source is internally turned
off when a fault condition is latched. Note that aside from the Short
Circuit fault condition, PC does not have significant current sinking
capability. Therefore in the case of an array of PRMs with
interconnected PC pins, PC does not in general reflect the fault state of
all PRMs.
The common PC line will not disable neighboring modules when a
fault is detected except for a latched Output Short Circuit fault.
Conversely any unit in the array latching a Short Circuit fault will
disable the array for TSCR.
Temperature Monitor (TM) pin outputs a voltage proportional to the
absolute temperature of the converter analog control IC. It can be used
to accomplish the following functions:
• Monitor the control IC temperature: The gain and setpoint of TM are
such that the temperature, in Kelvin, of the PRM controller IC is equal
to the voltage on the TM pin scaled by 100. (i.e. 3.0 V = 300 K = 27
ºC).
• Closed loop thermal management at the system level (e.g. variable
speed fans or coolant flow)
• Fault detection flag: The TM voltage source is turned off as soon as a
fault is detected. For system monitoring purposes (microcontroller
interface) faults are detected on falling edges of TM.
Reference Enable (RE) pin outputs a regulated 3.3 V, 8 mA voltage
source. It is enabled only after successful startup of the PRM
powertrain (see chapters 5.0 and 6.0.)
RE is intended to power the output current transducer and also the
voltage reference for the control loop. Powering the reference
generator with RE helps provide a controlled startup, since the output
voltage of the system is able to track the reference level as it comes
up.
Voltage Source (VS) pin outputs a gated (e.g. mirrors PC status), nonisolated, regulated 9 V, 5 mA voltage source. It can be used to power
external control circuitry; it always leads RE.
Signal Ground (SG) pin provides a Kelvin connection to the PRM’s
internal signal ground. It should be used as the reference for PR, TM,
IF, and should return all PC, VS and RE pin currents. In array
configurations with common ground control circuits, a series resistor
(~1Ω) is recommended in order to decouple power and signal current
returns.
10.2 Control circuit requirements and design procedure
The PR045A480T040FP is an intelligent powertrain module designed to
fully exploit external output voltage feedback and current sensing subcircuits. These two external circuits are illustrated in Figure 32, which
shows an example of the PRM in a standalone application with local
voltage feedback and high side current sensing.
VOUT = Vref •
R1+R2
R2

Note that the component R1 will also factor into the compensation as
described in a later section.
It is important to apply proper slew rate to the reference voltage rise
when the control loop is initially enabled. The recommended range for
reference rise time is 1 ms to 9 ms. The lower rise time limit will ensure
optimized modulator timing performance during startup, and to allow
the current limit feature (through IF pin) to fully protect the device
during power-up. The upper rise time limit is needed to guarantee a
sufficient factorized bus voltage is provided to any downstream VTM
input before the end of the VC pulse.
10.2.2 Setting the output current limit and overcurrent
protection level
The current limit and overcurrent protection set points are linked, and
scale together against the current sense shunt, and the gain of the
current sense amplifier. The output of the current sense IC provides the
IF voltage which has VIF_IL and VIF_OC thresholds for the two functions
respectively. The set points are therefore defined by:
IIL =
VIF_IL
RS • GCS
and
IOC =
VIF_OC
RS • GCS
where GCS is the gain of the current sense amplifier.
10.2.3 Control loop compensation requirements
In order to properly compensate the control loop, all components
which contribute to the closed loop frequency response should be
identified and understood. Figure 31 shows the AC small signal model
for the module.
Modulator DC gain GPR and powertrain equivalent resistance rEQ_OUT
are shown. These modeling parameters will support a design cut-off
frequency up to 50 kHz.
Standard Bode analysis should be used for calculating the error
amplifier compensation and analyzing the closed loop stability.
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 18 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
The recommended stability criteria are as follows:
10.2.4 Midband Gain Design (R1,R3):
1) Phase Margin > 45º : for the closed loop response, the phase should
be greater than 45º where the gain crosses 0 dB.
With reference to Figure 31: curve ABC is the:
2) Gain Margin > 10 dB : The closed loop gain should be lower than 10 dB where the phase crosses 0º.
• maximum input voltage expected in the application
3) Gain Slope = -20 dB/decade : The closed loop gain should have a
slope of -20 dB/decade at the crossover frequency.
The compensation characteristics must be selected to meet these
stability criteria. Refer to Figure 31 for a local sense, voltage-mode
control example based on the configuration in Figure 32. In this
example, it is assumed that the maximum crossover frequency (FCMAX)
has been selected to occur between B and C. Type-2 compensation
(Curve IJKL) is sufficient in this case.
• minimum output voltage in the application
• maximum load
PRM open loop response, and is where the maximum crossover
frequency occurs. In order for the maximum crossover frequency to
occur at the design choice FCMAX, the compensation gain must be
equal and opposite of the powertrain gain at this frequency. For
stability purposes, the compensation should be in the Mid-band (J-K) at
the crossover. Using Equation [1], the mid-band gain can be selected
appropriately.
The following data must be gathered in order to proceed:
• Modulator Gain GPR: See Figures 17, 18, 19
• Powertrain equivalent resistance rEQ: See Figures 17, 18, 19
• Internal output capacitance: see Figure 20
• External output capacitance value In the case of ceramic capacitors,
the ESR can be considered low enough to push the associated zero
well above the frequency of interest. Applications with high ESR
capacitor may require a different type of compensation, or cascade
control.
The system poles and zeros of the closed loop can then be defined as
follows:
• Powertrain pole, assuming the external capacitor
ESR can be neglected:
RCOUT_EXT <<
rEQ_OUT • RLOAD
rEQ_OUT • RLOAD
• Main pole frequency:
1
FP ≈
2π •
rEQ_OUT • RLOAD
rEQ_OUT + RLOAD
•
(C
OUT_INT
)
+ COUT_EXT
Figure 28 — Control circuit example
• Compensation Mid-Band Gain:
GMB = 201og
R3
R1
[1]
With reference to Figure 31: curve EFG is the:
• maximum output voltage in the application
• Compensation Zero:
1
FZ1 =
2π • R3• C1
• minimum input voltage expected in the application
[2]
2π •
• minimum load in the application
PRM open loop response, and is where the minimum crossover
frequency FCMIN occurs. Based on stability criteria, the compensation
must be in the mid-band at the minimum crossover frequency,
therefore FCMIN will occur where EFG is equal and opposite of GMB. C1
can be selected using Equation [2] so that FZ1 occurs prior to
• Compensation Pole:
FP2 =
10.2.5 Compensation Zero Design (C1):
1
R3 • C1• C2
C1+ C2
FCMIN.
• and for FP2>>FZ1 (C1 + C2 ≈ C1):
FP2 ≈
1
2π • R3• C2
[3]
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 19 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
In the absence of a network analyzer, a load step transient response
can be used in order to estimate stability.
Figure 30 illustrates an example of a load step response.
Equation [4] can be used to predict the phase margin based on the
ratio of the “kick” to “droop” (as defined in Fig. 28).
Open Loop Gain vs. Frequency
80
k
ln )
(
d
Φ ≈ 100
k
ln
√ ( d)
2
60
I
Application's op-amp G·BW
Compensation Gain
m
2
[4]
+ π2
40
Gain (dB)
E
F
PRM Open Loop Min Load
20
A
10.3 Burst Mode Operation:
B
PRM Open Loop Max Load
J
K
L
FCMIN
0
FCMAX
-20
C
-40
G
Frequency, Log scale
(y-intercept is application specific)
At light loads, the PRM will operate in a burst mode due to minimum
timing constraints. An example burst operation waveform is illustrated
in Figure 31.
For very light loads, and also for higher input voltages, the minimum
time power switching cycle from the powertrain will exceed the power
required by the load. In this case the external error amplifier will
periodically drive PR below the switching threshold in order to maintain
regulation.
Switching will cease momentarily until the error amplifier once again
drives PR voltage above the threshold.
Figure 29 — Reference asymptotic Bode plot for the considered system
10.2.6 High Frequency Pole Design (C2):
Using Equation [3], C2 should be selected so that FP2 is at least one
decade above FCMAX and prior to the gain bandwidth product of the
operational amplifier (10 MHz for this example). For applications with a
higher desired crossover frequency the use of a high gain bandwidth
product amplifier may be necessary to ensure that the real pole can be
set at least one decade above the maximum crossover frequency.
10.2.7 Verifying Stability:
The preferred method for verifying stability is to use a network
analyzer, measuring the closed loop response across various lines and
Reference asymptotic Bode plot for the considered systemload
conditions.
Figure 31 —light load burst mode of operation
Note that during the bursts of switching, the powertrain frequency is
constant, but the number of pulses as well as the time between bursts
is variable. The variability depends on many factors including input
voltage, output voltages, load impedance, and external error amplifier
output impedance.
In burst mode, the gain of the PR input to the plant which is modeled
in the previous sections is time varying. Therefore the small signal
analysis can not be directly applied to burst mode operation.
10.4 Input and Output filter design
Figures 14 and 15 provide the total input and output charge per cycle,
as well as switching frequency, of the PRM at full load under various
input and output voltages conditions.
Figure 30 — load step response example and “droop”
vs. “kick” definition
Figure 20 provides the effective internal capacitance of the module. A
conservative estimate of input and output peak-peak voltage ripple at
nominal line and trim is provided by equation [5]:
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 20 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
10.6 Arrays
QTOTΔV =
IFL • 0.4
fSW
CINT + CEXT
[5]
Up to ten PRMs of the same type may be placed in parallel to expand
the power capacity of the system. The following high-level guidelines
must be followed in order for the resultant system to start up and
operate properly, and to avoid overstress or exceeding any absolute
maximum ratings.
QTOT is the total input (Fig. 15) or output (Fig. 14) charge per switching
cycle at full load, while CINT is the module internal effective capacitance
at the considered voltage (Fig. 20) and CEXT is the external effective
capacitance at the considered voltage.
10.5 Input filter stability
The PRM can provide very high dynamic transients. It is therefore very
important to verify that the voltage supply source as well as the
interconnecting line are stable and do not oscillate. For this purpose,
the converter dynamic input impedance magnitude IrEQ_INI is provided
in Figures 22, 23, 24. It is recommended to provide adequate design
margin with respect to the stability conditions illustrated in 10.5.1 and
10.5.2.
10.5.1 Inductive source and local, external input decoupling
capacitance with negligible ESR (i.e.: ceramic type)
The voltage source impedance can be modeled as a series RlineLline
circuit. The high performance ceramic decoupling capacitors will not
significantly damp the network because of their low ESR; therefore in
order to guarantee stability the following conditions must be verified:
Rline>
Lline
(CIN_INT + CIN_EXT) • rEQ_IN
Rline<< rEQ_IN
[6]
[7]
• –IN pins of all PRMs must be connected together. Both inductance
and resistance from the common power source to each PRM should be
minimized, and matched.
• Input voltage to all PRMs must be the same. Independent fuses for
each PRM are recommended.
• PC pins must be connected together for synchronization and proper
fault response.
• Reference supply to the control loop voltage reference and current
sense circuitry must be enabled when all modules’ RE pins have
reached their operational voltage levels.
• There must be one single external voltage control loop. The control
loop must drive each PR pin relative to each modules’ SG pin, and the
local PR voltage must be the same across all modules.
• Each PRM must have its own local current shunt and current sense
circuitry to drive it’s IF pin.
• The number of PRMs required to achieve a given array capacity must
consider all sources of mismatch to avoid overstress of any PRM in the
array. Imbalances in sharing are not only due to current sharing
accuracy specifications, but also temperature differences among PRMs,
Vin variations, and error terms in the buffering of the error amplifier
output to the PR pins.
• Control loop compensation procedures above will hold for an array,
in general, although many parameters must be scaled against the
number of PRMs in the system.
Please contact Vicor Applications for assistance.
It is critical that the line source impedance be at least an octave lower
than the converter’s dynamic input resistance, [7]. However, Rline
cannot be made arbitrarily low otherwise equation [6] is violated and
the system will show instability, due to under-damped RLC input
network.
10.7 Input Fuse Recommendations
10.5.2 Inductive source and local, external input decoupling
capacitance with significant RCIN_EXT ESR (i.e.: electrolytic type)
Always ascertain and observe the safety, regulatory, or other agency
specifications that apply to your specific application.
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor Lline. Notice that, the
high performance ceramic capacitors CIN_INT within the PRM should be
included in the external electrolytic capacitance value for this purpose.
The stability criteria will be
10.8 Layout considerations
rEQ_IN
> RCIN_EXT
Lline
CIN_EXT • RCIN_EXT
[8]
< rEQ_IN
[9]
Equation [9] shows that if the aggregate ESR is too small – for example
by using very high quality input capacitors (CIN_EXT) – the system will be
under-damped and may even become destabilized. Again, an octave of
design margin in satisfying [8] should be considered the minimum.
A fuse should be incorporated at the input to each PRM, in series with
the +IN pin. A 15 A or smaller input fuse (Littelfuse® NANO2®
451/453 Series, or equivalent) is required to safety agency conditions
of acceptability.
Application Note AN:005 details board layout using VI Chip® and VI
BRICK® components. Additional consideration must be given to the
external control circuit components.
The current sense shunt signal voltage is highly sensitive to noise. As
such, current sensing circuitry should be located close to the shunt to
minimize the length of the sense signals. A Kelvined connection at the
shunt is recommended for best results.
The control signal from a remote voltage sense circuit to the PRM
should be shielded. Avoid routing this, or other control signals directly
underneath the PRM, if possible.
Components that tie directly to the PRM should be located close to
their respective pins. It is also critical that all control components be
referenced to SG, and that SG not be tied to any other ground in the
system, including –IN or –OUT of the PRM.
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 21 of 22
v i c o r p o w e r. c o m
PR045A480T040FP
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power
systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes
to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed
to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are used to the
extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all parameters of
each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the
“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment and is
not transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS
ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH RESPECT
TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR PARTICULAR
PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable for
collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no
liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and operating
safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor
to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to
the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was
defective within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support devices
or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when
properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the
life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products and components
in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products
described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by
this document. Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;
7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for
use under 6,975,098 and 6,984,965.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: [email protected]
Technical Support: [email protected]
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.0
05/2012
Page 22 of 22
v i c o r p o w e r. c o m