MC100LVEL92 5V Triple PECL Input to LVPECL Output Translator Description The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates them to differential LVPECL output signals. To accomplish the PECL to LVPECL level translation, the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard 5 V PECL supply, the LVCC supply is to be connected to the 3.3 V LVPECL supply, and Ground is connected to the system ground plane. Both the VCC and LVCC should be bypassed to ground with 0.01 mF capacitors. The PECL VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features http://onsemi.com SO−20 WB DW SUFFIX CASE 751D MARKING DIAGRAM* 20 • 500 ps Propagation Delays • 5 V and 3.3 V Supplies Required • ESD Protection: Human Body Model; >2 kV, • • • • • • • • • • 100LVEL92 AWLYYWWG Machine Model; >200 V The 100 Series Contains Temperature Compensation LVPECL Operating Range: LVCC = 3.0 V to 3.8 V PECL Operating Range: VCC = 4.5 V to 5.5 V Internal Input Pulldown Resistors Q Output will Default LOW with Inputs Open or < GND + 1.3 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Pb = Level 1 Pb−Free = Level 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index 28 to 34 Transistor Count = 247 devices Pb−Free Packages are Available* 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2008 November, 2008 − Rev. 12 1 Publication Order Number: MC100LVEL92/D MC100LVEL92 VCC Q0 Q0 LVCC Q1 Q1 20 19 18 16 15 17 LVCC Q2 14 13 LVPECL PECL PECL PECL 1 2 3 VCC D0 D0 4 5 6 D1 D1 VCC 12 11 7 8 9 10 VBB PECL LVPECL VBB PECL LVPECL Q2 D2 D2 GND Table 1. PIN DESCRIPTION PIN FUNCTION Dn, Dn Qn, Qn PECL VBB LVCC VCC GND PECL Inputs LVPECL Outputs PECL Reference Voltage Output LVPECL Power Supply PECL Power Supply Common Ground Rail Warning: All VCC, LVCC, and GND pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: SO−20 WB (Top View) Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Power Supply GND = 0 V 8 to 0 V LVCC LVPECL Power Supply GND = 0 V 8 to 0 V VI PECL Input Voltage GND = 0 V 6 to 0 V Iout Output Current Continuous Surge 50 100 mA mA IBB PECL VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20 WB SOIC−20 WB 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 WB 30 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free VI VCC Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 MC100LVEL92 Table 3. PECL INPUT DC CHARACTERISTICS VCC = 5.0 V; LVCC = 3.3 V; GND = 0 V Note 1) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ Min Typ Unit 12 mA PECL Power Supply Current VIH Input HIGH Voltage (Single−Ended) 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3515 3190 3525 3190 3525 mV PECL VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (DIfferential) (Note 2) Vpp < 500 mV Vpp y 500 mV 1.3 1.5 4.8 4.8 1.2 1.4 4.8 4.8 1.2 1.4 4.8 4.8 V V 150 mA Input HIGH Current IIL Input LOW Current 12 Max IVCC IIH 12 85°C Max 150 D D 0.5 −600 150 0.5 −600 0.5 −600 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input parameters vary 1:1 with VCC. VCC can vary 4.5 V to 5.5 V. 2. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V. Table 4. LVPECL OUTPUT DC CHARACTERISTICS VCC = 5.0 V; LVCC = 3.3 V; GND = 0 V (Note 3) −40°C Symbol Characteristic 25°C Min Typ Max 85°C Min Typ Max 20 Min Typ Max Unit ILVCC LVPECL Power Supply Current 21 mA VOH Output HIGH Voltage (Note 4) 2215 2295 2420 2275 2345 2420 20 2275 2345 2420 mV VOL Output LOW Voltage (Note 4) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Output parameters vary 1:1 with LVCC. VCC can vary 3.0 V to 3.8 V. 4. Outputs are terminated through a 50 W resistor to LVCC − 2.0 V. http://onsemi.com 3 MC100LVEL92 Table 5. AC CHARACTERISTICS VCC = 5.0 V; LVCC = 3.3 V; GND = 0 V (Note 5) −40°C Symbol Characteristic Min Typ 25°C Max Min 85°C Typ Max Min fmax Maximum Toggle Frequency tPLH tPHL Propagation Delay D to Q tSKEW Skew tJITTER Cycle−to−Cycle Jitter VPP Input Swing (Note 8) 150 1000 150 1000 tr tf Output Rise/Fall Times Q (20% − 80%) 270 530 270 530 TBD Diff S.E. 490 440 Output−to−Output (Note 6) Part−to−Part (Diff) (Note 6) Duty Cycle (Diff) (Note 7) TBD 590 590 690 740 20 20 25 100 200 510 460 TBD Typ Max GHz TBD 610 610 710 760 20 20 25 100 200 530 480 Unit 630 630 730 780 ps 20 20 25 100 200 ps 150 1000 mV 270 530 ps TBD ps TBD NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. LVCC can vary 3.0 V to 3.8 V; VCC can vary 4.5 V to 5.5 V. Outputs are terminated through a 50 W resistor to LVCC − 2.0 V. 6. Skews are valid across specified voltage range, part−to−part skew is for a given temperature. 7. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 8. VPP(min) is the minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈40. Q Zo = 50 W D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 4 MC100LVEL92 ORDERING INFORMATION Package Shipping† MC100LVEL92DW SO−20 WB 38 Units / Rail MC100LVEL92DWG SO−20 WB (Pb−Free) 38 Units / Rail MC100LVEL92DWR2 SO−20 WB 1000 / Tape & Reel MC100LVEL92DWR2G SO−20 WB (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 5 MC100LVEL92 PACKAGE DIMENSIONS SO−20 WB DW SUFFIX CASE 751D−05 ISSUE G A 20 q X 45 _ E h H M 10X 0.25 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B B 0.25 M T A S B S L A 18X e A1 SEATING PLANE C T DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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