Datasheet AS8530 LIN Tr a ns ce i ve r w it h I nt eg ra t e d Volt a ge Re gul at or a nd MCU Interface for Automotive Applications 1 General Description Typically 45µA quiescent current in standby mode, Typically 35µA quiescent current in sleep mode The AS8530 is a general purpose companion IC for sensor and actuator LIN slaves offering LIN transceiver and low drop voltage regulator. Under voltage reset with factory options LIN bus transceiver l conforming to LIN 2.1, TX time out fail safe feature, over temperature warning and shut down It also provides a 2-wire microcontroller interface through shared EN and TX pins to access a window watchdog with RC oscillator, control registers, backup registers and monitoring information. Window watchdog if factory enabled Micro controller 2-wire interface through shared pins for watchdog trigger, monitoring, register read /write The IC is fabricated in a high voltage CMOS technology which is able to withstand voltages up to 42V. Chip ID for traceability and module ID The product is available in ep-SOIC8 package. 8 Backup registers to store data during VCC shut down ep-SOIC8 package 2 Key Features -40ºC to +125ºC ambient operating temperature Operating voltage 6V to 18V 3 Applications Linear, low-drop voltage regulator: VCC = 5V ±5% or 3.3V ±5% as a factory programming option The AS8530 is a System Basis Chip for automotive LIN networked sensor or actuator slaves. 50mA load current Operating modes: Normal and Standby or Normal and Sleep as a factory option Figure 1. AS8530 LIN Transceiver Block Diagram VCC LDO VSUP POR-VSUP Temperature Limiter AS8530 TSHD RESET_VSUP_N EN 2-Wire Interface Window Watchdog (WWD) RESET_VCC_N Mode Control RESET_VSUP_N Control Signals WWD Output LIN Wakeup Reset Block RESET Receiver VSUP RX 30k VCC Transmitter LIN 15k Slew Control GND POR-VCC TX LIN Transceiver www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 1 - 32 AS8530 Datasheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 1 2 Key Features............................................................................................................................................................................. 1 3 Applications............................................................................................................................................................................... 1 4 Pin Assignments ....................................................................................................................................................................... 4 4.1 Pin Descriptions.................................................................................................................................................................................... 4 5 Absolute Maximum Ratings ...................................................................................................................................................... 5 6 Electrical Characteristics........................................................................................................................................................... 6 6.1 Operating Conditions............................................................................................................................................................................ 6 6.2 Digital Inputs and Outputs .................................................................................................................................................................... 6 6.3 Detailed System and Block Specifications ........................................................................................................................................... 7 6.3.1 Electrical System Specifications .................................................................................................................................................. 7 6.4 Low Dropout Regulator......................................................................................................................................................................... 7 6.5 LIN Transceiver .................................................................................................................................................................................... 8 6.5.1 6.5.2 6.5.3 6.5.4 DC Electrical Characteristics ....................................................................................................................................................... 8 AC Electrical Characteristics ....................................................................................................................................................... 9 Temperature Limiter .................................................................................................................................................................. 10 TX Timeout Watchdog ............................................................................................................................................................... 10 6.6 VCC Undervoltage Reset and Window Watchdog.............................................................................................................................. 11 6.7 Two Port Serial Interface .................................................................................................................................................................... 12 7 Detailed Description................................................................................................................................................................ 13 7.1 Voltage Regulator (LDO) .................................................................................................................................................................... 13 7.2 Temperature Limiter............................................................................................................................................................................ 13 7.3 VSUP Undervoltage Reset ................................................................................................................................................................. 13 7.3.1 VSUP Undervoltage in Normal Mode......................................................................................................................................... 13 7.3.2 VSUP Undervoltage in Standby Mode / Sleep Mode................................................................................................................. 13 7.3.3 VSUP Undervoltage in Low Slew Mode..................................................................................................................................... 13 7.4 RESET................................................................................................................................................................................................ 14 7.5 VCC Undervoltage Reset ................................................................................................................................................................... 14 7.6 Window Watchdog (WWD) ................................................................................................................................................................. 14 7.7 LIN Transceiver .................................................................................................................................................................................. 15 7.8 Operating Modes and States.............................................................................................................................................................. 7.8.1 7.8.2 7.8.3 7.8.4 7.8.5 Normal Mode ............................................................................................................................................................................. Standby Mode............................................................................................................................................................................ Sleep Mode................................................................................................................................................................................ Temporary Shutdown Mode ...................................................................................................................................................... Thermal Shutdown State ........................................................................................................................................................... 7.9 State Diagram..................................................................................................................................................................................... 8 Application Information ........................................................................................................................................................... 15 15 15 15 16 16 17 18 8.1 Initialization......................................................................................................................................................................................... 18 8.2 Wake-Up............................................................................................................................................................................................. 19 8.3 Over-Temperature Shutdown ............................................................................................................................................................. 19 8.4 LIN BUS Transceiver .......................................................................................................................................................................... 19 8.4.1 Transmit Mode........................................................................................................................................................................... 19 8.4.2 Receive Mode............................................................................................................................................................................ 20 www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 2 - 32 AS8530 Datasheet - C o n t e n t s 8.5 RX and TX Interface ........................................................................................................................................................................... 20 8.6 MODE Input EN.................................................................................................................................................................................. 21 8.7 Serial Port Interface............................................................................................................................................................................ 23 8.7.1 Device Configuration using 2-Wire Serial Port .......................................................................................................................... 23 8.8 Control and Diagnosis Registers ........................................................................................................................................................ 26 8.8.1 Definition of Control and Status Registers................................................................................................................................. 26 9 Package Drawings and Markings ........................................................................................................................................... 28 10 Ordering Information............................................................................................................................................................. 31 www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 3 - 32 AS8530 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments (Top View) EN 1 8 VCC VSUP 2 7 RESET AS8530 LIN 3 6 TX VSS 4 5 RX 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Number Pin Name Pin Type Special Requirements Description 1 EN Digital input with pull-down 2kV ESD Enable high-voltage compatible pin with pull down to VSS and ½ VCC trigger level, active high. 2 VSUP Supply pad Load dump (42V max), 4kV HBM ESD, Jump start (27V max) 3 LIN Analog I/O Conforms to LIN 2.1, 6kV HBM ESD 4 VSS Supply pad 5 RX Digital output with pull-up 6 TX Digital input with pull-up 7 RESET Digital output 8 VCC Supply pad www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Battery supply LIN Bus LIN transceiver receive signal, data out in test mode 2kV ESD LIN transceiver transmit signal, clock in test mode Digital output referenced to VCC, active low Regulated 5V / 3.3V supply for loads up to 50mA. OTP selectable Revision 1.1 4 - 32 AS8530 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Min Max Units Comments -0.3 42 V Transient up to 500ms duration EN -0.3 VSUP + 0.3 V VCC -0.3 7 V LIN -27 +40 V RESET, RX, TX -0.3 VCC + 0.3 V -100 100 mA Electrical Parameters VSUP DC Supply Voltage Input current (latchup immunity) Iscr Norm: JEDEC 78 Electrostatic Discharge Electrostatic Discharge (ESD) Norm: AEC-Q-100-002 ±2 For on board signals VCC, TX, RX, Reset kV ±4 ±6 For VSUP LIN to VSS, HBM Model Continuous Power Dissipation Total operating power dissipation (all supplies and outputs) Pt 0.25 W +150 ºC epSOIC8 in still air, soldered on JEDEC standard board @125º ambient, static operation = no time limit Temperature Ranges and Storage Conditions Storage temperature (Tstrg) -55 Package body temperature (Tbody) Humidity non-condensing 5 Moisture Sensitive Level www.austriamicrosystems.com/Lin_CompanionIC/AS8530 +260 ºC 85 % 3 The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/ JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). Represents a maximum floor life time of 168h Revision 1.1 5 - 32 AS8530 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics 6.1 Operating Conditions Symbol Parameter Conditions Min VSUP Positive Supply Voltage Normal operating condition 6 VSS Negative Supply Voltage TAMB Ambient temperature Maximum junction temperature (TJ) 150ºC -40 Isupp Supply Current Typ Max Units 18 V +125 ºC 65 mA Max Units 0 V 6.2 Digital Inputs and Outputs All pull-up, pull-downs have been implemented with active devices. RESET and RX have been measured with 100pF load. Symbol Parameter Conditions Min Typ EN Input High Voltage Pin which can also be connected to VSUP VIH High level input voltage VIL Low level input voltage ILEAK Input leakage current EN = L Ipd_en Pull down current EN = VCC 0.8VCC V 0.2VCC V -1 +1 µA 20 40 µA TX VIH High level input voltage 0.8VCC V VIL Low level input voltage 0.2VCC V ILEAK Input leakage current TX = VCC -1 +1 µA Ipu Pull up current TX pulled to VSS -30 -10 µA RESET VOH High level output voltage IOUT = 1 mA, VSUP ≥ 6V VOL Low level output voltage VSUP ≥ 6V VCC 0.5 V VSS + 0.4 V RX VOH High level output voltage VOL Low level output voltage www.austriamicrosystems.com/Lin_CompanionIC/AS8530 VCC 0.5 IOUT = 1 mA, VSUP ≥ 6V Revision 1.1 V VSS + 0.4 V 6 - 32 AS8530 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.3 Detailed System and Block Specifications 6.3.1 Electrical System Specifications Symbol Parameter 1 Current consumption Min Typ Max Units No load on VCC, LIN recessive, VSUP= 12V 300 µA No load on VCC, LIN dominant, VSUP = 12V 700 µA Stand-by mode Up to 125°C ambient (no load), VSUP= 12V 45 µA Sleep mode Up to 125°C ambient (no load), VSUP=12V 35 µA Normal mode IDDnom Conditions 1. No external load on the LIN bus 6.4 Low Dropout Regulator The LDO block is a linear voltage regulator, which provides a regulated (band-gap stabilized) output voltage (VCC) from the battery supply voltage (VSUP). (6V < VSUP < 18V for option 1, 6V <VSUP <18V option2; -40°C < TJ < 150°C; all voltages are with respect to ground (VSS); positive current flows into the pin), normal operating mode if not otherwise mentioned. Symbol Parameter Conditions Min Typ Max VCC Regulated supply voltage ILOAD 0mA to 50mA Option 1 4.75 5.25 Option 2 3.135 3.465 Units V TJ Junction Temperature -40 150 ºC VSUP Supply Voltage Range 6 12 18 V Load < 50mA 4.75 5.0 5.25 50mA to 65mA 4.5 5.5 Standby mode @ ICC < 5mA 4.5 5.5 Option 1 VCC Load-dump condition, ILOAD < 50mA Output Voltage Range Option 2 5.5 Load < 50mA 3.135 3.3 3.465 50mA to 65mA 2.97 3.3 3.63 Standby mode @ ICC < 5mA 2.97 Load-dump condition, ILOAD < 50mA V 3.63 3.63 Normal mode 50 250 Standby mode 5 250 ICC_SH Output Short Circuit Current dVCC1 Line Regulation ΔVCC / ΔVSUP 8 mV/V LOREG_SM Load Regulation (Standby mode) ΔVCC / ΔICCn (for ILOAD > 500µA) 10 mV/mA LOREG_NM Load Regulation (Normal mode) ΔVCC / ΔICCn (for ILOAD > 500µA) 1 mV/mA 2.2 10 µF 1 10 Ω CL1 ESR1 CL2 ESR2 CSUP1E ESR1_CSUP CSUP2C ESR2_CSUP Output Capacitor (Electrolytic) Output Capacitor (Ceramic) Input capacitor (Electrolytic) For EMC suppression Input capacitor (Ceramic) www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 mA 100 220 nF 0.02 1 Ω 10 100 µF 1 10 Ω 100 220 nF 0.02 1 Ω 7 - 32 AS8530 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.5 LIN Transceiver 6.5.1 DC Electrical Characteristics (4.5V < VCC < 5.5V; 6V < VSUP < 18V; -40°C < TJ < 150°C, VBUS is the voltage on the LIN node. All voltages are with respect to ground (VSS); positive current flows into the pin. Symbol Parameter Conditions Min Typ Max Units 40 120 200 mA 2 V 60 kΩ 20 µA Driver 1 Ibus_lim Current limitation in Dominant State LIN = VSUP_max LIN_VOL Output Voltage BUS (dominant state), ILIN = 40mA (short-circuit condition tested at VOL = 2.5V) Pull-up resistor Normal mode (recessive BUS level on TX pin) 20 Driver OFF; VSUP = 7.0V, 8V < VBUS < 18 Ibus_leak_rec 40 Receiver Ibus_leak_dom Input Leakage current at receiver Ibus_no_GND Ibus_no_bat Input Leakage current at receiver Driver OFF; Vbus = 0V; VSUP = 12V; VCC = 5V -1 VSS = VSUP; VSUP = 12V; 2 0V < VBUS < 18V, VCC = 5V -1 VSUP = VSS; 0V < VBUS < 18V, VCC = VSS 2 Vbus_dom Vbus_rec mA 1 mA 100 µA 0.4 VSUP 0.6 Vbus_cnt Vbus_cnt = (Vth_dom + Vth_rec)/2 Vhys Vhys = (Vth_dom – Vth_rec) 3 VSUP 0.475 0.525 VSUP 0.05 0.175 VSUP 3 1. This failure condition triggers thermal shut down when shut down temperature threshold is exceeded. 2. Not production tested. 3. Vth_dom: Receiver threshold of the recessive to dominant LIN bus edge Vth_rec : Receiver threshold of the dominant to recessive LIN bus edge www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 8 - 32 AS8530 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.5.2 AC Electrical Characteristics LIN Driver, Bus load conditions (CBUS ; RBUS): 1nF; 1kΩ / 6,8nF; 660Ω / 10nF; 500Ω Symbol Conditions Min Typ Max Units D1 (worst case 20Kbps transmission) Vth_rec(max) = 0.744 x VSUP; Vth_dom(max) = 0.581 x VSUP; VSUP = 6.0V to 18V; tbit = 50μs; D1 = tbus_rec(min) / (2 x tbit) 0.369 D2 (worst case 20kbps transmission) Vth_rec (min) = 0.422 x VSUP; Vth_dom (min) = 0.284 x VSUP; VSUP = 6V to 18V; tbit = 50μs; D2 = tbus_rec(max) / (2 x tbit) D3 (worst case 10.4kbps transmission) Vth_rec (max) = 0.778 x VSUP; Vth_dom (max) = 0.616 x VSUP; VSUP = 6.0V to 18V; tbit = 96μs; D3 = tbus_rec(min) / (2 x tbit) D4 (worst case 10.4kbps transmission) Vth_rec (min) = 0.389 x VSUP; Vth_dom (min) = 0.251 x VSUP; VSUP = 6V to18V; tbit = 96μs; D4 = tbus_rec(max) / (2 x tbit) 0.59 tdLR VCC = 5V; Propagation delay bus dominant to RX LOW 6 µs tdHR VCC = 5V; Propagation delay bus dominant to RX HIGH 6 µs tRS Receiver Delay symmetry -2 2 µs twake Wake-up delay time 30 150 µs tsln Transition from standby mode to normal mode (clock frequency is 128kHz ± 25%) 4 Clock cycles tnsl Transition from normal mode to standby mode (clock frequency is 128kHz ± 25%) 6 Clock cycles trec_deb Receiver De-bounce time Cint Guaranteed by design 0.581 0.417 1 220 3 µs 250 pF Note: Sleep-mode to Normal mode transition is identical to the Power-ON sequence after the remote wakeup event on LIN bus. The transition time will include the tRes (RESET time) and start-up time for the LDO. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 9 - 32 AS8530 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Figure 3. LIN Timing tbit tbit TXD tbus_dom(max) tbus_rec(min) tbus_dom(min) tbus_rec(max) LIN Vth_rec(max) Vth_dom(max) Vth_rec(min) Vth_dom(min) 6.5.3 Temperature Limiter Symbol Parameter Conditions Min Tsd Shut down temperature Junction temperature Tret Max Units 139 171 ºC Return temperature During shut down, the sensor must be powered by VSUP. Thermal shut down disables LDO and sets all drivers to high impedance, the IC returns from shut down with POR. 121 149 ºC Totset Over-temp warning flag set The temperature beyond which the warning flag is set. 121 149 ºC Totclear Over-temp warning flag clear The return temperature when the warning flag is cleared 103 127 ºC 6.5.4 Typ TX Timeout Watchdog Symbol Parameter tlin_wdog Time out duration (dominant state) www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Conditions Revision 1.1 Min Typ Max Units 0.5 1 2 s 10 - 32 AS8530 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.6 VCC Undervoltage Reset and Window Watchdog The values in this table are valid for normal and standby modes. All parameters are tested, unless mentioned otherwise. Symbol Parameter Conditions Min Vuvr_off VCC under-voltage threshold off (Default) Rising edge of VCC Vuvr_on VCC under voltage threshold on (Default) Vuvr1_off VCC under voltage threshold off (Factory Option) Rising edge of VCC Vuvr1_on VCC under voltage threshold on (Factory Option) Vuvr2_off Max Units 2.55 2.95 V Falling edge of VCC 2.3 2.7 V 1 3.0 3.4 V Falling edge of VCC 1 2.75 3.15 V VCC under voltage threshold off (Factory Option) Rising edge of VCC 1 3.5 3.9 V Vuvr2_on VCC under voltage threshold on (Factory Option) Falling edge of VCC 1 3.25 3.65 V Vuvr3_off VCC under-voltage threshold off (Factory Option) Rising edge of VCC 1 4.0 4.4 V Vuvr3_on VCC under voltage threshold on (Factory Option) Falling edge of VCC 1 3.75 4.15 V Vhyst_vcc Hysteresis of under-voltage threshold on/off VCC Default and all other factory options 0.1 0.4 V trr Spike filter on VCC To remove disturbance 4 Vsuvr_off VSUP under-voltage threshold off Vsuvr_on VSUP under-voltage threshold on WD_TCL WWD non-service time (if factory enabled) WD_TSV WWD Service – time (if factory enabled) tRes Reset delay time Tshd Temporary shutdown reset active time BOR level (considered to be the Master Reset for AS8530) RESET will be generated 12 RESET will not be generated 1 4ms, 16ms, 32ms (typ) are factory options (min = -25% and max = +50% of typical) 0-75 75-150 6 0.1 Typ 0.25 µs 3.85 V 3.25 V 0 -100 0-125 100-200 125-250 8 ms ms 12 ms 1 s 1. These are factory options which could be made available on specific request. 2. -40%, -20%, +20%, +60%, and +100% timings are available as factory options. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 11 - 32 AS8530 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6.7 Two Port Serial Interface Symbol Parameter Conditions Min Typ Max Units 250 Kbps General BR2WIRE_SPI Bit rate TENSCLK_H Clock high time 2 µs TENSCLK_L Clock low time 2 µs tDI_SU Data in setup time 20 ns tDI_HD Data in hold time 10 ns tDO_S Data out setup time 130 ns tDO_HD Data out hold time 135 ns tDO_D Data out delay tDI_HZ Data in to high impedance delay Write timing Read timing Time for the Microcontroller to release the TX bus 80 ns 80 ns Timing parameters when entering 2-Wire SP mode Ttx_su TX setup time before EN goes Low 20 ns Ttx_hd TX hold time after EN goes High 20 ns Ttx_SP_trigger EN falling edge to TX falling edge To enter into 2-Wire SP mode 2 TSTNDY_trigger TX high time from EN falling edge To enter into Sleep/Standby mode 5 cycles Ten_ENSCLK EN falling edge to start of 2-wire serial port clock 5 cycles www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 10 µs 12 - 32 AS8530 Datasheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description The AS8530 chip consists of a low drop-out regulator and a LIN bus transceiver, which is a bi-directional bus interface for data transfer between LIN bus and the LIN protocol controller. Additionally integrated is a RESET unit with a power-on-reset delay and a programmable window watchdog. It also includes a watchdog time-out on LIN TX node to indicate if the microcontroller is stuck in a loop and to release unintentional LIN bus dominant state. 7.1 Voltage Regulator (LDO) The voltage regulator has three operating modes. The features of the operating modes are given below: Normal mode: Stability to be better ±0.25V over input range and temperature for load current up to 50mA. The LDO Output provides a voltage of 5V or 3.3V as OTP option. Standby mode: The Standby mode is a low quiescent current mode used in car applications that are always switched on. The load current in standby mode is 5mA. Quiescent current (no load) is less than 45mA typically at room temperature. Sleep mode: Power down or temporary shutdown of the regulator can be set by a register bit. This bit can be written through 2-wire MCU interface. The LDO takes the input from bandgap and scales it up to the required voltage. The LDO starts charging only after the POR-VSUP event occurs (RESET_VSUP_N switched from low to high). The LDO can be powered-down by a control signal (temporary shutdown register) for the temporary shutdown mode. 7.2 Temperature Limiter Temperature limiter produces a power down when temperature exceeds 155ºC ±10%. It powers up and generates a reset when it returns to 135ºC ±10% junction temperature. During thermal shut down, temperature sensor is supplied by VSUP. During the temperature ramp-up phase, as soon as the temperature exceeds 135ºC ±10%, a warning signal is issued and is written into the diagnostic register, which can be read through the SP interface. 7.3 VSUP Undervoltage Reset VSUP undervoltage reset generates a reset RESET_VSUP_N, switched from low to high when VSUP ramps up above VSUVR_OFF. This is used to enable proper initialization of mode control and diagnostic registers. If VSUP < VSUVR_ON, then RESET_VSUP_N switches from high level to low level (active). This is considered to be the master reset and will have the highest priority over all other signals. As soon as VSUP < VSUVR_ON, the LDO, LIN Transceiver is completely shut off and system comes to a complete stop. AS8530 enters into the normal operating mode only after VSUP > VSUVR_OFF. 7.3.1 VSUP Undervoltage in Normal Mode Supply Voltages below VSUVR_OFF and above VSUVR_ON do not influence the voltage regulator. The output voltage VCC follows VSUP. 7.3.2 VSUP Undervoltage in Standby Mode / Sleep Mode No exit from the sleep mode or standby mode take place if the VSUP voltage drops down to VSUVR_OFF. If VSUP goes below VSUVR_ON, RESET_VSUP_N is active and resets the mode control and diagnostic register. The voltage regulator, LIN Transceiver modules are turned off. If VSUP rises again above VSUVR_OFF, RESET_VSUP_N is switched from low to high. The system enters normal mode where LIN Transceiver and LDO are switched on. 7.3.3 VSUP Undervoltage in Low Slew Mode The behavior of AS8530 at low VSUP voltages is equal to the sleep mode. The low slew mode (set by control register through serial interface as an option) will be cancelled, if VSUP drops below VSUVR_ON in this mode. The AS8530 enters the normal mode, if VSUP rises again above VSUVR_OFF. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 13 - 32 AS8530 Datasheet - D e t a i l e d D e s c r i p t i o n 7.4 RESET Reset generates an external RESET signal to reset the microcontroller and all other external circuits. The reset functionality is illustrated in Figure 4. Reset consists of a digital buffer at the output. RESET signal can be affected by RESET_VCC_N (which is the under-voltage reset on VCC) and Window watchdog output. All those conditions which cause a drop in the VCC voltage will be detected from the low voltage reset unit, which in-turn generates a reset signal. States like Temporary shut-down, Over-temperature monitor will influence the RESET output through RESET_VCC_N signal only. Figure 4. Reset Functionality VSUP T>Tj VCC T<Tj t<trr VUVR_OFF VUVR_ON tRes tRes tRes trr RESET Initialization Thermal shutdown Spike VSUP MISSING WATCHDOG ACCESS tRes Low voltage VSUP tRes Current limitation active 7.5 VCC Undervoltage Reset The POR-VCC generates RESET_VCC_N signal as output which determines under-voltage reset of the output of the LDO. The rising edge of the VCC gives an under-voltage reset “off” and the falling edge of the VCC gives an under-voltage reset “on”. This under-voltage signal is used to control the RESET output. When VCC rises up Vuvr_off for a period greater than reset duration (tRes) then RESET_VCC_N switches from low level to high level and pin RESET is inactive (high). If VCC falls below Vuvr_on for a period greater than a predetermined delay (trr) then RESET_VCC_N switches from high level to low level and pin RESET is active (low). The RESET_VCC_N signal is used to initializes Window watchdog timer, TX time-out, Test control circuits, 2-wire SP, and logic associated with SP (everything other than the SP control registers). VCC under-voltage reset threshold voltage level adjustment can be made by 2 bit OTP as explained in OTP interface. 7.6 Window Watchdog (WWD) To keep the external microcontroller always in proper function state, a window watchdog circuit is implemented. The WWD trigger is generated by external MCU through SP interface. If the window is missed, a reset on the RESET pin with certain reset time (tRes) is generated. The WWD function can be enabled or disabled by factory setting. The watchdog is started after the ASSP exits reset. Under normal working conditions, microcontroller gives a WWD trigger every time in the window period of WD_TSV (service time). If the trigger does not occur during WD_TSV or occurs too early during WD_TCL (non-service time), then RESET output is pulled low (active), which will reset the micro-controller. WWD circuit is turned on after the RESET pin goes back to high (inactive). If VCC < Vuvr_on, WWD circuit is switched off. When the WWD function is enabled, there is a 3-bit factory programming available to set the trigger window. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 14 - 32 AS8530 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 5. Window Watchdog Trigger Period Non-Service time (WD_TCL) Service time (WD_TSV) 50 % 100 % Trigger restart period Trigger via SPI Last trigger point Earliest possible trigger point (System will not RESET) Latest possible trigger point (System will not be RESET) Valid Trigger point (System will not be RESET) Unwanted trigger point (System will be RESET) 7.7 LIN Transceiver The transceiver provides short circuit limitation, hardware watchdog and over temperature shut down features. The TX watchdog timer is active when TX is pulled low (active). As soon as the TX watchdog timeout occurs, the LIN bus is released from dominant state to recessive state. The LIN transceiver has a pull-up resistor (for the slave node; extra resistor externally for the master node) to the VSUP. A diode protection is available to protect it from back supply from bus line. The LIN transmitter has the basic functionality of relaying the data from the micro-controller on to the LIN. The data on the LIN needs to have controlled slew to have reduced EMI. The receiver relays the data from the LIN to the micro-controller. This transmitter has optimized EMC performance across different loading conditions conforming to the LIN 2.1 standards. The wake-up detects a wake up event on the LIN. 7.8 Operating Modes and States The AS8530 provides four main operating modes “normal”, “sleep/stand-by” (programmed by OTP), “temporary shutdown” and “thermal shutdown”. The LIN transceiver can be programmed to operate with lower slew in the normal mode. Refer to Table 3 for a detailed description on transition for each mode. 7.8.1 Normal Mode This is the mode after the power-up. In normal mode, LDO, LIN Transceiver, Window Watchdog, Resistive divider and the line drivers are all turned on. All the blocks are completely functional. LDO is now capable of delivering maximum load current possible as per the device specifications. The LIN Transceiver is capable of sending the TX data from microcontroller to the LIN bus at a maximum rate of 20Kbps. EN signal is set to high and LIN, TX, RX pins can be driven into dominant (low) or recessive (high) states. If the junction temperature increases more than Totset, a warning flag is set in the diagnostic register, which can be read through the 2-wire interface. 7.8.2 Standby Mode Standby mode is a functional low-power mode where LIN Transceiver is disabled. The LIN wake-up circuit and over-temperature monitor circuit is enabled. Window watchdog, TX timeout watchdog, Resistive divider, relay driver circuits are disabled. EN pin held low in this mode. TX pin is in recessive state (high). CS is pulled to VCC while SDI and SCLK outputs are pulled to VSS. 7.8.3 Sleep Mode As a factory programming option on request the AS8530 offers as a replacement to the standby mode with sleep mode. Sleep mode is the most current saving mode. If EN is held low, the LDO, LIN Transceiver and the reset and window watchdog unit will be switched off. VCC is pulled down to zero. The LIN wake-up circuit, oscillator and over-temperature monitor circuit is active. LIN bus is in recessive state (high). Only wakeup possible is through remote wake-up, through LIN pin, pulling it to dominant state for 100µs typical (low), can change the state of the system. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 15 - 32 AS8530 Datasheet - D e t a i l e d D e s c r i p t i o n 7.8.4 Temporary Shutdown Mode In this mode, the VCC is pulled down and the LDO is powered down. This mode is introduced to interface with other components which do not have a pin for the reset functionality. This provides an alternative way to reset those components interfacing with AS8530. This mode is default disabled but can be enabled by an OTP option. In this mode, all internal modules supplied by the LDO are disabled. Only the oscillator, control registers are enabled. The VCC output can be temporarily switched off and pulled to VSS. EN signal, RX, TX is pulled low and LIN Transceiver along with the LIN wake-up circuit is powered down. No remote wake-up functionality is possible. LIN bus enters into recessive state. The system goes out of this mode to normal mode after the time-out of an internal counter delay (Tshd). Normal mode to temporary shutdown transition will be controller by register bit in configuration register. 7.8.5 Thermal Shutdown State If the junction temperature TJ is higher than Tsd, the AS8530 will be switched into the thermal shutdown mode. The transceiver is completely disabled. No wake-up functionality is available. Window watchdog, TX timeout watchdog, and LDO are completely turned off. Only the overtemperature monitor would be working. As soon as the temperature returns back to Tret, the system enters normal mode. For more information on transition, see Table 3. Table 3. Transition Table Transition From mode Interface To mode LIN RX Stand-By X-RS X-H Sleep X-RS X-H Temporary Shutdown X-RS X-H OverTemperature X-RS X-H Normal (LW) X H-X Normal (RW) X Temporary Shutdown RS H OverTemperature RS H Normal RS-X H-X Normal RS-X OverTemperature RS H Power Off X 1 Normal Mode Stand-By Mode Temporary Shutdown Mode 2 2 TX H H 3 3 Reg. 0x05 D0 rwake Uvbat OT Uvcc 3 L X X inactive inactive TX is high for TSTNDY_triggerr 3 L X X inactive set TX is high for 1 TSTNDY_triggerr The Control Bit is set through the 2-Wire SP interface EN H-L H-L Flags 2 X H 3 H X X inactive set 2 X X L X X set set 2 X L-H L X X inactive inactive H-X 2 H X L set X inactive Remote Wake up inactive Event occurred on LIN 2 H L H X X inactive set 2 H L L X X set set 2 X X L X X inactive clear Internal 128ms timer expired H-X 2 X X L set X inactive clear Remote Wake up Event occurred on LIN 2 X X L X X set hold Temperature monitor output asserted (covered by scan) X X X X X L-H X X 3 3 3 Sleep Mode All States Comments 3 The Control Bit is set through the 2-Wire SP interface 1. Chosen by factory programming option 2. Effect of Transition 3. Cause for Transition Note: L = low state, H = high state, OT = Over-temperature Reset, Uvcc = Undervoltage VCC, Uvbat = Undervoltage VBAT, rwake =remote wake, X = do not care. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 16 - 32 AS8530 Datasheet - D e t a i l e d D e s c r i p t i o n 7.9 State Diagram The complete functional state machine for AS8530 is illustrated in Figure 6. Some soft-states in the FSM like “TXWD Wait”, “Standby Wait” and other “wait” states have been included for the sake of completeness. Figure 6. Finite State Machine Model for the AS8530 System INIT0 Vsup > Vsuvr_off Temperature < Tret OVTEMP OTP LOAD otp_load Temperature > Tsd 128msec Temperature > Tsd Temporary Shutdown RESET TIMEOUT Tem shu porar tdo y wn RESET time > tRES Vcc < Vuvr_on || wwdtimeout rwake Temperature > Tsd y ar or n mp ow Te hutd s y ndb sta rwake orary Temp wn o shutd Temperature > Tsd STANDBY WAIT Vcc < Vuvr_on RX=0 WAIT_TEST otp _en RX =0 ary por n Tem utdow sh STANDBY NORMAL by and ! st Vcc < Vuvr_on rw ak e_ wa it Temperature > Tsd test_en Standby & sleep TX=1 SLEEP Txwd_timeout Temperature > Tsd WAIT_OTP Vcc < Vuvr_on || wwdtimeout TXWD WAIT Temperature > Tsd www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 17 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8 Application Information 8.1 Initialization When the power supply is switched on, if VSUP > VSUVR_OFF, RESET_VSUP_N becomes inactive (high). After this, the voltage regulator starts with a default LDO output setting of 3.3V and Vuvr_off setting of 2.75V. If VCC > Vuvr_off (2.75V), active-low PORN_2_OTP is generated. The rising edge of PORN_2_OTP loads contents of fuse onto the OTP latch after load access time TLoad. LOAD_OTP_IN_PREREG signal loads contents of OTP latch onto the pre-regulator domain register. This register gives actual settings of LDO, Vuvr_off and Reset Timeout period TRes. This is done because the OTP block is powered by the VCC. If VCC > Vuvr_off (phase 2), Reset timeout is restarted. RESET signal is deasserted after Reset Timeout period TRes (phase 2) and then device enters into normal mode. The circuit initializes correctly also for very slow ramp on VSUP (of the order of 0.5V/min). Figure 7. Initialization Sequence for AS8530 Vsuvr_off VSUP RESET_VSUP_N PHASE 1 Device Settings LDO Off PHASE 2 LDO On Vuvr_off = 2.75V, LDO setting = 3.3V tRES = 4msec LDO On Vuvr_off = from OTP Block, LDO setting = from OTP Block tRES = from OTP Block Vuvr_off Vuvr_off VCC RESET_VCC_N PORN_2_OTP 6 Cycles of RC-Oscillator LOAD_OTP_IN_PREREG RESET If Phase 1 POR threshold != Phase 2 POR threshold Tres = Reset Timeout from OTP Block If Phase 1 POR threshold == Phase 2 POR threshold Tres = Reset Timeout from OTP Block www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 18 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 4. VSUP>Vsuvr_on and VCC<Vuvr_on Block Output Signal TRANSCEIVER = Enabled (disabled only during initial VSUP ramp-up) LIN = high-z, RX = follows V LDO = Enabled (disabled only during initial ramp-up) VCC = low RELAY DRIVER = Enabled LDRIVE1 = high, LDRIVE2 = high RESET = Enabled RESET = high-z RESISTIVE DIVIDER = Enabled VBAT= high, VBAT_DIV = enabled Block Output Signal TRANSCEIVER = Disabled LIN = high-z, RX = high-z LDO = Disabled VCC = low RELAY DRIVER = Disabled LDRIVE1 = high, LDRIVE2 = high RESET = Disabled RESET = high-z RESISTIVE DIVIDER = Disabled VBAT = high, VBAT_DIV = low Table 5. VSUP<Vsuvr_on 8.2 Wake-Up If the regulator is put into sleep/standby mode, it can be woken up with the BUS interface. A transition on the BUS (high to low) with a minimum predefined low time (twake) puts the regulator into normal mode. 8.3 Over-Temperature Shutdown If the junction temperature increases beyond Tsd the over-temperature recognition will be activated and the regulator voltage will be switched off. The VCC voltage drops down, the reset state is entered and the bus transceiver is switched off (recessive state). After TJ falls below Tret, the AS8530 will be initialized again. This initialization starts independently from the voltage levels on EN and BUS. Within the thermal shutdown mode, the transceiver cannot switch to the normal mode either with local or with remote wake-up. The operation of the AS8530 is possible between TJ (125ºC) and the switch off temperature Tsd, but small parameter differences can appear. After over-temperature switch-off, the IC initializes as explained in Initialization on page 18. The low slew mode for LIN Transceiver has to be selected again on re-initialization, if necessary. 8.4 LIN BUS Transceiver The AS8530 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed by a de-bouncing unit. 8.4.1 Transmit Mode During transmission the data at the pin TX will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit. Transmitting will be interrupted in the following cases: Sleep mode Thermal Shutdown active Master Reset (VSUP < Vsuvr_on) The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the AS8530 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1kΩ resistor in series with a diode to VBAT. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 19 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.4.2 Receive Mode The data signals from the BUS pin will be transferred continuously to the pin RX. Short spikes on the bus signal are suppressed by the implemented de-bouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely observed. Figure 8. Receive Mode Impulse Diagram Vthr_max 60% BUS Vthr_hys Vthr_cnt 50% 40% Vthr_min t < tdeb_BUS t < tdeb_BUS RX 8.5 RX and TX Interface Input TX. The 5V input TX controls directly the BUS level. LIN Transmitter acts like a slew-controlled level shifter. A dominant state (low) on TX leads to the LIN bus being pulled low (dominant state) too. The TX pin has an internal active pull up connected to VCC. This guarantees that an open TX pin generates a recessive BUS level. Figure 9. TX Input Circuitry MCU AS8530 VCC VCC IPU_TXD www.austriamicrosystems.com/Lin_CompanionIC/AS8530 TX Revision 1.1 RC-Filter (10ns) 20 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Output RX. The received BUS signal will be output to the RX pin: BUS < Vthr_cnt – 0.5 * Vthr_hys → RX = low BUS > Vthr_cnt + 0.5 * Vthr_hys → RX = high This output is a push-pull driver between VCC and GND with an output current of 1mA. Figure 10. RX Output Circuitry AS8530 MCU VCC RX 8.6 MODE Input EN The AS8530 is switched from normal mode to the standby/sleep mode with a falling edge on EN and keeping TX high for TSTNDY_trigger time. Device is switched from standby mode to normal mode with a rising edge at the EN pin. The mode change for AS8530 with a falling edge at EN can be done independently from the state of the bus transceiver. Device enters into Serial port mode by forcing EN low and driving TX high to low within Ttx_SP_trigger time after EN forced to low. This ensures the direct control of device to enter into Standby/Sleep mode by microcontroller using EN pin. Figure 11. EN Pin Functionality Entry into Serial Port Mode Ten_ENSCLK EN RD LEN LEN A4 WR 1 0 TX Ttx_su Normal Mode TSTNDY_trigger Ttx_hd Standby/Sleep Mode D3 D2 D1 D0 Ttx_su Ttx_SP_trigger Normal Mode Serial Port Mode Normal Mode The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 21 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 12. Enable Controlled via. MCU Cload EN VSUP LIN AS8530 VBAT VCC + MCU + 5V RESET TX VSS RX If the application doesn’t need the wake up capability of the AS8530, a direct connection EN to VCC is possible. In this case the AS8530 operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via. VSUP signal as shown below. Figure 13. Permanent Normal Mode Cload EN VSUP LIN AS8530 VBAT VCC + 5V RESET VSS www.austriamicrosystems.com/Lin_CompanionIC/AS8530 + MCU TX RX Revision 1.1 22 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.7 Serial Port Interface The interface is essentially used to trigger the window watchdog, to access test mode and read out diagnostic information for the AS8530. The description of this interface and the protocol is explained below. Information on block status and errors can be displayed by diagnosis registers. 8.7.1 Device Configuration using 2-Wire Serial Port The AS8530 device configuration register is programmed via a 2-wire Serial Programming Interface. EN/SCL is used as Serial Clock and TX/ SDA_IO is used as Serial Data. EN is used as clock input to access serial port registers in serial port mode. Also EN is used to control transition from normal mode to standby/sleep mode. The TX input of the device will be multiplexed as following: LIN TX for transmitting data from microcontroller on LIN bus SDA_IO for Serial data input/output, this will be used for serially accessing data from configuration and status register SP Frame. A frame is formed by first byte for command and address/configuration and following bit stream that can be formed by an integer number of bytes. Command is coded RD/WR on the first bits, length of the transfer is indicated by LEN1, LEN2 bits while address is given on LSB 5 bits. Table 6. Command Bits Command Bits Register Address or Transmission Configuration RD/WR LEN1 LEN2 A4 A3 A2 A1 A0 RD/WR Command <A4:A0> Description 0 WRITE ADDRESS Writes data byte on the given starting address. 1 READ ADDRESS Read data byte from the given starting address. Table 7. Transfer Length LEN1 LEN2 Length Description 0 0 1 Transfer consists of single Data phase. After completion of single Data phase device comes out of Serial port interface. 0 1 2 Transfer consist of two Data phase. 1 0 4 Transfer consist of four Data phase. 1 1 8 Transfer consist of eight Data phase. Write Command. For Write command RD/WR = 0 After the command code, length of the transfer is send in next two bits, the address of register to be written has to be provided from the MSB to the LSB. Then one, two, four, or eight data bytes can be transferred from the MSB to the LSB. For each data byte following the first one, used address is the incremented value of the previously written address. Each bit of the frame has to be driven by the 2-Wire SP master on the SP clock (EN pin) positive edge and the 2-Wire SP slave (device) samples this bit on the next SP clock (EN pin) negative edge. In the following figures two examples of write command (without and with address self-increment). Figure 14. Protocol for Serial Data Write with Length = 1 EN TX 0 LEN1 LEN0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Data Phase Command & Address Phase LEN1 = 0 LEN0 = 0 Length of Transaction = 1 Transfer edge www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Sampling edge Revision 1.1 Data D7 – D0 is moved to Address A4..A0 here 23 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 15. Protocol for Serial Data Write with Length = 4 EN TX 1 1 0 A A A A A 4 3 2 1 0 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 LEN1 LEN0 Command & Address Phase Data2 Phase Data1 Phase Data D7-D0 is moved to Address A4-A0 here LEN1 = 1 LEN0 = 0 Length = 4 Data3 Phase Data D7-D0 is moved to Address A4-A0 + 1 here Data4 Phase Data D7-D0 is moved to Address A4-A0 + 2 here Data D7-D0 is moved to Address A4-A0 + 3 here Read Command. For Read command RD/WR=1. After the command code, length of the transfer is send in next two bits, the address of register to be read has to be provided from the MSB to the LSB. Then one, two, four or eight data bytes can be transferred from the SPI slave to the master, always from the MSB to the LSB. Each bit of the command and address sections of the frame have to be driven by the 2-Wire SP master on the SP clock (EN pin) positive edge and the 2-Wire SP slave (device) samples this bit on the next SP clock (EN pin) negative edge. Each bit of the data phase of the frame has to be driven by the 2-Wire SP slave (device) on the SP clock (EN pin) positive edge and the 2-Wire SP master samples this bit on the next SP clock (EN pin) negative edge. The following figures illustrate two examples of read command (without and with address self-increment.) Figure 16. Protocol for Serial Data Read with Length = 1 EN TX 0 LEN1 LEN0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Data Phase Command & Address Phase LEN1 = 0 LEN0 = 0 Length of Transaction = 1 Transfer edge Sampling edge www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Data D7 – D0 at address A4 ..A0 is read here Revision 1.1 Transfer edge Sampling edge 24 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 17. Protocol for Serial Data Read with Length = 4 EN TX 1 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 A A A A A 4 3 2 1 0 1 0 LEN1 LEN0 Command & Address Data2 Phase Data3 Phase Data4 Phase Data1 Phase Phase Data D7-D0 at Data D7-D0 at Data D7-D0 at Data D7-D0 at Data D7-D0 at LEN1 = 1 LEN0 = 0 Address A4-A0 Address A4-A0 +1 Address A4-A0 +2 Address A4-A0 +3 Address A4-A0 +4 Length = 4 is read here is read here is read here is read here is read here Timing. The following figures illustrate timing waveforms and parameters. Figure 18. Timing for Writing TENSCLK_H TENSCLK_L EN TDI_SU TDI_HD DATAI TX DATAI Figure 19. Timing for Reading TENSCLK_H TD0_D TENSCLK_L EN TDI_SU TX TD0_D TDI_HD DATAI DATAO DATAO TDI_HZ www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 25 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 8.8 Control and Diagnosis Registers The serial interface can be used as interface between the ASSP AS8530 and an external micro-controller. The interface is a slave and only the micro-controller can start the communication. This interface will be used for device configuration, entering into test mode and carrying out diagnostic options. Refer to Table 8 for details on the configuration registers. 8.8.1 Definition of Control and Status Registers A total of 32 control, diagnosis and test registers, each of 8-bit can be accessed using the 2-wire serial interface. Table 8 provides a description of all control and status registers. Table 8. Configuration Registers Address Register Name POR Value RD / WR Description Control and Configuration Register D0 Reserved D1 Reserved D2 Reserved 0 x 03 Device Configuration Register On POR_VCC 0000_1111 RD / WR D3 Enable / Disable LIN Transceiver 0 Disabled 1 Enabled D7…D4 Reserved 0 x 04 Device Control Register On POR_VSUP 0000_0001 RD / WR D7... D1 Reserved D0 Temporary shutdown control bit 0 x 05 Temporary Shutdown Register On POR_VCC 0000_0000 RD / WR 0 No Temporary shutdown 1 Enter into Temporary shutdown D7…D1 Reserved D0 Window Watch Dog Trigger 0 x 06 Window Watch Dog Trigger Register On POR_VCC 0000_0000 This bit will be set by MCU to indicate trigger event. If this trigger occurs outside the Window of Watch dog counter, then RESET signal is asserted. Also on this trigger WWD counter is restarted and this bit will be cleared internally within 2 cycles of 128KHz clock. WR D7 … D1 Reserved 0 x 07 Low Side Driver Data Register On POR_VCC 0000_0000 www.austriamicrosystems.com/Lin_CompanionIC/AS8530 RD / WR D7 … D0 Reserved Revision 1.1 26 - 32 AS8530 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Table 8. Configuration Registers Address Register Name POR Value RD / WR Description Diagnosis Register D7..D0 = DR[7:0] 8 LSB bits of the 24 bit Diagnostic Register D0 PORVSUP (set when VSUP < Vsuvr_on, cleared after µC read) D1 UVVCC Under voltage VCC (set when VCC < Vuvr_on, cleared after µC read) D2 OTEMP160 Over-temperature Reset. (set when temp > Tsd, cleared after µC read) 0 x 08 Diagnostic Register 1 On POR_VSUP 0000_0011 RD D3 OTEMP140 Over-temperature warning (set when temp > Totset, cleared after µC read) D4 OVVBAT Overvoltage VBAT. (set when VSUP > Vovthh, cleared after µC read) D5 Reserved D6 RWAKE Remote Wakeup (set on Remote Wakeup event on LIN Bus, cleared after µC read) D7 WWDT Window watchdog timeout. (set on failure of Window watchdog timeout, cleared after µC read) D7..D0 = DR[15:8] next 8 LSB bits of the 24 bit Diagnostic Register. 0 x 09 Diagnostic Register 2 On POR_VSUP 0000_0000 RD D0 TXTIMEOUT Tx timeout of 1sec. (set on TX low > 1sec, cleared after µC read) D1 TEMPSHUT this bit is set on entering into temporary shutdown state and cleared after µC read. D7 D2 Reserved Note: When the device is powered ON @ ambient temperature of 125ºC, the status of the OVTEMP140 can be HIGH indicating an over temperature warning. This is because 125ºC is within the limits for the OVTEMP140. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 27 - 32 AS8530 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings The device is available in a ep-SOIC8 package. Figure 20. Drawings and Dimensions YYWWIZZ AS8530* * The device marking for the VCC=5V option will change to AS8530A. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 28 - 32 AS8530 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Symbol A A1 A2 b c D D1 E E1 E2 e L Min 0.00 1.25 0.31 0.17 2.24 1.55 0.41 Nom 4.90 BSC 3.10 6.00 BSC 3.90 BSC 2.41 1.27 BSC 0.64 Max 1.70 0.15 0.51 0.25 3.20 2.51 0.89 Symbol L1 L2 h θ aaa bbb ccc ddd eee fff N Min 0.25 0º - Nom 1.04 REF 0.25 BSC 0.10 0.20 0.10 0.25 0.10 0.15 8 Max 0.50 8º - Notes: 1. 2. 3. 4. Dimensions and tolerancing conform to ASME Y14.5M -1994. All dimensions are in miilimeters. Angles are in degrees. Datums A and B to be determined at datum H. Extrusion of exposed area in bottom side is 0.20mm typical. Marking: YYWWIZZ. YY WW I ZZ Last two digits of the manufacturing year Manufacturing Week Plant Identifier Traceability Code www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 29 - 32 AS8530 Datasheet - R e v i s i o n H i s t o r y Revision History Revision 1.0 1.1 Date Owner Description 26 Nov, 2010 mbl Initial release 29 Nov, 2010 kpt Marking details updated under Ordering Information. 03 Jun, 2011 mbl Updated Package Drawings and Markings, Ordering Information. Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 30 - 32 AS8530 Datasheet - O r d e r i n g I n f o r m a t i o n 10 Ordering Information The devices are available as the standard products shown in Table 9. Table 9. Ordering Information 1 Ordering Code Marking Description Delivery Form Package AS8530A-ASOT AS8530-ASOT AS8530A VCC = 5V Tape & Reel ep-SOIC8 AS8530 VCC = 3.3V Tape & Reel ep-SOIC8 1. For both product versions, the RESET delay time tRes as well as undervoltage threshold are set to default value and window watchdog is disabled. On special request, optional factory settings can be made available on specific vendor addendum. Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is available at http://www.austriamicrosystems.com/Technical-Support For further information and requests, please contact us mailto: [email protected] or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 31 - 32 AS8530 Datasheet - C o p y r i g h t s Copyrights Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com/Lin_CompanionIC/AS8530 Revision 1.1 32 - 32