Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer Frequency Table Product Features • • • • • • • • • • BYPASS# PLL_EN VCO_SEL Q(0:7) 0 0 0 REF 0 0 1 REF 0 1 0 REF 0 1 1 REF 1 0 0 REF/4 1 0 1 REF/8 1 1 0 VCO/4 1 1 1 VCO/8 110MHz Clock Support TM Supports PowerPC , Intel and RISC Processors 9 Clock Outputs: drive up to 18 loads LVPECL Reference Input Clock Output Disable Control Spread Spectrum Compatible 3.3V Power Supply Pin Compatible with MPC953 Industrial Temp. Range: -40°C to +85°C 32-Pin TQFP Package FB_OUT REF REF REF REF REF/4 REF/8 VCO/4 VCO/8 Table 1 Function Table ‘1’ = PLL Enabled ‘0’ = PLL Bypass ‘1’ = Outputs Disabled HiZ ‘0’ = Outputs Enabled ‘1’ = VCO/2 ‘0’ = VCO ‘1’ = Select VCO ‘0’ = Select PECL_CLK BYPASS# MR/OE# VCO_SEL PLL_EN Table 2 VCO_SEL BYPASS# PLL_EN VSS FB_OUT VDDC Q0 VSS 32 31 30 29 28 27 26 25 Pin Configuration Block Diagram FB_OUT 13 14 15 16 VSS Q6 VDDC Q5 MR/OE# 12 BYPASS# Z9953 Q7 VCO_SEL 24 23 22 21 20 19 18 17 11 LPF 1 2 3 4 5 6 7 8 VDDC Q7 VCO 200-500M VDD FB_IN NC NC NC NC VSS PECL_CLK 9 Q(0:6) 10 7 /2 MR/OE# FB_IN /4 Phase Detector PECL_CLK# PECL_CLK PECL_CLK# Q1 VDDC Q2 VSS Q3 VDDC Q4 VSS PLL_EN Figure 1 Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07086 Rev. *B 12/26/2002 Page 1 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer Pin Description PIN 8 9 12, 14, 16, 18, 20, 22, 24, 26 28 NAME PECL_CLK PECL_CLK# Q(7:0) PWR VDDC I/O I I O Description FB_OUT VDDC O 2 FB_IN I 10 MR/OE# I 30 PLL_EN I 31 BYPASS# I 32 VCO_SEL I 11, 15, 19, 23, 27 1 7, 13, 17, 21, 25, 29 3, 4, 5, 6 VDDC Feedback Clock Output. Connect to FB_IN for normal operation. A bypass delay capacitor at this output will control Input Reference / Output phase relationships. Feedback Clock Input. Connect to FB_OUT for accessing the PLL. Master Reset/Output Enable Input. When asserted high, resets all of the internal flip-flops and also disables all of the outputs. When pulled low, releases the internal flip-flops from reset and enables all of the outputs. PLL Select Input. When asserted high, VCO output is selected. And when set low, PECL_CLK is the input to the output dividers. PLL Enable Input. When high, PLL is enabled and when low, PLL is bypassed. VCO Divider Select Input. When set high, VCO output is divided by 2. When set low, the divider is bypassed. 3.3V Power Supply for Output Clock Buffers. VDD VSS 3.3V Power Supply for PLL Common Ground NC No Connection PECL Input Clock. PECL Input Clock. Clock Output. PD = Internal Pull-Down, PU = Internal Pull-Up. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07086 Rev. *B 12/26/2002 Page 2 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer Maximum Ratings¹ This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Maximum Input Voltage Relative to VSS: VSS - 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: Operating Temperature: -65°C to + 150°C -40°C to +85°C Maximum ESD protection 2KV Maximum Power Supply: Maximum Input Current: VSS<(Vin or Vout)<VDD 5.5V ±20mA Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters Characteristic Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Symbol Min VIL VIH IIL IIH VPP VSS 2.0 VCMR VDD1.5 Typ - 300 Output Low Voltage VOL Output High Voltage VOH VDD0.6 Quiescent Supply Current - Max Units Conditions 0.8 VDD -120 120 1000 V V µA µA mV Note 2 VDD0.6 V 0.6 V IOL = 20mA, Note 4 V IOH = -20mA, Note 4 Note 3 IDDC - - 20 mA All VDDC and VDD PLL Supply Current IDD - 15 20 mA VDD only Input Capacitance Cin - - 4 pF VDD = VDDC = 3.3V ±5%, TA = -40°°C to +85°°C Note 1: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Note 2: Inputs have pull-up, pull-down resistors that affect input current. Note 3: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. Note 4: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Output buffers are dual staged to control drive strength in order to reduce over/under shoot. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07086 Rev. *B 12/26/2002 Page 3 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer AC Parameters1 SYMBOL PARAMETER MIN Tr / Tf TCLK Input Rise / Fall 2 Fref FrefDC Fvco Tlock Reference Input Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time Tr / Tf Output Clocks Rise / Fall Time 4,5 Fout Maximum Output Frequency TYP MAX UNITS 3.0 ns 25 25 200 110 75 500 10 MHz % MHz ms 0.10 1.0 ns 0.8V to 2.0V 50 110 MHz VCO_SEL = ‘0’ 25 62.5 VCO_SEL = ‘1’ 200 4,5 FoutDC Output Duty Cycle TCCJ TSKEW 45 50 Cycle to Cycle Jitter (peak to 4,5 peak) 4,5 Any Output to Any Output Skew Bypass Mode 55 % 100 ps - - 250 ps -75 - 125 ps Tpd Input to FB_IN Delay (PLL 3,4,5 locked) tpZL, tpZH Output enable time (all outputs) 6 ns tpLZ, tpHZ Output disable time (all outputs) 7 ns Tpd Input to Q Delay (PLL bypassed) 7 ns 3 CONDITIONS VDD = VDDC = 3.3V +/- 5%, TA = -40°°C to +85°°C Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. Note 2: Maximum and minimum input reference is limited by the VCO lock range. Note 3: The Tpd (PLL locked) is input reference frequency dependent. Note 4: Driving series or parallel terminator 50Ω (or 50Ω to VDD/2) transmission lines. Note 5: Outputs loaded with 30pF each Description The Z9953 is a PLL based clock generator that provides low skew and low jitter clock outputs for high performance systems. The Z9953 features a differential PLL to minimize cycle-to-cycle and phase jitter. The PLL is ensured stable operation given that the VCO is configured to run between 200MHz and 500MHz. The input reference is a differential LVPECL clock. All other control inputs are LVCMOS/LVTTL compatible The Z9953 features 9 LVCMOS/LVTTL compatible outputs each capable of driving two series terminated 50Ω transmission lines. With this capability the Z9953 has an effective fan-out of 1:18. The outputs can also be tri-stated when MR/OE# is set high. When used as a zero-delay buffer any of the 9 outputs can be used as the feedback input to the PLL. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07086 Rev. *B 12/26/2002 Page 4 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer 32 Pin TQFP Outline Dimensions INCHES D SYMBOL D1 10° A1 A2 A L e NOM MILLIMETERS MAX MIN NOM MAX A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 - 0.041 0.95 - 1.05 D - 0.354 - - 9.00 - D1 - 0.276 - - 7.00 - b 0.012 - 0.018 0.30 - 0.45 e L b MIN 0.031 BSC 0.018 - 0.80 BSC 0.030 0.45 - 0.75 Ordering Information Part Number Package Type Production Flow Z9953AA 32 PIN TQFP Industrial, -40°C to +85°C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress Z9953AA Date Code, Lot # Z9953AA Package A = TQFP Revision Device Number Notice Cypress Semiconductor Corp. reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corp. assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corp. for the use of its products in the life supporting and medical applications Cypress Semiconductor Corporation http://www.cypress.com Document#: 38-07086 Rev. *B 12/26/2002 Page 5 of 6 Z9953 3.3V, 180MHz, Multi-Output Zero Delay Buffer Document Title: Z9953 3.3V 180 MHz, Multi-Output Zero Delay Buffer Document Number: 38-07086 Rev. ECN No. ** 107122 *A 108065 *B 122771 Issue Date 06/05/01 07/03/01 12/26/02 Cypress Semiconductor Corporation http://www.cypress.com Orig. of Change IKA NDP RBI Description of Change Convert from IMI to Cypress Changed Commercial to Industrial (See page 5) Add power up requirements to maximum ratings information Document#: 38-07086 Rev. *B 12/26/2002 Page 6 of 6