PRELIMINARY CY7C1072AV33 32-Mbit (1M x 32) Static RAM Features specified on the address pins (A0 through A19). If Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23 and I/O24 to I/O31, respectively. • High density 32-Mbit SRAM • High speed — tAA = 10 ns • Low active power • • • • Reading from the device is accomplished by enabling the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte Enable B (BB) is LOW, then data from memory will appear on I/O8 to I/O15. Similarly, Bc and BD correspond to the third and fourth bytes. See the truth table at the back of this data sheet for a complete description of read and write modes. — ICC = 450 mA Operating voltages of 3.3 ± 0.3V 2.0V data retention Automatic power-down when deselected TTL compatible inputs and outputs • Available in standard 119-ball FBGA The input/output pins (I/O0 through I/O31) are placed in a high-impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the byte selects are disabled (BA-D HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). Functional Description The CYM1072AV33 is a 3.3V high-performance 32-Megabit static RAM organized as 1M words by 32 bits. The CY7C1072AV33 is available in a 119-ball grid array (FBGA) package. Writing to the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Enable A (BA) is LOW, then data from the I/O pins (I/O0 through I/O7), is written into the location WE CE1 CE2 1024K x 32 ARRAY OUTPUT BUFFERS SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFERS CONTROL LOGIC Logic Block Diagram OE BA BB BC BD I/O0–I/O31 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 COLUMN DECODER Selection Guide CY7C1072AV33-10 CY7C1072AV33-12 Unit Maximum Access Time 10 12 ns Maximum Operating Current 450 400 mA Maximum Standby Current 100 100 mA Cypress Semiconductor Corporation Document #: 38-05635 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 1, 2005 PRELIMINARY CY7C1072AV33 Pin Configurations 119 BGA (Top View) 1 2 3 4 5 6 7 A I/O16 A A A A A I/O0 B C D E F G H J K L M N P I/O17 I/O18 I/O19 A Bc VDD A CE2 VSS CE1 A VSS A NC VSS A Ba VDD I/O1 I/O2 I/O3 I/O20 VSS VDD VSS VDD VSS I/O4 I/O21 VDD VSS VSS VSS VDD I/O5 I/O22 VSS VDD VSS VDD VSS I/O6 I/O23 NC VDD VSS VSS VDD VSS VSS VSS VDD VDD VSS I/O7 DNU I/O24 I/O25 VDD VSS VSS VDD VSS VSS VSS VDD VDD VSS I/O8 I/O9 VDD VSS VSS VSS VDD I/O10 I/O27 VSS VDD VSS VDD VSS I/O11 I/O28 VDD VSS VSS VSS VDD I/O12 I/O29 A Bd NC Bb A I/O13 I/O30 A A WE A A I/O14 I/O31 A A OE A A I/O15 R T U I/O26 Document #: 38-05635 Rev. *A Page 2 of 9 PRELIMINARY CY7C1072AV33 DC Input Voltage [1] ............................... –0.3V to VCC + 0.3V Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C [1] Supply Voltage on VCC to Relative GND Operating Range ...... –0.5V to 4.6V Range DC Voltage Applied to Outputs in High Z State [1] ...................................–0.3V to VCC + 0.3V Commercial Ambient Temperature VCC 0°C to +70°C 3.3V ± 0.3V Industrial –40°C to +85°C Electrical Characteristics Over the Operating Range -10 Parameter Description Test Conditions Min. -12 Max. Min. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.0 VCC + 0.3 VIL Input LOW Voltage[1] –0.3 0.8 IIX Input Load Current –2 +2 –2 +2 –2 2.4 Max. 2.4 V 0.4 GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE1 > VIH,CE2< VIL; VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE1> VCC – 0.3V, CE2 < 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 –2 Com’l / Ind’l Com’l / Ind’l Unit 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V +2 μA +2 μA 450 400 mA 140 140 mA 100 100 mA Capacitance[2] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. TA = 25°C, f = 1 MHz, VCC = 3.3V Unit 12 pF 15 pF Thermal Resistance[2] Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case)[2] [2] AC Test Loads and Waveforms Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board All-Packages Unit TBD °C/W TBD °C/W [3] 50Ω OUTPUT R1 317Ω VTH = 1.5V Z0 = 50Ω 3.3V 30 pF* * Capacitive Load consists of all OUTPUT components of the Test environment 5 pF ALL INPUT PULSES 3.3V 90% (a) GND Rise time > 1 V/ns 90% 10% 10% R2 351Ω INCLUDING JIG AND SCOPE (b) (c) Fall time > 1 V/ns Notes: 1. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 38-05635 Rev. *A Page 3 of 9 PRELIMINARY CY7C1072AV33 Switching Characteristics[4,5] Over the Operating Range -10 Parameter Description Min. -12 Max. Min. Max. Unit Read Cycle tpower VCC(typical) to the first access[6] 1 10 1 ms tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE active to Data Valid 10 12 ns tDOE OE LOW to Data Valid 5 6 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[7] tLZCE [7] 12 3 CE inactive to High CE active to Power-Up[8] CE inactive to tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low-Z tHZBE Byte Disable to High-Z ns 6 ns 3 ns 5 0 Power-Down[8] tPD 1 3 Z[7] ns ns 5 CE active to Low Z tPU 12 3 1 tHZCE ns 10 6 ns 0 ns 10 12 ns 10 12 ns 1 1 ns 5 6 ns Write Cycle[9, 10] tWC Write Cycle Time 10 tSCE CE active to Write End 7 8 ns tAW Address Set-Up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-Up to Write End 5.5 6 ns tHD Data Hold from Write End 0 0 ns 3 3 ns WE HIGH to Low Z[7] tHZWE WE LOW to High Z[7] tBW Byte Enable to End of Write tLZWE 12 ns 5 7 6 ns 8 ns Data Retention Characteristics Over the Operating Range Parameter Conditions[12] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[2] Chip Deselect to Data Retention Time tR[11] Operation Recovery Time Min. Max Unit 100 mA 2.0 Com’l / Ind’l VCC = VDR = 2.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V 0 V ns μs Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 5. CE indicates a combination of both chip enables. When ACTIVE LOW, CE indicates the CE1 is LOW and CE2 is HIGH. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 11. Test conditions assume tr < 3 ns. 12. No input may exceed VCC + 0.3V. Document #: 38-05635 Rev. *A Page 4 of 9 PRELIMINARY CY7C1072AV33 Data Retention Waveform DATA RETENTION MODE 3.0V VCC 3.0V VDR > 2V tCDR tR CE Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE tLZOE BA, BB, BC, BD tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% ISB Notes: 13. Device is continuously selected. OE, CE1, BA, BB, BC, BD = VIL, CE2 = VIH 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW, CE2 transition HIGH. Document #: 38-05635 Rev. *A Page 5 of 9 PRELIMINARY CY7C1072AV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[5, 16, 17] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BA, BB, BC , BD tSD tHD DATA I/O Write Cycle No. 2 (BA, BB, BC, BD Controlled)[5, 16, 17] tWC ADDRESS tSA tBW BA, BB, BC , BD tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 16. Data I/O is high impedance if OE = VIH or BA/BB/BC/BD = VIH 17. If CE goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05635 Rev. *A Page 6 of 9 PRELIMINARY CY7C1072AV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[5, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BA, BB, BC, BD tHZWE tSD tHD DATA I/O tLZWE Truth Table OE WE BA BB Bc BD I/O0– I/O7 I/O8– I/O15 I/O16– I/O23 I/O24– I/O31 CE1 CE2 Mode Power H X X X X X X X High-Z High-Z High-Z High-Z Power Down (ISB) X L X X X X X X High-Z High-Z High-Z High-Z Power Down (ISB) (ICC) L H L H L L L L Data Out Data Out Data Out Data Out Read All Bits L H L H L H H H Data Out High-Z High-Z High-Z Read Byte A Bits (ICC) Only L H L H H L H H High-Z Data Out High-Z High-Z Read Byte B Bits (ICC) Only L H L H H H L H High-Z High-Z Data Out High-Z Read Byte C Bits (ICC) Only L H L H H H H L High-Z High-Z High-Z Data Out Read Byte D Bits (ICC) Only L H X L L L L L Data In Data In Data In Data In Write All Bits L H X L L H H H Data In High-Z High-Z High-Z Write Byte A Bits (ICC) Only L H X L H L H H High-Z Data In High-Z High-Z Write Byte B Bits (ICC) Only L H X L H H L H High-Z High-Z Data In High-Z Write Byte C Bits (ICC) Only L H X L H H H L High-Z High-Z High-Z Data In Write Byte D Bits (ICC) Only L H H H X X X X High-Z High-Z High-Z High-Z Selected, Outputs (ICC) Disabled Document #: 38-05635 Rev. *A (ICC) Page 7 of 9 PRELIMINARY CY7C1072AV33 Ordering Information Speed (ns) Ordering Code 10 Package Name CY7C1072AV33-10 BBC BB119 Operating Range Package Type 119-Ball (14 x 22 x 2.02 mm) FBGA Commercial CY7C1072AV33-10 BBI 12 Industrial CY7C1072AV33-12 BBC BB119 119-Ball (14 x 22 x 2.02 mm) FBGA Commercial CY7C1072AV33-12 BBI Industrial Package Diagrams 119 FBGA (14 x 22 x 2.02 MM) BB119B -# -#!" !#/2.%2 ¼8 ! ! " " # $ # $ % % & & ( * + , ' ( ¼ ' * + , - . 0 . 0 2 2 4 4 5 5 ¼ # " ¼ 8 2%&%2%.#%*%$%#.! 0+'7)%'(4GMS 3%!4).'0,!.% # Document #: 38-05635 Rev. *A ¼ -!8 # ! 51-85210-** Page 8 of 9 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CY7C1072AV33 Document History Page Document Title: CY7C1072AV33 32-Mbit (1M x 32) Static RAM Module Document Number: 38-05635 REV . ECN NO. Issue Date Orig. of Change Description of Change ** 278072 See ECN RKF New Data Sheet *A 397700 See ECN SYT Converted from “Advance Information” to “Preliminary” Changed the MPN from CYM1072AV33 to CY7C1072AV33 Changed Title from “CY7C1072AV33 32-Mbit (1M x 32) Static RAM Module” to “CY7C1072AV33 32-Mbit (1M x 32) Static RAM“ Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed redundant information from the “Features” and “Functional Description” sections Changed Package offering from 119 PBGA (BG119) to 119 FBGA (BB119) Changed the DC Voltage Applied to Outputs in High-Z State and DC Input Voltage from “-0.5V to VCC + 0.5V” to “-0.3V to VCC + 0.3V” in the Maximum Ratings on Page # 3 Changed VCC from “3.3V +5%” to “3.3V + 0.3V” in the Operating Range table on Page # 3 Edited Test Conditions for ISB1 and ISB2 in the Electrical Characteristics table on Page # 3 Changed tDBE from 5 ns to 10 ns and 6 ns to 12 ns for -10 and -12 speed bins respectively on Page # 4 Moved footnote #15 to footnote # 5 Included spec for ICCDR = 100 mA in the Data Retention Characteristics table on Page# 5 Edited footnote # 12 from “VCC + 0.5V” to “VCC + 0.3V” Edited footnote # 13 to include “CE2 = VIH “ Edited footnote # 15 to include “CE2 transition HIGH” Edited footnote # 16 to include “BA/BB/BC/BD = VIH “ Edited footnote # 17 to include “CE2 goes LOW” Corrected typo on footnote #16 Referenced Footnotes # 5, 16 and 17 on to the Write Cycle No.3 on Page # 7 Corrected Truth table on Page #9 Updated the Ordering Information to include the BB119 Package Document #: 38-05635 Rev. *A Page 9 of 9