STMICROELECTRONICS TDA7535013TR

TDA7535
Delta/sigma cascade 20 bit stereo DAC
Features
■
20-bit resolution single ended output
■
Analog reconstruction third order Chebyshev
filter
■
I2S input data format
■
On chip PLL
■
System clock: 64 Fs
■
2 output channels
■
0.9 VRMS single ended output dynamic
■
3.3 V power supply
■
Reset
■
Sampling rate 36 kHz to 48 kHz
)
s
(
ct
u
d
o
r
P
e
Description
t
e
l
o
)
(s
The TDA7535 is a stereo, digital-to-analog
converter designed for audio application,
including digital interpolation filter, a third order
multi-bit Delta-Sigma DAC, a third order
Chebyshev's reconstruction filter and a differential
to single ended output converter. This device is
fabricated in highly advanced CMOS, where high
speed precision analog circuits are combined with
high density logic circuits. The TDA7535,
according to standard audio converters, can
accept any I2S data format.
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
Table 1.
SO14
s
b
O
The TDA7535 is available in SO14 package. The
total power consumption is less than 75 mW.
TDA7535 is suitable for a wide variety of
applications where high performance are
required. Its low cost and single 3.3 V power
supply make it ideal for several applications, such
as CD players, MPEG audio, MIDI applications,
CD-ROM drives, CD-Interactive, digital radio
applications and so on. An evaluation board is
available to perform measurement and to make
listening tests.
Device summary
Order code
Package
Packing
TDA7535
SO14
Tube
TDA7535013TR
SO14
Tape and reel
February 2009
Rev 8
1/12
www.st.com
12
Contents
TDA7535
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4
Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5
General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6
Low voltage CMOS interface DC electrical characteristics . . . . . . . . . . . . 5
2.7
DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
)
s
(
ct
u
d
o
r
P
e
3
I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
t
e
l
o
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
2/12
s
b
O
TDA7535
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
I2S
I2S
Block diagram
DIGITAL
INPUT 20
FIR1
FIR2
FIR3
20
FS
PLL
8FS
ALU
CLKOUT
23
S&H
ΣΔ MODULATOR
64FS
4
THERMO DECODER &
RANDOMIZER
DIFF TO SINGLE
CONVERTER
D02AU1417
Figure 2.
Pin connection (top view)
N.C.
1
14
SDATA
2
13
SCK
3
N.C.
4
GND_DIG
5
GND_ANA
6
OUTSR
Table 2.
od
7
FSYNC
VDD_DIG
11
N.C.
10
VDD_ANA
9
VCM
8
OUTSL
D01AU1276A
Input/output power
N.C.
-
-
SDATA
I
I2S digital data input
3
SCK
I
I2S clock input
4
N.C.
-
-
5
GND_DIG
P
Digital ground
6
GND_ANA
P
Analog ground
7
OUTSR
O
Right channel single ended output
8
OUTSL
O
Left channel single ended output
9
VCM
P
Reference 1.65 V externally filtered
10
VDD_ANA
P
Analog 3.3 V supply
11
N.C.
-
-
12
VDD_DIG
P
Digital 3.3 V-supply
13
FSYNC
I
I2S Left-right channel selector
14
RESETN
I
Reset (active low)
2
b
O
-O
RESETN
Pin name
1
e
t
e
l
so
t
c
u
Pin function
Pin #
(s)
bs
u
d
o
r
P
e
t
e
l
o
12
ANALOG
OUTPUT
)
s
(
ct
3rd CHEBYSHEV
SC FILTER
Pr
Description
3/12
Electrical specification
TDA7535
2
Electrical specification
2.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
-0.5 to +4.6
-0.5 to +4.6
V
V
Power supplies
Vaio
Analog input and output voltage
-0.5 to (VCC+0.5)
V
Vdio
Digital input and output voltage
-0.5 to (VDD+0.5)
Vdi5
Digital input voltage (5 V tolerant)
-0.5 to 6.5
Operating junction temperature range
-40 to 125
(s)
Tstg
°C
°C
t
e
l
o
)
(s
t
c
u
od
Pr
Rth j-amb
V
Operation at or beyond these limit may result in permanent
damage to the device. Normal operation is not guaranteed at
these extremes.
Thermal data
Symbol
-55 to 150
V
r
P
e
Thermal data
Table 4.
ct
u
d
o
Storage temperature
Warning:
2.2
Unit
VDD
VCC
Tj
Digital
Analog
Value
s
b
O
Parameter
Thermal resistance junction to ambient (1)
Value
Unit
85
°C/W
e
t
e
ol Recommended DC operating conditions
1. In still air.
2.3
s
b
O
Table 5.
Recommended DC operating conditions
Symbol
Parameter
VDD
VCC
4/12
Test condition
Min.
Typ.
Max.
Unit
3.3 V digital power supply voltage
3.15
3.3
3.45
V
3.3 V analog power supply voltage
3.15
3.3
3.45
V
TDA7535
Electrical specification
2.4
Power consumption
Table 6.
Power consumption
Symbol
Idd
Parameter
Test condition
Total maximum current
Min.
Power supply @ 3.3 V and Tj = 125 °C
2.5
General interface electrical characteristics
Table 7.
General interface electrical characteristics
Symbol
Parameter
Test condition
lil
Low level input current
without pull-up device
Vi = 0 V(1)
lih
High level input current
without pull-up device
Vi = Vdd (1)
I/O latch-up current
V < 0 V, V > Vdd
Ilatchup
Electrostatic protection
Vesd
Leakage, 1
Min.
Max.
Unit
21.5
25
mA
Typ.
Max.
Unit
1
μA
1
μA
)
s
(
ct
u
d
o
r
P
e
200
μA(2)
Typ.
t
e
l
o
mA
2000
V
1. The leakage currents are generally very small, <1nA. The value given here, 1mA, is the maximum that can occur after an
Electrostatic Stress on the pin.
2. Human body model.
)
(s
s
b
O
2.6
Low voltage CMOS interface DC electrical characteristics
Table 8.
Low voltage CMOS interface DC electrical characteristics
Symbol
Vil
t
c
u
d
o
r
Test Condition
Min.
Low Level Input Voltage
P
e
t
e
l
o
Vih
Vhyst
Parameter
High Level Input Voltage
Schmitt trigger hysteresis
Typ.
Max.
Unit
0.2*Vd
V
d
0.8*Vd
V
d
0.8
V
s
b
O
5/12
Electrical specification
2.7
TDA7535
DAC electrical characteristics
Table 9.
DAC electrical characteristics
Vdd = 3.3 V; Tamb = 25 °C; Input signal frequency = sinus wave generated by
audio precision Sys.2; Input signal amplitude (see notes); Noise integration
bandwidth = 20 Hz to 22 kHz (A- weighted)
Parameter
Test condition
Min.
Typ.
Noise + distortion (1)
@0 dB
@-6 dBb
@-40 dB
@-60 dB
Total harmonic distortion
see note (2)
70(3)
94
Dynamic range
see note (4)
84(5)
96
89
94
96
96
(6)
Crosstalk
see note
Full scale output voltage
Vdd = 3.15 to 3.45 V
Full scale input
0.8
ete
36
ol
Passband ripple
s
b
O
@ 3dB
@ 90dB
44.1kHz sampling rate
)-
Interchannel gain mismatch
)
s
(
ct
dB
dB
du
o
r
P
0.9
Unit
dB
dB
dB
dB
-95
Input sampling rate
Stopband
Max.
dB
1.0
Vrms
48
kHz
0.12
21.53
dB
24.80
0.05
kHz
0.1
s
(
t
c
dB
1. It is the ratio between the maximum input signal and the integration of the in-band noise after deducing the
power of signal fundamental. It depends on the input signal amplitude. In this case 0dB means full scale
digital, 1 kHz frequency used.
u
d
o
2. It is the ratio of the rms value of the signal fundamental component at 0 dB (full scale digital) to the rms
value of all of the harmonic components in the band.
r
P
e
3. By correlation to beuch results. ATE limits are 60 dB.
4. Measured using the SNR at -60dB input signal, with 60dB added to compensate for small input signal.
t
e
l
o
5. By correlation to beuch results. ATE limits are 80 dB.
6. Left channel on with 0dB/1kHz input signal, Right channel on with DC input signal.
s
b
O
6/12
I2S interface
TDA7535
I2S interface
3
I2S interface diagram
Figure 3.
Left
Right
FSYNC
32 * SCK
32 * SCK
SCK
LSB
MSB
I2S
Figure 4.
20 Bits
20 Bits
SDATA
r
P
e
timings
t
e
l
o
SDATA
Valid
FSYNC
)-
s
(
t
c
SCK
u
d
o
e
t
e
ol
Table 10.
s
b
O
Pr
tlrw-
s
b
O
Valid
tsckf
tsckr
tlrw+
tsds
tsdh
tsckpl
tsckph
tsck
Timing characteristics
Timing
tsck
u
d
o
LSB
MSB
)
s
(
ct
Description
Clock cycle(1)
Min.
Max.
1/(64*Fs) - 150psRMS 1/(64*Fs) + 150psRMS
Unit
ns
tsckpl
SCK phase low
0.5*tsck - 1%
0.5*tsck +1%
ns
tsckph
SCK phase high
0.5*tsck - 1%
0.5*tsck +1%
ns
tlrw-
FSYNC switching time window before SCK falling
edge(2)
0
0.125*tsck-10
ns
tlrw+
FSYNC switching time window after SCK falling
edge(2))
0
0.125*tsck-10
ns
tsds
SDATA setup time
60
ns
tsdh
SDATA hold time
30
ns
7/12
I2S interface
Table 10.
TDA7535
Timing characteristics (continued)
Timing
Description
Min.
Max.
Unit
tsckr
SCK rise time
22
ns
tsckf
SCK fall time
20
ns
1. SCK clock defines the Fs, being the Sample Rate. This input clock needs a jitter below ~212psRMS.
2. FSYNC switches inside the time window as specified w.r.t. to falling edge of SCK.
Figure 5.
Power up and reset sequence
VDD
)
s
(
ct
RESET
u
d
o
TRES
TRES
Figure 6.
t
c
u
d
o
r
P
e
s
b
O
8/12
D02AU1418
r
P
e
Frequency response
)
(s
t
e
l
o
Min 50ms
s
b
O
t
e
l
o
TDA7535
4
Application circuit
Application circuit
Figure 7.
Application circuit
μP
R2 10K
+3.3 VDIG
SW1
C7
10μF
10V
10μF
U4
TP1
SDATA
2
+3.3VANA
RESETN
14
10
TP2
SCK
2
I S
3
12
TP3
FSYNC
100nF(*)
VDD_ANA
10μH
bead inductor
100nF(*)
VDD_DIG
TP5
GND_DIG
GND_ANA
VCM
C16
100nF
(*)
C15
47μF 10V
(*)
)
s
(
ct
10μF
13
8
5
J3
BNC
u
d
o
OUTSL
OUTSL
TP6
r
P
e
6
TP7
9
t
e
l
o
7
OUTSR
J4
BNC
OUTSR
TP8
D02AU1419B
s
b
O
(*) AS CLOSE AS POSSIBLE TO THE PIN
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
9/12
Package information
5
TDA7535
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 8.
SO14 mechanical data and package dimensions
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
1.35
1.75
0.053
0.069
A1
0.10
0.30
0.004
0.012
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.01
8.55
8.75
0.337
0.344
4.0
0.150
D
(1)
E
3.80
e
1.27
5.8
6.20
0.228
h
0.25
0.50
0.01
L
0.40
1.27
k
)
(s
0.016
t
c
u
0.10
r
P
e
t
e
l
o
0.157
0˚ (min.), 8˚ (max.)
ddd
u
d
o
0.050
H
)
s
(
ct
s
b
O
0.244
0.02
0.050
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO14
d
o
r
P
e
t
e
l
o
s
b
O
0016019 D
10/12
TDA7535
6
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
Changes
13-Dec- 2003
5
Initial release.
21-Dec- 2005
6
Update electrical characteristics.
Add revision history table.
03-Feb-2006
7
Updated max. value of tsckr and tsckt parameter on page 5/9.
06-Feb-2009
8
Document reformatted.
Updated Section 5: Package information on page 10.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
11/12
TDA7535
)
s
(
ct
Please Read Carefully:
u
d
o
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
r
P
e
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
t
e
l
o
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
)
(s
s
b
O
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
t
c
u
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
d
o
r
P
e
t
e
l
o
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
s
b
O
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2009 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
12/12