PD - 95443B
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l Lead-Free
IRFR3707ZPbF
IRFU3707ZPbF
HEXFET® Power MOSFET
VDSS RDS(on) max
9.5m:
30V
Benefits
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
D-Pak
IRFR3707ZPbF
Qg
9.6nC
I-Pak
IRFU3707ZPbF
Absolute Maximum Ratings
Parameter
VDS
Drain-to-Source Voltage
Max.
Units
30
V
VGS
Gate-to-Source Voltage
± 20
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V
56
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
39
IDM
Pulsed Drain Current
220
PD @TC = 25°C
Maximum Power Dissipation
50
PD @TC = 100°C
Maximum Power Dissipation
25
c
f
f
Linear Derating Factor
0.33
TJ
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
A
W
W/°C
°C
300 (1.6mm from case)
Thermal Resistance
Parameter
RθJC
Junction-to-Case
RθJA
Junction-to-Ambient (PCB Mount)
RθJA
Junction-to-Ambient
g
Typ.
Max.
Units
–––
3.0
°C/W
–––
50
–––
110
Notes through
are on page 11
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1
05/14/08
IRFR/U3707ZPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
∆ΒVDSS/∆TJ
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
30
–––
–––
0.023
–––
–––
RDS(on)
Static Drain-to-Source On-Resistance
–––
–––
7.5
10
9.5
12.5
VGS(th)
∆VGS(th)/∆TJ
Gate Threshold Voltage
Gate Threshold Voltage Coefficient
1.35
–––
1.80
-5.0
2.25
V VDS = VGS, ID = 25µA
––– mV/°C
IDSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
1.0
150
µA
VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
–––
–––
–––
–––
100
-100
nA
VGS = 20V
VGS = -20V
gfs
Qg
Forward Transconductance
Total Gate Charge
71
–––
–––
9.6
–––
14
S
VDS = 15V, ID = 12A
Qgs1
Qgs2
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
–––
–––
2.6
0.90
–––
–––
Qgd
Qgodr
Gate-to-Drain Charge
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
3.5
2.6
–––
–––
Output Charge
–––
–––
4.4
5.8
–––
–––
td(on)
tr
Turn-On Delay Time
Rise Time
–––
–––
8.0
11
–––
–––
td(off)
tf
Ciss
Turn-Off Delay Time
Fall Time
Input Capacitance
–––
–––
–––
12
3.3
1150
–––
–––
–––
ns
Clamped Inductive Load
Coss
Crss
Output Capacitance
Reverse Transfer Capacitance
–––
–––
260
120
–––
–––
pF
VDS = 15V
ƒ = 1.0MHz
Qsw
Qoss
V VGS = 0V, ID = 250µA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 15A
VGS = 4.5V, ID = 12A
e
e
nC
VDS = 15V
VGS = 4.5V
ID = 12A
See Fig. 16
nC
VDS = 15V, VGS = 0V
VDD = 16V, VGS = 4.5V
ID = 12A
e
VGS = 0V
Avalanche Characteristics
EAS
IAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
EAR
Repetitive Avalanche Energy
c
d
c
Typ.
–––
–––
Max.
42
12
Units
mJ
A
–––
5.0
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
f
Conditions
IS
Continuous Source Current
–––
–––
56
ISM
(Body Diode)
Pulsed Source Current
–––
–––
220
showing the
integral reverse
VSD
(Body Diode)
Diode Forward Voltage
–––
–––
1.0
V
p-n junction diode.
TJ = 25°C, IS = 12A, VGS = 0V
trr
Qrr
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
25
17
38
26
ns
nC
TJ = 25°C, IF = 12A, VDD = 15V
di/dt = 100A/µs
ton
Forward Turn-On Time
2
c
MOSFET symbol
A
D
G
S
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR/U3707ZPbF
10000
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
TOP
1000
VGS
10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.5V
2.2V
10
1
0.1
2.2V
0.01
100
BOTTOM
10
2.2V
1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.001
0.1
0.1
1
10
0.1
VDS, Drain-to-Source Voltage (V)
1
10
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
100
RDS(on) , Drain-to-Source On Resistance
(Normalized)
1000
ID, Drain-to-Source Current (Α)
VGS
10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.5V
2.2V
T J = 175°C
10
1
TJ = 25°C
0.1
VDS = 10V
20µs PULSE WIDTH
0.01
ID = 30A
VGS = 10V
1.5
1.0
0.5
0
2
4
6
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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8
-60 -40 -20 0
20 40 60 80 100 120 140 160 180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRFR/U3707ZPbF
10000
6.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
ID= 12A
Ciss
1000
Coss
Crss
VDS= 24V
VDS= 15V
5.0
VGS, Gate-to-Source Voltage (V)
C, Capacitance(pF)
C oss = C ds + C gd
4.0
3.0
2.0
1.0
100
0.0
1
10
100
0
VDS, Drain-to-Source Voltage (V)
2
4
6
8
10
12
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
1000
1000.00
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100.00
T J = 175°C
10.00
1.00
0.10
TJ = 25°C
VGS = 0V
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10
100µsec
1msec
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
0
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U3707ZPbF
60
Limited By Package
50
ID, Drain Current (A)
VGS(th) Gate threshold Voltage (V)
2.5
40
30
20
10
2.0
ID = 250µA
1.5
1.0
0
25
50
75
100
125
150
-75 -50 -25
175
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
R1
R1
0.05
0.1
τJ
0.02
0.01
τ1
τ2
τ2
Ci= τi/Ri
Ci= τi/Ri
SINGLE PULSE
( THERMAL RESPONSE )
0.01
τJ
τ1
R2
R2
R3
R3
τ3
τC
τ
τ3
Ri (°C/W) τi (sec)
0.823
0.000128
1.698
0.481
0.000845
0.016503
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U3707ZPbF
15V
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
20V
VGS
DRIVER
L
VDS
200
ID
TOP
3.7A
5.6A
BOTTOM 12A
180
160
140
120
100
80
60
40
20
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
LD
I AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator
Same Type as D.U.T.
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
Fig 14a. Switching Time Test Circuit
VDS
90%
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
10%
VGS
td(on)
tr
td(off)
tf
Fig 14b. Switching Time Waveforms
6
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IRFR/U3707ZPbF
D.U.T
Driver Gate Drive
P.W.
+
+
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by R G
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D=
Period
V DD
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRFR/U3707ZPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + Pdrive + Poutput
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ (Qg × Vg × f )
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgd
+⎜I ×
× Vin ×
ig
⎝
⎞ ⎛
Qgs 2
⎞
f⎟ + ⎜ I ×
× Vin × f ⎟
ig
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRFR/U3707ZPbF
D-Pak (TO-252AA) Package Outline
D-Pak (TO-252AA) Part Marking Information
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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9
IRFR/U3707ZPbF
I-Pak (TO-251AA) Package Outline
(Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
(;$03/( 7+,6,6$1,5)8
:,7+$66(0%/<
/27&2'(
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRFR/U3707ZPbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.58mH, RG = 25Ω,
IAS = 12A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 05/2008
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11