Data Sheet No. PD60240 IRS20124(S)PbF Digital Audio Driver with Discrete Deadtime and Protection Product Summary Features • 200 V high voltage ratings deliver up to 1000 W • • • • • • • output power in Class D audio amplifier applications Integrated deadtime generation and bi-directional over-current sensing simplify design Programmable compensated preset deadtime for improved THD performances over temperature High noise immunity Shutdown function protects devices from overload conditions Operates up to 1 MHz 3.3 V/5 V logic compatible input RoHS compliant VSUPPLY 200 V max. IO+/- 1 A / 1.2 A typ. Selectable Deadtime 15 ns, 25 ns, 35 ns, 45 ns typ. Prop Delay Time 60 ns typ. Bi-Directional OverCurrent Sensing Package 14-Lead SOIC Typical Application Diagram <20 V IN IN <20 V <200 V NC OCSET 1 NC DT/SD VB OCSET 2 HO OC SD www.irf.com OC VS COM NC LO VCC IRS20124 1 IRS20124S(PbF) Description The IRS20124 is a high voltage, high speed power MOSFET driver with internal deadtime and shutdown functions specially designed for Class D audio amplifier applications. The internal dead time generation block provides accurate gate switch timing and enables tight deadtime settings for better THD performances. In order to maximize other audio performance characteristics, all switching times are designed for immunity from external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logic inputs are compatible with LSTTL output or standard CMOS down to 3.0 V without speed degradation. The output drivers feature high current buffers capable of sourcing 1.0 A and sinking 1.2 A. Internal delays are optimized to achieve minimal deadtime variations. Proprietary HVIC and latch immune CMOS technologies guarantee operation down to Vs= –4 V, providing outstanding capabilities of latch and surge immunities with rugged monolithic construction. Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. All currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol VB Vs VHO VCC VLO VIN VOC VOCSET1 VOCSET2 dVs/dt PD RthJA TJ TS TL www.irf.com Definition Min. Max. High-side floating supply voltage High-side floating supply voltage -0.3 VB-20 220 VB+0.3 High-side floating output voltage Low-side fixed supply voltage Low-side output voltage Input voltage Vs-0.3 -0.3 -0.3 -0.3 VB+0.3 20 Vcc+0.3 Vcc+0.3 OC pin input voltage OCSET1 pin input voltage OCSET2 pin input voltage Allowable Vs voltage slew rate -0.3 -0.3 -0.3 - Vcc+0.3 Vcc+0.3 Vcc+0.3 50 Maximum power dissipation Thermal resistance, junction to ambient Junction temperature Storage temperature -55 1.25 100 150 150 - 300 Lead temperature (soldering, 10 seconds) Units V V/ns W °C/W °C 2 IRS20124S(PbF) Recommended Operating Conditions For proper operation, the device should be used within the recommended conditions. The Vs and COM offset ratings are tested with all supplies biased at a 15 V differential. Symbol Definition Min. Max. Vs+10 Note 1 Vs 10 Vs+18 200 VB 18 VCC VCC VCC VCC VB VS VHO VCC High-side floating supply absolute voltage High-side floating supply offset voltage High-side floating output voltage Low-side fixed supply voltage VLO VIN VOC VOCSET1 Low-side output voltage Logic input voltage OC pin input voltage OCSET1 pin input voltage 0 0 0 0 VOCSET2 TA OCSET2 pin input voltage Ambient Temperature 0 -40 Units V VCC 125 °C Note 1: Logic operational for VS equal to -8 V to 200 V. Logic state held for VS equal to -8 V to -VBS. Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15 V, CL = 1n F and TA = 25 °C unless otherwise specified. Fig. 2 shows the timing definitions. Symbol Definition Min. Typ. Max. Units Test Conditions ton High & low-side turn-on propagation delay — 60 80 VS=0 V toff tr tf tsd High & low-side turn-off propagation delay Turn-on rise time Turn-off fall time Shutdown propagation delay — — — — 60 25 15 140 80 40 35 200 VS=200 V toc Propagation delay time from Vs>Vsoc+ to OC — 280 — OC pulse width OC input filter time — — 100 200 — — 0 15 40 VDT>VDT1 5 25 50 VDT1>VDT> VDT2 10 35 60 VDT2>VDT>VDT3 15 45 70 VDT3>VDT>VDT4 twoc min toc filt Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) DT1 DT2 DT3 DT4 Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO) Deadtime: LO turn-off to HO turn-on (DTLO-HO) & HO turn-off to LO turn-on (DTHO-LO)VDT= VDT4 www.irf.com OCSET1=3.22 V OCSET2=1.20 V ns 3 IRS20124S(PbF) Static Electrical Characteristics VBIAS (VCC , VBS) = 15 V and TA = 25 °C unless otherwise specified. Symbol VIH VIL VOH VOL UVCC+ UVCCUVBS+ UVBSIQBS Min. Typ. Max. Units Test Conditions Logic high input voltage Definition 2.5 — — Logic low input voltage High level output voltage, VBIAS – VO Low level output voltage, VO Vcc supply UVLO positive threshold — — — 8.3 — — — 9.0 1.2 1.2 0.1 9.7 7.5 8.3 7.5 — 8.2 9.0 8.2 — 8.9 9.7 8.9 1 — — — — — — 3 0 4 50 10 1.0 Vcc supply UVLO negative threshold High-side well UVLO positive threshold High-side well UVLO negative threshold High-side quiescent current IQCC ILK IIN+ IIN- Low-side quiescent current High-to-low-side leakage current Logic “1” input bias current Logic “0” input bias current Io+ IoVDT1 VDT2 Output high short circuit current (source) — 1.0 — Output low short circuit current (sink) — 1.2 — DT mode select threshold 1 0.8(Vcc) 0.89(Vcc) 0.97(Vcc) DT mode select threshold 2 0.51(Vcc) 0.57(Vcc) 0.63(Vcc) VDT3 VDT4 DT mode select threshold 3 DT mode select threshold 4 0.32(Vcc) 0.36(Vcc) 0.40(Vcc) 0.21(Vcc) 0.23(Vcc) 0.25(Vcc) Vcc=10 V -20 V Io=0 A V mA µA A V VDT=Vcc VB=VS =200 V VIN=3.3 V VIN=0V Vo=0 V, PW<10 µs Vo=15 V, PW<10 µs VSOC+ OC threshold in Vs 0.75 1.0 1.25 OCSET1=3.22 V OCSET2=1.20 V VSOC- OC threshold in Vs -1.25 -1.0 -0.75 OCSET1=3.22 V OCSET2=1.20 V www.irf.com 4 IRS20124S(PbF) Lead Definitions Symbol Description VCC VB HO Low-side logic supply voltage High-side floating supply High-side output VS IN DT/SD COM High-side floating supply return Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO Input for programmable deadtime, referenced to COM. shutdown LO and HO when tied to COM Low-side supply return LO OC OC SET1 OC SET2 Low-side output Over-current output (negative logic) Input for setting negative over current threshold Input for setting positive over current threshold 1 IN NC 14 2 OCSET1 NC 13 3 DT/SD VB 12 4 OCSET2 HO 11 5 OC VS 10 6 COM NC 9 7 LO VCC 8 IR20124S 14 Lead SOIC (narrow body) www.irf.com 5 IRS20124S(PbF) Block Diagram VB LEVEL SHIFTER IN DEAD TIME UV DETECT S R UV Q HO SD VS CURRENT SENSING DT/SD Vcc UV DETECT LO DELAY www.irf.com OCSET2 OCSET1 OC COM 6 IRS20124S(PbF) IN 50% 50% ton(L) toff(L) toff(H) ton(H) 90% LO 10% DTHO- LO DTLO- HO 90% HO 10% Figure 1. Switching Time Waveform Definitions DT/SD VSD HO LO 90% TSD Figure 2. Shutdown Waveform Definitions www.irf.com 7 IRS20124S(PbF) LO COM toc filt VS VS VSoc+ COM VSoc- Vsoct COM HIGH OC OC tdoc COM twoc Figure 4. OC Waveform Definitions Figure 3. OC Input FilterTime Definitions IN NC OCSET1 NC DT/SD 10k VB OCSET2 HO __ OC VS 15V COM Vsoc+ Vsoc- LO NC VCC 15V OC Vsoc+ VS COM Vsoc- OC Figure 5. OC Waveform Definitions www.irf.com 8 200 200 160 160 Turn-On Delay Time (ns) Turn-On Delay Time (ns) IRS20124S(PbF) 120 80 40 0 -50 -25 0 25 50 75 100 120 80 40 125 0 10 12 Temperature ( C) o 0 120 120 Turn-Off Time (ns) Turn-Off Time (ns) 150 Max. 60 0 0 -50 18 20 18 20 Figure 6B. Turn-On Tim e vs. Supply Voltage 0 150 30 0 16 V BIAS Supply Voltage (V) Figure 6A. Turn-On Tim e vs. Tem perature 0 90 14 Typ. Max. 90 60 Typ. 30 0 -25 0 25 50 75 Temperature (oC) Figure 7A. Turn-Off Time vs. Temperature www.irf.com 100 125 10 12 14 16 VBIAS Supply Voltage (V) Figure 7B. Turn-Off Time vs. Supply Voltage 9 IRS20124S(PbF) 60 Turn-On Rise Time (ns) Turn-On Rise Time (ns) 60 50 40 30 20 10 -50 50 40 30 20 10 -25 0 25 50 75 100 125 10 Temperature ( oC) 14 16 18 20 V BIAS Supply Voltage (V) Fiure 8A. Turn-On Rise Tim e vs.Tem perature Figure 8B. Turn-On Rise Tim e vs. Supply Voltage 50 50 Turn-Off Fall Time (ns) Turn-Off Fall Time (ns) 12 40 30 20 10 0 40 30 20 10 0 -50 -25 0 25 50 75 100 Temperature ( C) o Figure 9A. Turn-Off Fall Tim e vs. Tem perature www.irf.com 125 10 12 14 16 18 20 V BIAS Supply Voltage (V) Figure 9B. Turn-Off Fall Tim e vs. Supply Voltage 10 5 5 4 4 Input Voltage (V) Input Voltage (V) IRS20124S(PbF) 3 Min. 2 3 2 Min. 1 1 -50 -25 0 25 50 75 100 10 125 12 4 3 3 Input Voltage (V) Input Voltage (V) 4 2 Max. 1 0 25 50 75 100 Temperatre ( C) o Figure 11A. Logic "0" Input Voltage vs. Temperature www.irf.com 18 20 Figure 10B. Logic "1" Input Voltage vs. Supply Voltage Figure 10A. Logic "1" Input Voltage vs. Tem perature -25 16 V CC Supply Voltage (V) Temperature (oC) 0 -50 14 125 2 Max. 1 0 10 12 14 16 18 20 V CC Supply Voltage (V) Figure 11B. Logic "0" Input Voltage vs. Supply Voltage 11 4 High Level Output Voltage (V) High Level Output Voltage (V) IRS20124S(PbF) 3 2 Max. 1 0 -1 -50 -25 0 25 50 75 100 4 3 2 Max. 1 0 10 125 12 Low Level Output Voltage (V) Low Level Output Voltage (V) 0.25 0.20 0.15 Max. 0.05 -25 0 25 50 75 100 Temperature ( C) o Figure 13A. Low Level Output vs.Temperature www.irf.com 18 20 Figure 12B. High Level Output vs. Supply Voltage Figure 12A. High Level Output vs. Temperature 0.00 -50 16 V CC Supply Voltage (V) Temperature (oC) 0.10 14 125 0.25 0.20 0.15 Max. 0.10 0.05 0.00 10 12 14 16 18 20 VCC Supply Voltage (V) Figure 13B. Low Level Output vs. Supply Voltage 12 300 250 200 150 100 50 Max. 0 -50 -25 0 25 50 75 100 125 Offset Supply Leakage Current (µA) Offset Supply Leakage Current (µA) IRS20124S(PbF) 110 90 70 Max. 50 30 Typ. 10 -10 50 80 Temperature ( oC) 110 140 170 200 V B Boost Voltage (V) Figure 14B. Offset Supply Leakage Current vs. Supply Voltage Figure 14A. Offset Supply Leakage Current vs. Temperature V B= 200 V 2.5 V BS Supply Current (µA) V BS Supply Current (µA ) 3 2.0 1.5 1.0 0.5 2 2 1 1 0 0.0 -50 -25 www.irf.com 0 25 50 75 100 125 10 12 14 16 18 Temperature (oC) V BS Supply Voltage (V) Figure 15A. V BS Supply Current vs. Tem perature Figure 15B. V BS Supply Current vs. Supply Voltage 20 13 IRS20124S(PbF) 10 V cc Supply Current (µΑ) V cc Supply Current (µA) 10 8 6 4 Max. 2 0 -50 8 6 Max. 4 2 0 -25 0 25 50 75 100 10 125 12 18 20 Figure 16B. V CC Supply Current vs. Supply Voltage Figure 16A. V CC Supply Current vs. Temperature 30 Logic "1" Input Current (µA) 30 Logic "1" Input Current (µA) 16 V CC Supply Voltage (V) Temperature (oC) 24 18 12 6 0 -50 14 -25 0 25 50 75 100 Temperature (oC) Figure 17A. Logic "1" Input Current vs. Tem perature www.irf.com 125 24 18 12 6 0 10 12 14 16 18 20 V CC Supply Voltage (V) Figure 17B. Logic "1" Input Current vs. Supply Voltage 14 6 5 Max 4 3 2 1 0 -50 -25 6 Logic "0" Input Bias C urrent (µA) Lo gic "0" Input Bias Current (µA) IRS20124S(PbF) 0 25 50 75 100 Max 5 4 3 2 1 0 10 125 12 16 18 20 Supply Voltage (V) Temperature (°C) Figure 18A. Logic "0" Input Bias Current vs. Temperature Figure 18B. Logic "0" Input Bias Current vs. Voltage 11 10 V cc Supply Cur rent (µΑ ) 11 V cc Supply Cur rent (µΑ) 14 10 Max. 9 Typ. 8 Min. 7 6 -50 -25 0 25 50 75 100 Temperature ( C) o Figure 19. V CC Undervoltage Threshold (+) vs. Temperature www.irf.com 125 Max. 9 Typ. 8 Min. 7 6 -50 -25 0 25 50 75 100 125 Temperature ( C) o Figure 20. V CC Undervoltage Threshold (-) vs. Temperature 15 IRS20124S(PbF) 11 VBS Supply Current (µA) VBS Supply Current (µA) 11 10 9 8 7 10 9 8 7 6 6 -50 -25 0 25 50 75 100 -50 125 -25 0 75 100 125 Temperature ( C) Figure 22. V BS Undervoltage Threshold (-) vs. Tem perature Figure 21. V BS Undervoltage Threshold (+) vs. Tem perature 1.5 Output Sink Current (Α) 1.5 Output Source Current (Α) 50 o Temperature (oC) 1.3 1.1 0.9 0.7 25 Typ. 0.5 1.3 1.1 0.9 Typ. 0.7 0.5 10 12 14 16 18 V BIAS Supply Voltage (V) Figure 23. Output Source Current vs. Supply Voltage www.irf.com 20 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 24. Output Sink Current vs. Supply Voltage 16 -5 16 Typ. -7 Max. 15 -9 VDT1 (V) VS Offset Supply Voltage (V) IRS20124S(PbF) -11 14 Typ. 13 Min. 12 -13 11 -50 -15 10 12 14 16 18 20 -25 0 125 8 7 Max. 9 VDT3 (V) VDT2 (V) 100 Figure 26. DT Mode Select Threshold (1) vs. Temperature 11 7 75 o Figure 25. Maximum V S Negative Offset vs. Supply Voltage 8 50 Temperature ( C) V BS Floting Supply Voltage (V) 10 25 Typ. Min. 6 -50 -25 0 25 50 75 100 125 Temperature ( C) Figure 27. DT Mode Select Threshold (2) vs. Temperature Max. Typ. 5 4 o www.irf.com 6 Min. 3 -50 -25 0 25 50 75 100 125 Temperature ( C) o Figure 28. DT Mode Select Threshold (3) vs. Temperature 17 4.5 60 4.0 52 3.5 44 DTLO-HO (ns) VDT4 (V) IRS20124S(PbF) 3.0 2.5 2.0 -50 -25 0 25 50 75 100 36 Typ. 28 20 -50 125 -25 0 2.0 -0.3 1.6 -0.6 Max. 1.2 Typ. Min. 0.4 0.0 -25 0 25 50 75 100 125 Temperature ( oC) Figure 31. Positive OC Threshold(+) in V S vs. Tem perature www.irf.com 75 100 125 Figure 30. DT LO Turn-Off to HO TurnOon (3) vs. Tem perature Negative OC TH (V) Positive OC TH (V) Figure 29. DT Mode Select Threshold (4) vs. Tem perature -50 50 Temperature ( C) Temperature ( C) 0.8 25 o o Max. -0.9 Typ. -1.2 Min. -1.5 -1.8 -50 -25 0 25 50 75 100 125 Temperature ( C) o Figure 32. Negative OC Threshold(-) in V S vs. Temperature 18 65 65 55 55 45 140V 70V 0V 35 25 Temperature (oC) Temperature (oC) IRS20124S(PbF) 140v 70v 0v 45 35 25 15 15 1 10 100 1 1000 100 Figure 34 33.. IRS20124S vs. Frequency (IRFBC30) Rgate=22 Ω , V CC=12 V Figure 33 32.. IRS20124S vs. Frequency (IRFBC20) Rgate=33 Ω , VCC=12 V 65 75 140V 140V 70V 0V 45 35 25 Temperature (oC) 65 55 1000 Frequency (kHz) Frequency (kHz) Temperature (oC) 10 70V 0V 55 45 35 25 15 15 1 10 100 1000 Frequency (kHz) Figure 334. 5. IRS20124S vs. Frequency (IRFBC40) Rgate=15 Ω , V CC=12 V www.irf.com 1 10 100 1000 Frequency (kHz) 6. IRS20124S vs. Frequency (IRFPE50) Figure 335. Rgate=10 Ω , V CC=12 V 19 IRS20124S(PbF) Functional description 90% Effective dead-time Programmable Dead-time The IRS20124 has an internal deadtime generation block to reduce the number of external components in the output stage of a Class D audio amplifier. Selectable deadtime through the DT/SD pin voltage is an easy and reliable function, which requires only two external resistors. The deadtime generation block is also designed to provide a constant deadtime interval, independent of Vcc fluctuations. Since the timings are critical to the audio performance of a Class D audio amplifier, the unique internal deadtime generation block is designed to be immune to noise on the DT/SD pin and the Vcc pin. Noise-free programmable deadtime function is available by selecting deadtime from four preset values, which are optimized and compensated. How to Determine Optimal Deadtime Please note that the effective deadtime in an actual application differs from the deadtime specified in this datasheet due to finite fall time, tf. The deadtime value in this datasheet is defined as the time period from the starting point of turn-off on one side of the switching stage to the starting point of turn-on on the other side as shown in Fig. 5. The fall time of MOSFET gate voltage must be subtracted from the deadtime value in the datasheet to determine the effective dead time of a Class D audio amplifier. (Effective deadtime) = (Deadtime in datasheet) – (fall time, tf) www.irf.com HO (or LO) 10% tf LO (or HO) Deadtime 10% Effective Deadtime A longer deadtime period is required for a MOSFET with a larger gate charge value because of the longer tf. A shorter effective deadtime setting is always beneficial to achieve better linearity in the Class D switching stage. However, the likelihood of shoot-through current increases with narrower deadtime settings in mass production. Negative values of effective deadtime may cause excessive heat dissipation in the MOSFETs, potentially leading to their serious damage. To calculate the optimal deadtime in a given application, the fall time (tf)for both output voltages, HO and LO, in the actual circuit needs to be measured. In addition, the effective deadtime can also vary with temperature and device parameter variations. Therefore, a minimum effective deadtime of 10 ns is recommended to avoid shoot-through current over the range of operating temperatures and supply voltages. 20 IRS20124S(PbF) DT/SD pin DT/SD pin provides two functions: 1) setting deadtime and 2) shutdown. The IRS20124 determines its operation mode based on the voltage applied to the DT/SD pin. An internal comparator translates which mode is being used by comparing internal reference voltages. Threshold voltages for each mode are set internally by a resistive voltage divider off Vcc, negating the need of using a precise absolute voltage to set the mode. Deadtime mode DT1 DT2 DT3 DT4 R1 (Ω) <10k 3.3k 5.6k 8.2k R2 (Ω) Open 8.2k 4.7k 3.3k DT/SD (V) 1.00 (Vcc) 0.71 (Vcc) 0.46 (Vcc) 0.29 (Vcc) Table 1. Suggested Resistor Values for Deadtime Settings Shutdown Operational Mode 15nS Dead-time 25nS 35nS 45nS Shutdown 0.23xVcc 0.36xVcc 0.57xVcc 0.89xVcc Vcc VDT Deadtime Settings vs VDT Voltage Design Example Table 1 shows suggested values of resistance for setting the deadtime. Resistors with up to 5% tolerance can be IRS20124 used if these >0.5mA listed values are Vcc followed. R1 DT/SD R2 COM External Resistor www.irf.com Since IRS20124 has internal deadtime generation, independent inputs for HO and LO are no longer provided. Shutdown mode is the only way to turn off both MOSFETs simultaneously to protect them from over current conditions. If the DT/SD pin detects an input voltage below the threshold, VDT4, the IRS20124 will output 0 V at both HO and LO outputs, forcing the switching output node to go into a high impedance state. Over Current Sensing In order to protect the power MOSFET, IRS20124 has a feature to detect over-current conditions, which can occur when speaker wires are shorted together. The over-current shutdown feature can be configured by combining the current sensing function with the shutdown mode via the DT/SD pin. Load Current Direction in Class D Audio Application In a Class D audio amplifier, the direction of the load current alternates according to the audio input signal. An over current condition can therefore happen during either a positive current cycle or a negative current cycle. It should be noted that 21 IRS20124S(PbF) each MOSFET carries a part of the load current in an audio cycle. Bi-directional current sensing offers over current detection capabilities in both cases by monitoring only the low side MOSFET. Load Current 0 IRS20124 measures the current during the period when the low side MOSFET is turned on. Under normal operating conditions, Vs voltage for the low side switch is well within the trip threshold boundaries, VSOC- and VSOC+. In the case of Fig. 9(b) which demonstrates the amplifier sourcing too much current to the load, the Vs node is found below the trip level, VSOC-. In Fig. 9(c) with opposite current direction, the amplifier sinks too much current from the load, positioning Vs well above trip level, VSOC+. Once the voltage in Vs exceeds the preset threshold, the OC pin pulls down to COM to detect an over-current condition. Direction in MOSFET Current and Load Current Bi-Directional Current Sensing IRS20124 has an over-current detection function utilizing RDS(ON) of the low side switch as a current sensing shunt resistor. Due to the proprietary HVIC process, the IRS20124 is able to sense negative as well as positive current flow, enabling bi-directional load current sensing without the need for any additional external passive components. Since the switching waveform usually contains over/under shoot and associated oscillatory artifacts on their transient edges, a 200 ns blanking interval is inserted in the Vs voltage sensing block at the instant the low side switch is engaged. Because of this blanking interval, the OC function will be unable to detect over current conditions if the low side ON duration less than 200 ns. LO Vs + OC SET1 - OR OCSET2 AND OC + - vs ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ Vsoc+ Simplified Functional Block Diagram of Bi-Directional Current Sensing COM Vsoc- (a ) Normal Operation Condition (b ) Over- Current in Positive Load Current (c ) Over- Current in Negative Load Current Vs Waveform in Over-Current Condition www.irf.com The bi-directional current sensing block has an internal V level shifter feeding the signal to the comparator. OCSET1 sets the threshold, and is given a trip level at VSOC+, which is OCSET1 -V. In the same way, for a given OCSET2, VSOC- is set at OCSET2 -V. 22 IRS20124S(PbF) >0.5mA Vcc in the negative load current direction, the sensing voltage at the Vs node is limited by the body diode of the low side MOSFET as explained later. OCSET1 Design Example OCSET2 This example demonstrates how to use the external resistor network to set ITRIP+ and ITRIP- to be ±11 A, using a MOSFET that has RDS(ON) =60 µΩ. R3 R4 R5 COM External Resistor Network to Set OC Threshold How to set OC Threshold The positive and negative trip thresholds for bidirectional current sensing are set by the voltages at OCSET1 and OCSET2. The trip threshold voltages, VSOC+ and VSOC+, are determined by the required trip current levels, ITRIP+ ITRIP-, and RDS(ON) in the low side MOSFET. Since the sensed voltage of Vs is shifted up by 2.21 V internally and compared with the voltages fed to the OCSET1 and OCSET2 pins, the required value of OCSET1 with respect to COM is VOCSET1 = VSOC+ + 2.21 V = I x RDS(ON) + 2.21 V The same relation holds between OCSET2 and VSOC-, VOCSET2 = VSOC- + 2.21 V = I x RDS(ON) + 2.21 V In general, RDS(ON) has a positive temperature coefficient that needs to be considered when the threshold level is being set. Please also note that, www.irf.com VISET1 = VTH+ + 2.21 V = ITRIP+ x RDS(ON) + 2.21 V = 11 x 60 µΩ +2.21 V = 2.87 V VISET2 = VTH- + 2.21 V = ITRIP- x RDS(ON) + 2.21 V = (−11) V 60 µΩ +2.21 V = 1.55 V The total resistance of resistor network is based on the voltage at the Vcc and required bias current in this resistor network. Rtotal =R3 + R4 + R5 = Vcc / Ibias = 12 V / 1 µΑ = 12 k Ω The expected voltage across R3 is Vcc- VISET1 = 12 V - 2.87 V=9.13 V. Similarly, the voltages across R4 is VSOC+ - VSOC- = 2.87 V - 1.55 V =1.32 V, and the voltage across R5 is VISET2= 1.55 V respectively. R3 =9.13 V/ Ibias = 9.13 kΩ R4 =1.32 V/ Ibias = 1.32 kΩ R5 =1.55 V/ Ibias = 1.55 kΩ Choose R3= 9.09 kΩ R4=1.33 kΩ, R5=1.54 kΩ from E-96 series. Consequently, actual threshold levels are VSOC+ =2.88 V gives ITRIP+ = 11.2 A VSOC- =1.55 V gives ITRIP- = -11.0 A Resisters with 1% tolerances are recommended. 23 IRS20124S(PbF) OC Output Signal The OC pin is a 20 V open drain output. The OC pin is pulled down to ground when an over current condition is detected. A single external pull-up resistor can be shared by multiple IRS20124 OC pins to form the ORing logic. In order for a microprocessor to read the OC signal, this information is buffered with a mono stable multi vibrator to ensure 100 ns minimum pulse width. Because of unpredictable logic status of the OC pin, the OC signal should be ignored during power up/down. VS - COM 0 } ID Limitation from Body Diode in MOSFET When a Class D stage outputs a positive current, flowing from the Class D amp to the load, the body diode of the MOSFET will turn on when the drain to source voltage of the MOSFET become larger than the diode forward drop voltage. In such a case, the sensing voltage at the Vs pin of the IRS20124 is clamped by the body diode. This means that the effective RDS(ON) is now much lower than expected from RDS(ON) of the MOSFET, and the Vs node my not able to reach the threshold to turn the OC output on before the MOSFET fails. Therefore, the region where body diode clamping takes a place should be avoided when setting VSOC. www.irf.com Body Diode Clamp OCSET2 should be set in this region Body Diode in MOSFET Clamps vs Voltage For further application information for gate driver IC please refer to AN-978 and DT98-2a. For further application information for class D application, please refer to AN-1070 and AN-1071. 24 IRS20124S(PbF) Case Outline 14 Lead SOIC (narrow body) www.irf.com 01-6019 01-3063 00 (MS-012AB) 25 IRS20124S(PbF) LOAD ED TA PE FEED DIRECTION Tape & Reel 14-Lead SOIC A B H D F C N OT E : CO NTROLLING D IMENSION IN MM E G C A R R I E R T A P E D IM E N S I O N F O R 1 4 S O IC N M etr ic Im p erial Co d e M in M ax M in M ax A 7 .9 0 8.1 0 0. 31 1 0 .3 18 B 3 .9 0 4.1 0 0. 15 3 0 .1 61 C 15 .7 0 1 6. 30 0. 61 8 0 .6 41 D 7 .4 0 7.6 0 0. 29 1 0 .2 99 E 6 .4 0 6.6 0 0. 25 2 0 .2 60 F 9 .4 0 9.6 0 0. 37 0 0 .3 78 G 1 .5 0 n/ a 0. 05 9 n/ a H 1 .5 0 1.6 0 0. 05 9 0 .0 62 F D C B A E G H R E E L D IM E N S I O N S F O R 1 4 SO IC N M etr ic Im p erial Co d e M in M ax M in M ax A 32 9. 60 3 30 .2 5 1 2 .9 76 13 .0 0 1 B 20 .9 5 2 1. 45 0. 82 4 0 .8 44 C 12 .8 0 1 3. 20 0. 50 3 0 .5 19 D 1 .9 5 2.4 5 0. 76 7 0 .0 96 E 98 .0 0 1 02 .0 0 3. 85 8 4 .0 15 F n /a 2 2. 40 n /a 0 .8 81 G 18 .5 0 2 1. 10 0. 72 8 0 .8 30 H 16 .4 0 1 8. 40 0. 64 5 0 .7 24 www.irf.com 26 IRS20124S(PbF) LEADFREE PART MARKING INFORMATION Part number Date code IRSxxxxx YWW? ?XXXX Pin 1 Identifier ? P IR logo MARKING CODE Lead Free Released Non-Lead Free Released Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 200-002 ORDER INFORMATION 14-Lead SOIC IRS20124SPbF 14-Lead SOIC Tape & Reel IRS20124STRPbF SO-14 package is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at IR's Web Site http://www.irf.com WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel:(310) 252-7105 Data and specifications subject to change without notice. www.irf.com 12/4/2006 27