APW7159A Dual Channel Synchronous Buck PWM Controller for SMPS Features General Description • • The APW7159A is a dual channel voltage mode and syn- Single 12V Power Supply Required Excellent Output Voltage Regulation chronous PWM controller which drives dual N-channel MOSFETs. The two channels are operated with 180 de- - 1.0V±0.8% Internal Reference Over Line and Temperature • gree phase shift. The device integrates all of the control, monitoring, and Simple Single Loop Control Design - Voltage Mode PWM Control • • protecting functions into a single package; provides two controlled power output with over-voltage, over- 0~100% Duty Ratio Programmable Frequency Range from 50kHz to temperature, and over-current protections. The APW7159A provides excellent regulation for output 400kHz (Constant 50kHz when Floating) Integrated Soft-Start and Soft-Off (Patent Pending) • • • • • load variation. The internal 1.0V temperature-compensated reference voltage provides high accuracy of 0.8% Support Pre-Biased Power-On Both Channel with 180o Phase Shift over line and temperature. The device includes a 50kHz free-running triangle-wave oscillator that is adjustable Integrated Boot-Strap Diode Over-Current Protection from 50kHz to 400kHz. The APW7159A has been equipped with excellent pro- - Sense High Side MOSFET’s RDS(ON) 120% Over-Voltage Protection • • • • • tection functions: POR, OCP, UVP, and OVP protections. The Power-On-Reset (POR) circuit can monitor the VCC 50% Under-Voltage Protection Over-Temperature Protection and OCSET voltage to make sure the supply voltage exceeds their threshold voltage while the controller is Available in SOP-20 Package Lead Free and Green Devices Available running. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the high (RoHS Compliant) side MOSFET’s RDS(ON). When the output current reaches the trip point, the controller will be latched. Under-Voltage Applications Protection (UVP) and Over-Voltage Protection (OVP) monitor the FB voltage to protect APW7159A from burnout when • output voltage is under 50% or over 120% of normal output voltage. The APW7159A is available in SOP-20 SMPS package. Simplified Application Circuit VIN Phase Shift VOUT1 PWM Controller 1 PWM Controller 2 VOUT2 APW7159A S ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 1 www.anpec.com.tw APW7159A Ordering and Marking Information Package Code K : SOP-20 Operating Ambient Temperature Range I : -40 to 85oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7159A Assembly Material Handling Code Temperature Range Package Code APW7159A APW7159A XXXXX K: XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration FB1 1 20 RT COMP1 2 19 SS OCSET1 3 18 FB2 GND 4 17 COMP2 VCC 5 16 OCSET2 15 BOOT2 BOOT1 6 UGATE1 PHASE1 7 8 LGATE1 9 14 UGATE2 13 PHASE2 12 LGATE2 11 NC PGND 10 SOP-20 (Top View) Absolute Maximum Ratings Symbol VVCC VBOOT1/2 (Note 1) Parameter Rating Unit Input Bias Supply Voltage (VCC to GND) -0.3 ~ 16 V BOOT1/ BOOT2 to PHASE1/PHASE2 Voltage -0.3 ~ 16 V <400ns pulse width -5 ~ VBOOT1/2+5 V >400ns pulse width -0.3 ~ VBOOT1/2+0.3 V <400ns pulse width -5 ~ VVCC+0.3 V >400ns pulse width -0.3 ~ VVCC+0.3 V <400ns pulse width -10 ~ 30 V >400ns pulse width -0.3 ~ 16 V -0.3 ~ 7 V -0.3 ~ VVCC+0.3 V UGATE1/UGATE2 to PHASE1/PHASE2 LGATE1/LGATE2 to PGND Voltage PHASE1/PHASE2 to PGND Voltage RT, SS, COMP1, COMP2, FB1, FB2 to GND Voltage OCSET1, OCSET2 to GND Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 2 www.anpec.com.tw APW7159A Absolute Maximum Ratings (Cont.) Symbol (Note 1) Parameter PGND to GND Voltage PD Power Dissipation TSDR Unit -0.3 ~ 0.3 V Internally Limited Maximum Junction Temperature TSTG Rating Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds W 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Thermal Resistance in Free Air (Note 2) SOP-20 Typical Value Unit 100 °C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions (Note 3) Symbol VVCC VIN1/VIN2 Parameter Input Bias Supply Voltage (VCC to GND) Converter Input Voltage VOUT1/VOUT2 Converter Output Voltage IOUT1/IOUT2 Converter Output Current Range Unit 10 ~ 13.2 V 2 ~ 13.2 V 1 ~ VIN1/VIN2 V 0 ~ 30 A TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o C C Note 3 : Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VIN=12V, VOUT= 3.3V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APW7159A Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVCC VCC Supply Current (Shutdown Mode) VVCC<5V, SS=GND - 0.5 1 mA VCC Supply Current (Shutdown Mode) 5V< VVCC <9V, SS=GND - 0.8 1.6 mA VCC Supply Current UGATE1/UGATE2 and LGATE1/LGATE2 open - 5 10 mA 9 9.5 10 V Falling VCC Threshold 1 7.5 8 8.5 V Falling VCC Threshold 2 - 4.6 - V Rising VOCSET1/VOCSET2 Threshold - 1.6 - V Falling VOCSET1/VOCSET2 Threshold - 1.0 - V POWER-ON-RESET (POR) AND LOCKOUT VOLTAGE THRESHOLDS Rising VCC Threshold Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 3 www.anpec.com.tw APW7159A Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VIN=12V, VOUT= 3.3V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APW7159A Test Conditions Unit Min. Typ. Max. OSCILLATOR FOSC VOSC Free Running Frequency RT = NC, VVCC =12V 45 50 55 kHz Programmable Frequency Range Connect Resistor from RT to GND 45 - 400 kHz Total Frequency Accuracy Over-Temperature -10 - 10 % Ramp Amplitude (Note 4) - 1.9 - V Duty Cycle 0 - 100 % - 1.0 - V -0.8 - +0.8 % - 0.01 - %/A RL=10kΩ, CL=10pF (Note 4) - 88 - dB (Note 4) - 15 - MHz Slew Rate (Note 4) RL=10kΩ, CL=10pF (Note 4) - 6 - V/µs FB1/FB2 Input Current VFB1/VFB2=1.0V - - 0.1 µA COMP1/COMP2 Source Current VCOMP=2V - 5 - mA COMP1/COMP2 Sink Current VCOMP=2V - 5 - mA REFERENCE VOLTAGE VREF Reference Voltage Reference Voltage Tolerance Load Regulation VVCC=10V~13.2V (Note 4) IOUT1= IOUT2=0A~10A PWM ERROR AMPLIFIERS Open Loop Gain (Note 4) Unity-Gain Bandwidth (Note 4) RL=10kΩ, CL=10pF BOOT-STRAP DIODE AND SOFT-START VF Diode Forward Voltage ISS Soft-Start Charge Current IF=10mA - 0.8 - V 24 30 36 µA GATE DRIVERS IUGATE1/ IUGATE2 ILGATE1/ ILGATE2 High Side Gate Source Current VBOOT1=VBOOT2=12V, VUGATE1-VPHASE1=2V/VUGATE2 – VPHASE2=2V - 1.7 - A High Side Gate Sink Current VBOOT1=VBOOT2=12V, VUGATE1-VPHASE1= 10V/VUGATE2 – VPHASE2=10V - 1.1 - A Low Side Gate Source Current VVCC=12V, VLGATE1=VLGATE2=2V - 1.9 - A VVCC=12V,VLGATE1= VLGATE2=10V - 1.6 - A - 40 - ns - 40 - ns 180 200 220 µA Low Side Gate Sink Current Dead Time 1 UGATE1/UGATE2 Falling to LGATE1/LGATE2 Rising LGATE1/LGATE2 Falling to UGATE1/UGATE2 Rising (Note 4) Dead Time 2 (Note 4) PROTECTION IOCSET1/ IOCSET2 OCSET1/OCSET2 Current Source Over Voltage Protection Measure on FB1/FB2 115 120 125 %VREF Under Voltage Protection Measure on FB1/FB2 45 50 55 %VREF - 150 - o - o Over-Temperature Shutdown Over-Temperature Hysteresis (Note 4) (Note 4) - 40 C C Note 4: Guarantee by design, not production test Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 4 www.anpec.com.tw APW7159A Typical Operating Characteristics Reference Voltage vs. Junction Temperature Switching Frequency vs. Junction Temperature 1003 55 54 Switching Frequency (kHz) Reference Voltage (mV) 1002 1001 1000 999 998 997 996 -40 -20 0 20 40 60 52 51 50 49 48 47 46 45 -40 -20 80 100 120 Junction Temperature Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 53 0 20 40 60 80 100 120 Junction Temperature 5 www.anpec.com.tw APW7159A Operating Waveforms Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Power On Power Off VIN1= VIN2=VVCC , IOUT=0mA VIN1= VIN2=Vvcc 1 1 VOUT1 VOUT2 VOUT1 2 2 VOUT2 3 3 CH1: VIN1=VIN2=VVCC, 5V/Div CH2: VOUT1, 2V/Div CH3: VOUT2, 2V/Div Time: 2ms/Div CH1: VIN1=VIN2=VVCC, 5V/Div CH2: VOUT1, 2V/Div CH3: VOUT2, 2V/Div Time: 5ms/Div Enable Shutdown R LOAD1=R LOAD2 =10Ω VSS 1 1 V SS VOUT1 VOUT1 2 2 VOUT2 VOUT2 3 3 CH1: VSS, 5V/Div CH2: VOUT1, 2V/Div CH3: VOUT2, 2V/Div Time: 2ms/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 CH1: VSS, 5V/Div CH2: VOUT1, 2V/Div CH3: VOUT2, 2V/Div Time: 10ms/Div 6 www.anpec.com.tw APW7159A Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Short-Circuit Protection Over-Current Protection ROCSET=1kΩ, RDS (high-side)=10mΩ VIN=Vvcc VIN=V VCC 1 1 VOUT VOUT 2 2 3 3 VPHASE VPHASE IL 4 4 IL CH1: VIN=VVCC, 10V/Div CH2: VOUT, 2V/Div CH3: VPHASE, 10V/Div CH4: IL, 10A/Div Time: 50µA/Div CH1: VIN=VVCC, 10V/Div CH2: VOUT, 2V/Div CH3: VPHASE, 10V/Div CH4: IL, 10A/Div Time: 10ms/Div UGATE Falling IOUT =10A UGATE Rising IOUT =10A VLGATE VLGATE VUGATE VUGATE 1,2 1,2 VPHASE VPHASE 3 3 CH1: VUGATE, 10V/Div CH2: VLGATE, 5V/Div CH3: VPHASE, 10V/Div Time: 20ns/Div Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 CH1: VUGATE, 10V/Div CH2: VLGATE, 5V/Div CH3: VPHASE, 10V/Div Time: 20ns/Div 7 www.anpec.com.tw APW7159A Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. Load Transient Response Load Transient Response VIN2=VVCC =12V, VOUT2=3.3V VIN1=VVCC =12V, VOUT1=5V IOUT2 slew rate=10A/µs IOUT1 slew rate=10A/µs VOUT1 VOUT2 1 1 I OUT1 IOUT2 2 2 CH1: VOUT2, 200mV/Div CH1: VOUT1, 200mV/Div CH2: IOUT2, 5A/Div Time: 100µs/Div CH2: IOUT1, 5A/Div Time: 100µs/Div Pin Description PIN FUNCTION NO. NAME 1 FB1 Feedback Input of Channel 1. The Buck converter senses feedback voltage via FB1 and regulates the FB1 voltage at 1.0V. Connecting FB1 with a resistor-divider from the output sets the output voltage of the Buck converter. 2 COMP1 Error Amplifier Output of Channel 1. It is used to compensate the regulation control loop. Refer to the section “Application Information” for details. 3 OCSET1 This pin is used to set the maximum inductor current of channel 1. Refer to the section in “Function Description” for detail. 4 GND Signal Ground. 5 VCC Power Supply Input. Connect a nominal 10V to 13.2V power supply voltage to this pin. A power-on-reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1 to 10µF) should be connected to the GND for noise decoupling. 6 BOOT1 This pin provides the bootstrap voltage to the high-side gate driver for driving the N-channel MOSFET. An external capacitor from PHASE1 to BOOT1, an internal diode, and the power supply voltage VCC, generate the bootstrap voltage for the high-side gate driver (UGATE1). 7 UGATE1 High-Side Gate Driver Output of Channel 1. This pin is the gate driver for high-side MOSFET. 8 PHASE1 This pin is the return path for the high-side gate driver 1. Connect this pin to the high-side MOSFET source and connect a capacitor to BOOT1 for the bootstrap voltage. This pin is also used to monitor the voltage drop across the MOSFET for over-current protection. Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 8 www.anpec.com.tw APW7159A Pin Description (Cont.) PIN FUNCTION NO. NAME 9 LGATE1 10 PGND Low-side Gate Driver Output of channel 1. This pin is connected to low-side MOSFET. Power Ground of the Low-Side Gate Drivers. Use a separate track to connect this pin to Source of the low-side MOSFET. The Source of the low-side MOSFET must be connected to system ground with very low impedance. Connecting this pin to the GND. 11 NC 12 LGATE2 Low-side Gate Driver Output of channel 2. This pin is the gate driver for low-side MOSFET. 13 PHASE2 This pin is the return path for the high-side gate driver of channel 2. Connect this pin to the high-side MOSFET source and connect a capacitor to BOOT2 for the bootstrap voltage. This pin is also used to monitor the voltage drop across the MOSFET for over-current protection. 14 UGATE2 High-side Gate Driver Output of Channel 2. This pin is connected to high-side MOSFET. 15 BOOT2 This pin provides the bootstrap voltage to the high-side gate driver for driving the N-channel MOSFET. An external capacitor from PHASE2 to BOOT2, an internal diode, and the power supply voltage VCC, generate the bootstrap voltage for the high-side gate driver (UGATE2). 16 OCSET2 This pin is used to set the maximum inductor current of channel 2. Refer to the section in “Function Description” for detail. 17 COMP2 Error Amplifier Output of Channel 2. It is used to compensate the regulation control loop. Refer to the section “Application Information” for details. 18 FB2 Feedback Input of Channel 2. The converter senses feedback voltage via FB2 and regulates the FB2 voltage at 1.0V. Connecting FB2 with a resistor-divider from the output sets the output voltage of the Buck converter. 19 SS Connect a capacitor to the GND and a 30µA current source charges this capacitor to set the soft-start time. The pin also integrates EN/Shutdown function. Pulling SS below 0.7V shuts down the IC. 20 RT This pin allows adjusting the switching frequency. Connect a resistor from RT to the ground to increase the switching frequency. - No Connection. Exposed Pad Connect the pad to the system ground plane on PCBs. The PCB will be a heat sink of the IC. Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 9 www.anpec.com.tw APW7159A Block Diagram VCC Regulator Power-OnReset I SS (30µA typ.) V REF SS (1.0V typ.) OCSET2 OCSET1 I OCSET2 I OCSET1 BOOT2 BOOT1 UGATE2 Over-Current Comparator 2 15k PHASE2 Soft-Start and Fault Logic UGATE1 Over-Current Comparator 1 15k PHASE1 VCC VCC Gate Control LGATE2 Gate Control LGATE1 15k 15k Over-Voltage Comparator 2 PGND2 Over-Voltage Comparator 1 1.2 Under-Voltage Comparator 1 Under-Voltage Comparator 2 PGND1 1.2 0.5 0.5 FB2 FB1 VREF Error Amplifier 2 PWM Comparator 2 PWM Comparator 1 Error Amplifier 1 V REF COMP2 COMP1 Oscillator RT Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 10 GND www.anpec.com.tw APW7159A Typical Application Circuit 2k 2k 10µF 1µF 1µF 1nF (option) 100nF VOUT1 5V/30A L1 7.2µH 2200µFx2 ESR=30mΩ 4R7 BOOT1 BOOT2 UGATE1 UGATE2 PHASE1 PHASE2 (option) LGATE1 LGATE2 PGND VVCC VOUT2 3.3V/30A 2200µFx2 ESR=30mΩ 4R7 1.5nF COMP2 33nF APW7159 6.8nF L2 7.2µH (option) 33nF 12k 1k APM3106 PGND COMP1 12k 470µF APM3109 APM3106 10µF 1nF (option) 100nF APM3109 1.5nF 15nF VIN OCSET2 OCSET1 6.8nF 12k 12k FB1 FB2 VCC RT GND SS 15nF 1k 5R1 3k 5.2k 1µF 47nF Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 11 RT www.anpec.com.tw APW7159A Function Description VCC Power-On-Reset (POR) VSS Voltage The Power-On-Reset (POR) function of APW7159A continually monitors the voltage on VCC and OCSET1/ OCSET2 pin. When the voltage on VCC and OCSET1/ OCSET2 exceeds their rising POR threshold voltage respectively (9.5V and 1.6V typical), the POR function ini- 1.4 tiates soft-start operation. Where the voltage at OCSET1/ OCSET2 pin is equal to VIN1/VIN2 minus a fixed voltage 1 VFB 1 drop (VOCSET1/VOCSET2 = VIN1/VIN2 – V ROCSET1/VROCSET2). For operation with a single +12V power source, VIN1/VIN2 and VFB2 VCC are equivalent and the +12V power source must exceed the rising VCC threshold. With all input supplies t0 t1 t2 t3 t4 Time Figure 1. Soft-start timing sequence above their POR thresholds, the device initiates a softstart interval. Soft-Off (5V<VCC<9V) (Note 5) Soft-Start The APW7159A also integrates a soft-off circuitry. When the voltage on VCC falls below the falling threshold1 (8V The SS pin controls the soft-start and enables/disables the controller. Connect a soft-start capacitor from SS pin typical), an internal current source, I SS (30µA typical), starts to discharge from SS. When the VVCC falls below the fall- to GND to set the soft-start interval. Figure1 shows the soft-start interval. When VCC reaches its Power-On-Re- ing threshold2 (4.6V typical), the device is shutdown. The APW7159A will initiate a soft-start process until re-cycle set threshold (9.5V typical), a soft-start current source, ISS (30µA typical), starts to charge the capacitor. When the power supply (9.5V typical). VSS reaches the threshold about 1V, the internal 1.0V reference starts to rise and follows the VSS; the error ampli- Over-Temperature Protection (OTP) Note 5: The mentioned soft-off function is patent pending by ANPEC The over-temperature circuit limits the junction temperature of the APW7159A. When the junction temperature fier output (V COMP) suddenly rises to 1.1V, which is the valley of the triangle wave of the oscillator, leads the VOUT1/ exceeds 150oC, a thermal sensor pulls UGTAE1/UGATE2 and LGATE1/LGATE2 low, allowing the devices to cool. VOUT2 to start up. VOUT1 and VOUT2 have power on sequence issue, VOUT2 will start up after VSS rise up to 1.4V. The soft- The thermal sensor allows the converters to start a softstart process and to regulate the output voltage again start time can be calculated as below: TSOFT −START = t 3 − t1 = t 4 − t 2 = CSS ⋅ 1V ISS after the junction temperature cools by 40oC. The OTP is designed with a 40oC hysteresis to lower the average Where CSS = external capacitor connected at SS pin Junction Temperature (TJ ) during continuous thermal overload conditions, increasing the lifetime of the device. ISS = soft-start current, typical ISS current is 30µA The APW7159A does not have EN pin, pull SS low (SS Over-Current Protection <0.7V) shut down the IC. The over-current function protects the switching converter against over-current or short-circuit conditions. The controller senses the inductor current by detecting the drainto-source voltage, which the product of the inductor’s current and high side MOSFET on-resistance during it’s onstate. This method enhances the converter’s efficiency and reduces cost by eliminating a current sensing resistor required. Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 12 www.anpec.com.tw APW7159A Function Description (Cont.) Over-Current Protection (Cont.) Over-Voltage Protection A resistor (ROCSET1/ROCSET2) connected between OCSET1/ The over-voltage protection monitors the FB voltage to prevent the output from over-voltage. When the output OCSET2 pin and the drain of the upper MOSFET will determine the over-current limit. An internal current source voltage rises to 120% of the nominal output voltage, the APW7159A turns off all devices. The APW7159A will ini- will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the up- tiate a soft-start process until re-cycle power supply. per MOSFET. When the voltage across the upper MOSFET exceeds the voltage drop across the ROCSET1/ROCSET2, the Adaptive Shoot-Through Protection The gate driver incorporates adaptive shoot-through protection to high-side and low-side MOSFETs from con- IC shuts off the entire gate drives. After a soft-start period delay, the APW7159A initiates a new soft-start process. ducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has After 3 times over-current events are counted continuously, all devices and gate drivers (UGATE1/UGATE2/LGATE1/ turned off one MOSFET before the other is allowed to rise. LGATE2) were shutdown. Both outputs of the PWM converter are latched to be floating. The threshold of the over- During turn-off of the low-side MOSFET, the LGATE1/ LGATE2 voltage is monitored until it reaches a 1.6V current limit is therefore given by : ILIMIT = IOCSET ⋅ ROCSET RDS( ON) (high − side ) threshold, at which time the UGATE is released to rise after a constant delay. During turn-off of the high-side For the over-current is never occurred in the normal operating load range; the variation of all parameters in the MOSFET, the UGATE1/UGATE2 to PHASE1/PHASE2 voltage is also monitored until it reaches a 1.6V threshold, at above equation should be determined. - The MOSFET’s RDS(ON) is varied by temperature and which time the LGATE1/LGATE2 is released to rise after gate to source voltage, the user should determine the maximum RDS(ON) in manufacturer’s datasheet. Pre-Bias Power-On -The minimum IOCSET1/IOCSET2 (typical 200µA) and minimum R OCSET1 /R OCSET2 should be used in the above voltage will smoothly rising without discharged even the voltage is not zero. a constant delay. When the APW7159A initiates the soft-start, the output equation. -Note that the ILIMIT is the current flow through the upper MOSFET; ILIMIT must be greater than maximum output Switching Frequency The APW7159A provides the oscillator switching frequency adjustment. The device includes a 50kHz free- current add the half of inductor ripple current. The over-current protection will shut down the device and running triangle wave oscillator. If operates in higher frequency than 50kHz, connect a resistor from RT pin to the discharge the CSS with a 30µA sink current. If the ROCSET1/ ROCSET2 is not connected or VOCSET1/VOCSET2 is below 1.6V, ground to increase the switching frequency. Equation 1 and figure 2 shows the relationship between oscillation the APW7159A will not initiate soft-start process and force device shutdown. frequency and RT resistance. FOSC (kHz ) = 50 + Under-Voltage Protection The under-voltage function monitors the voltage on FB by Under-Voltage comparator to protect the PWM converter 7550 R T (kΩ ) against short-circuit conditions. When the VFB falls below the falling UVP threshold (50% VREF), a fault signal is internally generated and the device turns off high-side and low-side MOSFETs. The converter is shutdown and the output is latched to be floating. Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 13 www.anpec.com.tw APW7159A Function Description (Cont.) Switching Frequency (Cont.) Oscillator Frequency vs. RT Resistance Oscillator Frequency (kHz) 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 RT Resistance (k) Figure 2. Oscillator Frequency vs. RT Resistance Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 14 www.anpec.com.tw APW7159A Application Information Output Voltage Selection Output Capacitor Selection The output voltage can be programmed with a resistive divider. Use 1% or better resistors for the resistive divider Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 1V. The out- performance low ESR capacitors is intended for switching regulator applications. In some applications, mul- put voltage is determined by: tiple capacitors have to be parallelled to achieve the desired ESR value. A small decoupling capacitor in R VOUT = 1× 1 + OUT R GND parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, Where ROUT is the resistor connected from VOUT to FB and RGND is the resistor connected from FB to the GND. consult the capacitors manufacturer. Output Inductor Selection Input Capacitor Selection The input capacitor is chosen based on the voltage rating The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor’s ripple current and induces and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher lower output ripple voltage. The ripple current and ripple voltage can be approximated by: IRIPPLE = than the maximum input voltage. The RMS current of the bulk input capacitor is calculated as the following equation: VIN − VOUT VOUT × FS × L VIN IRMS = IOUT ⋅ D ⋅ (1 − D ) ∆VOUT = IRIPPLE × ESR During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are where Fs is the switching frequency of the regulator. used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors Although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will manufacturer. For high frequency decoupling, a ceramic capacitor 1µF can be connected between the drain of exist between the inductor’s ripple current and the regulator load transient response time. upper MOSFET and the source of lower MOSFET. A smaller inductor will give the regulator a faster load MOSFET Selection transient response at the expense of higher ripple current. Increasing the switching frequency (FS) also reduces the The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the fol- choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value lowing equations: 2 PUPPER = IOUT ( 1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FS has been chosen, select an inductor is capable of carrying the required peak current without going into 2 PLOWER = IOUT (1+ TC)(RDS(ON))(1-D) saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase Where IOUT is the load current TC is the temperature dependency of RDS(ON) abruptly when it saturates. This will result in a larger output ripple voltage. FS is the switching frequency tSW is the switching interval D is the duty cycle Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 15 www.anpec.com.tw APW7159A Application Information (Cont.) MOSFET Selection (Cont.) Note that both MOSFETs have conduction loss while the upper MOSFET includes an additional transition loss. The PWM modulator is shown in Figure 5. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by: VIN GAINPWM = ∆VOSC V IN The switching internal, tSW , is the function of the reverse transfer capacitance C RSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. OSC PWM Compensation ΔV OSC The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain Figure 5. The PWM Modulator The compensation network is shown in Figure 6. It provides a close loop transfer function with the highest tor and output capacitors. The transfer function of the LC filter is given by: 1 FESR = 2 × π × ESR × COUT zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: 1 1 // R2 + VCOMP sC1 sC2 GAINAMP = = 1 VOUT R1// R3 + sC3 The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor. V OUT 1 1 s + × s + R2 C2 R1 R3 C3 ( + ) × × R1 + R3 = × C1 + C2 1 R1× R3 × C1 s s + × s + R2 × C1× C2 R3 × C3 C OUT ESR The poles and zeros of the transfer function are: 1 FZ1 = 2 × π × R2 × C2 1 FZ2 = 2 × π × (R1 + R3) × C3 1 FP1 = C1× C2 2 × π × R2 × C1 + C2 Figure 3. The Output LC Filter FLC -40dB/dec GAIN (dB) PHASE Driver should be added. The compensation network is shown in Figure 6. The output LC filter consists of the output induc- L PWM Comparator Output of Error Amplifier slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB, and V OUT V PHASE Driver FP2 = FESR 1 2 × π × R3 × C3 C1 -20dB/dec R3 C3 R2 C2 V OUT R1 Frequency(Hz) V COMP V REF Figure 4. The LC Filter GAIN and Frequency Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 FB Figure 6. Compensation Network 16 www.anpec.com.tw APW7159A Application Information (Cont.) PWM Compensation (Cont.) The closed loop gain of the converter can be written as: The poles and zero of this transfer functions are: FLC = GAINLC X GAINPWM X GAINAMP Figure 7. shows the asymptotic plot of the closed loop R3 = R1 FS −1 2 × FLC C3 = 1 π × R3 × FS converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similars to the curve plotted. A stable closed loop has a -20dB/ decade 1 2 × π × L × COUT slope and a phase margin greater than 45 degree. 1. Choose a value for R1, usually between 1K and 5K. FZ1 FZ2 2. Select the desired zero crossover frequency FP1 FP2 GAIN (dB) FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: ∆VOSC FO R2 = × × R1 VIN FLC Compensation Gain 20log (R2/R1) 20log (VIN/ΔVOSC) 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. FLC FZ1 = 0.75 X FLC FESR Calculate the C2 by the equation: 1 C2 = 2 × π × R2 × FLC × 0.75 PWM & Filter Gain Converter Gain Frequency(Hz) Figure 7. Converter Gain and Frequency 4. Set the pole at the ESR zero frequency FESR: FP1 = FESR Layout Consideration Calculate the C1 by the equation: C2 C1 = 2 × π × R2 × C2 × FESR − 1 In any high switching frequency converter, a correct layout is important to ensure proper operation of the 5. Set the second pole FP2 at the half of the switching regulator. With power devices switching at 200kHz, the resulting current transient will cause voltage spike across frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops amplifier. flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of FP2 = 0.5 X FS the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed FZ2 = FLC Combine the two equations will get the following component circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And signal calculations: GAINLC = 1 + s × ESR × COUT s × L × COUT + s × ESR × COUT + 1 and power grounds are to be kept separating till combined using the ground plane construction or single point 2 grounding. Figure 8. illustrates the layout, with bold lines Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 17 www.anpec.com.tw APW7159A Application Information (Cont.) Layout Consideration (Cont.) Close to IC APW7159A indicating high current paths; these traces must be short and wide. Components along the bold lines should be VIN GND placed lose together. Below is a checklist for your layout: - Keep the switching nodes (UGATE, LGATE, and PHASE) VCC OCSET away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces BOOT to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UGATE UGATE ROCSET L O A D PHASE and LGATE) should be short and wide. - Place the source of the high-side MOSFET and the drain LGATE of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the VOUT Figure 8. Layout Consideration resistor dividers, and boot capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the lower MOSFET GND. - The drain of the MOSFETs (VIN and PHASE nodes) should be a large plane for heat sinking. - The ROCSET resistance should be placed near the IC as close as possible. - The decoupling capacitor for VCC should be placed near the VCC and GND. CBOOT should be connected as close to the BOOT and PHASE pins as possible. Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 18 www.anpec.com.tw APW7159A Package Information SOP-20 D h X 45o E E1 SEE VIEW A e c A L 0 GAUGE PLANE SEATING PLANE A1 A2 0.25 b VIEW A S Y M B O L SOP-20 MILLIMETERS INCHES MIN. MAX. A 2.65 A1 0.10 0.30 A2 2.05 b 0.31 0.51 0.012 0.020 c 0.20 0.33 0.008 0.013 D 12.60 13.00 0.496 0.512 0.413 0.299 MIN. 0.104 0.012 0.004 0.081 E 10.10 10.50 0.398 E1 7.40 7.60 0.291 e MAX. 1.27 BSC 0.050 BSC h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 0 0o 8o 0o 8o Note : 1. Follow from JEDEC MS-013 AC. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 19 www.anpec.com.tw APW7159A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-20 A H 330.0±2.00 50 MIN. P0 P1 4.0±0.10 12.0±0.10 T1 C 24.40+2.00 13.0+0.50 -0.00 -0.20 P2 D0 2.0±0.10 1.5+0.10 -0.00 d D W E1 F 1.5 MIN. 20.2 MIN. 24.0±0.30 1.75±0.10 11.5±0.10 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 10.9±0.20 13.3±0.20 3.1±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOP-20 Tape & Reel 1000 Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 20 www.anpec.com.tw APW7159A Taping Direction Information SOP-20 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 21 www.anpec.com.tw APW7159A Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 22 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7159A Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Oct., 2009 23 www.anpec.com.tw