TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 4W, 25W Filter-Free Class-D Stereo Amplifier with AM Avoidance Check for Samples: TPA3131D2, TPA3132D2 FEATURES DESCRIPTION • The TPA3131/32D2 are efficient, stereo digital amplifier power stages for driving speakers with up to 2x42W/4Ω peak power. TPA3131/32D2 operates heatsink-free with cooling to PCB through the bottom side Power-Pad with sustained output power from 2x4W/8Ω (TPA3131D2) to 2x25W/8Ω (TPA3132D2). 1 2 • • • • • • • • • • • • Supports Multiple Output Configurations – 2×4-W into a 8-Ω BTL Load at 7.4 V (TPA3131D2) – 2×25-W into a 8-Ω BTL Load at 19 V (TPA3132D2) Wide Voltage Range: 4.5 V – 26 V Automotive Load-Dump Compliant Efficient Class-D Operation – >90% Power Efficiency Combined with Low Idle Loss for Heat Sink free Operation – Advanced Modulation Schemes Multiple Switching Frequencies – AM Avoidance – Master/Slave Synchronization – Up to 1.2 MHz Switching Frequency Feedback Power Stage Architecture with High PSRR Reduces PSU Requirements Programmable Power Limit Differential/Single-Ended Inputs Stereo and Mono Mode with Single Filter Mono Configuration Single Power Supply Reduces Component Count Integrated Self-Protection Circuits Including Over-Voltage, Under-Voltage, OverTemperature, DC-Detect, and Short Circuit with Error Reporting Thermally Enhanced Package – 32-Pin QFN Pad-Down –40°C to 85°C Ambient Temperature Range APPLICATIONS • • • The TPA3131/32D2 advanced oscillator/PLL circuit employs a multiple switching frequency option to avoid AM interferences; this is achieved together with an option of Master/Slave option, making it possible to synchronize multiple devices. The TPA3131/32D2 are fully protected against faults with short-circuit protection and thermal protection as well as over-voltage, under-voltage and DC protection. Faults are reported back to the processor to prevent devices from being damaged during overload conditions. For feature compatible devices see: Power Pad up device 2x50W TPA3116D2, Power Pad down 2x15W TPA3130D2 and 2x30W TPA3118D2. Simplified Application Circuit Audio Processor And control Right PBTL Detect Left Audio Source 4.5V-26V PSU TPA3131D2 TPA3132D2 Right LC Filter Left LC Filter SDZ MUTE FAULTZ AM/FM Avoidance Control GAIN control and Master/Slave setting Power Limit Capable of synchronizing to other devices AM2,1,0 GAIN / SLV PLIMIT Sync DEVICE POWER QFN 32-PIN TPA3131D2 2 x 4W/8Ω Pad down TPA3132D2 2 x 25W/8Ω Pad down Laptop Computers and Ultrabooks Flatpanel TV Consumer Audio Applications 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM INNR INPR FAULTZ SDZ PVCC PVCC BSPR OUTPR 32 31 30 29 28 27 26 25 QFN PACKAGE 32-PIN (TOP VIEW) PLIMIT 1 24 GND GVDD 2 23 OUTNR GAIN/SLV 3 22 BSNR GND 4 21 GND INNL 5 20 GND INPL 6 19 BSNL MUTE 7 18 OUTNL AM2 8 17 GND 13 14 AVCC PVCC PVCC OUTPL 12 SYNC 16 11 AM0 BSPL 10 15 9 AM1 Power Pad TERMINAL FUNCTIONS PIN NO. TYPE (1) DESCRIPTION 1 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. 2 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1uF X7R ceramic decoupling capacitor. 3 GAIN/SLV I Sets Gain and selects between Master and Slave mode depending on pin voltage divider. 4 GND G Ground 5 INNL I Negative audio input for left channel. Biased at 3V. 6 INPL I Positive audio input for left channel. Biased at 3V. 7 MUTE I Mute signal for fast disable/enable of outputs: HIGH = outputs OFF (high-Z), LOW = outputs ON. TTL logic levels with compliance to AVCC. 8 AM2 I AM Avoidance Frequency Selection 9 AM1 I AM Avoidance Frequency Selection 10 AM0 I AM Avoidance Frequency Selection 11 SYNC DIO 12 AVCC P Analog Supply 13 PVCC P Power supply 14 PVCC P Power supply 15 BSPL BST Boot strap for positive left channel output, connect to 220nF X7R ceramic cap to OUTPL 16 OUTPL PO Positive left channel output 17 GND 18 OUTNL (1) 2 NAME G PO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV pin. Input signal not to exceed GVDD (7V) Ground Negative left channel output TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 TERMINAL FUNCTIONS (continued) PIN NO. NAME TYPE (1) DESCRIPTION 19 BSNL BST 20 GND G Ground 21 GND G Ground 22 BSNR BST Boot strap for negative right channel output, connect to 220nF X7R ceramic cap to OUTNR 23 OUTNR PO Negative right channel output 24 GND 25 OUTPR PO Positive right channel output 26 BSPR BST Boot strap for positive right channel output, connect to 220nF X7R ceramic cap to OUTPR 27 PVCC PI Power supply 28 PVCC PI Power supply 29 SDZ 30 FAULTZ 31 INPR I Positive audio input for right channel. Biased at 3V. 32 INNR I Negative audio input for right channel. Biased at 3V. 33 Thermal Pad or PowerPAD™ G Connect to GND for best system performance. If not connected to GND, leave floating. G I DO Boot strap for negative left channel output, connect to 220nF X7R ceramic cap to OUTNL Ground Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. General fault reporting including Over-current_PVCC, OVP_DVDD FAULT1Z = High, normal operation FAULT1Z = Low, fault condition Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 3 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com SYSTEM BLOCK DIAGRAM GVDD SDZ MUTE PVCC BSPR PVCC TTL Buffer Gain Control PBTL Select OUTPR_FB Gate Drive GAIN OUTPR + OUTPR FB – RINN RINP Gain Control + – + – + PLIMIT – + – GND PWM Logic GVDD – PVCC BSNR PVCC OUTPNR FB OUTNR_ FB + FAULTZ Gate Drive OUTNR SC Detect GND SYNC GAIN/SLV Ramp Generator AM<2:0> Startup Protection Logic Biases and References PLIMIT Reference PLIMIT DC Detect Thermal Detect UVLO/OVLO GVDD AVDD AVCC PVCC LDO Regulator GVDD Gate Drive GVDD OUTNL + OUTNL_FB OUTNL_ FB – – LINP LINN BSNL PVCC Gain Control – + + + – GND PWM Logic PLIMIT GVDD + PVCC BSPL PVCC OUTPL_FB – Input Sense Gate Drive OUTPL PBTL Select PBTL Select OUTPL_FB GND GND Thermal Pad 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC Input voltage, VI Slew rate, maximum VALUE UNIT PVCC, AVCC –0.3 to 30 V INPL, INNL, INPR, INNR –0.3 to 6.3 V PLIMIT, GAIN / SLV, SYNC –0.3 to GVDD+0.3 V AM0, AM1, AM2, MUTE, SDZ –0.3 to PVCC+0.3 V 10 V/msec Operating free-air temperature, TA AM0, AM1, AM2, MUTE, SDZ –40 to 85 °C Operating junction temperature range, TJ –40 to 150 °C Storage temperature range, Tstg –40 to 125 °C ±2 kV ±500 V Electrostatic discharge: Human body model, ESD Electrostatic discharge: Charged device model, ESD THERMAL INFORMATION THERMAL METRIC (1) TPA3131D2 TPA3132D2 UNITS QFN 32 PINS θJA Junction-to-ambient thermal resistance (2) ψJT Junction-to-top characterization parameter (3) ψJB (1) (2) (3) (4) Junction-to-board characterization parameter 31.3 0.2 (4) °C/W 5.5 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM Supply voltage PVCC, AVCC VIH High-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC VIL Low-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC 0.8 V VOL Low-level output voltage FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V IIH High-level input current AM0, AM1, AM2, MUTE, SDZ (VI = 2 V, VCC = 18 V) 50 µA Minimum load RL(PBTL) Impedance Lo Output-filter Inductance 2 Output filter: L = 10 µH, C = 680 nF 3.2 Output filter: L = 10 µH, C = 1 µF 1.6 Minimum output filter inductance under short-circuit condition 26 UNIT VCC RL(BTL) 4.5 MAX V 4 1 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 V Ω µH 5 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS TA = 25°C, AVCC = PVCC = 7.4 V to 26 V, RL = 8 Ω (unless otherwise noted) PARAMETER | VOS | ICC TEST CONDITIONS Class-D output offset voltage (measured differentially) Quiescent supply current MIN TYP MAX VI = 0 V, Gain = 36 dB 1.5 15 SDZ = 2 V, No load or filter, PVCC = 7.4 V (TPA3131D2) 16 SDZ = 2 V, No load or filter, PVCC = 19 V (TPA3132D2) 27 UNIT mV mA ICC(SD) Quiescent supply current in shutdown mode SDZ = 0.8 V, No load or filter <50 µA rDS(on) Drain-source on-state resistance, measured pin to pin PVCC = 7.4V to 19V V, Iout = 500 mA, TJ = 25°C 120 mΩ G G Gain (BTL) Gain (SLV) R1 = open, R2 = 20 kΩ 19 20 21 R1 = 100 kΩ, R2 = 20 kΩ 25 26 27 R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 R1 = 75 kΩ, R2 = 47 kΩ 35 36 37 R1 = 51 kΩ, R2 = 51 kΩ 19 20 21 R1 = 47 kΩ, R2 = 75 kΩ 25 26 27 R1 = 39 kΩ, R2 = 100 kΩ 31 32 33 R1 = 16 kΩ, R2 = 100 kΩ 35 36 37 ton Turn-on time SDZ = 2 V tOFF Turn-off time SDZ = 0.8 V 10 GVDD Gate drive supply IGVDD < 200 µA VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms dB dB dB dB ms 2 µs 6.4 6.9 7.4 V 6.75 7.90 8.75 V TYP MAX UNIT AC ELECTRICAL CHARACTERISTICS TA = 25°C, AVCC = PVCC = 7.4 V to 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER KSVR PO Power supply ripple rejection Continuous output power TEST CONDITIONS MIN 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs ACcoupled to GND RL = 8 Ω, THD+N = 10%, f = 1 kHz, PVCC = 7.4 V (TPA3131D2) 4 RL = 4 Ω, THD+N = 10%, f = 1 kHz, PVCC = 7.4 V (TPA3131D2) 7.3 RL = 8 Ω, THD+N = 10%, f = 1 kHz, PVCC = 19V (TPA3132D2) 25 RL = 4 Ω, THD+N = 10%, f = 1 kHz, PVCC = 19V (TPA3132D2) 42 THD+N Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 0.1W to 2 W (TPA3132D2) RL = 8 Ω, f = 1 kHz, PO = 0.1W to 12.5 W (TPA3131D2) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz SNR 6 Signal-to-noise ratio –70 W 0.1% 70 µV –80 dBV –100 dB Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted (TPA3131D2, PVCC = 7.4V) 98 Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted (TPA3131D2, PVCC = 19V) 105 Submit Documentation Feedback dB dB Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 AC ELECTRICAL CHARACTERISTICS (continued) TA = 25°C, AVCC = PVCC = 7.4 V to 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER fOSC Oscillator frequency TEST CONDITIONS MIN TYP MAX AM2=0, AM1=0, AM0=0 376 400 424 AM2=0, AM1=0, AM0=1 470 500 530 AM2=0, AM1=1, AM0=0 564 600 636 AM2=0, AM1=1, AM0=1 940 1000 1060 AM2=1, AM1=0, AM0=0 1128 1200 1278 UNIT kHz AM2=1, AM1=0, AM0=1 AM2=1, AM1=1, AM0=0 Reserved AM2=1, AM1=1, AM0=1 Thermal trip point Thermal hysteresis Over current trip point 150+ °C 15 °C TPA3131D2 3.4 TPA3132D2 7 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 A 7 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com TYPICAL CHARACTERISTICS fs = 400 kHz, BD Mode (unless otherwise noted) TOTAL HARMONIC DISTORTION +NOISE (BTL) vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY 10 10 Gain = 26 dB PVCC = 7.4 V TA = 25 °C f = 1 kHz 1 THD+N (%) 1 THD+N (%) PO = 0.5 W PO = 1 W PO = 2.5 W Gain =26 dB PVCC = 7.4 V TA = 25 °C RL = 8 Ω 0.1 0.01 0.1 0.01 RL = 4 Ω RL = 8 Ω 0.001 0.01 0.1 1 Output Power per Channel (W) 0.001 10 20 100 1k Frequency (Hz) 10k 20k G003 G001 Figure 1. Figure 2. POWER EFFICIENCY (BTL) vs SUPPLY VOLTAGE TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY 10 100 PO = 1 W PO = 2.5 W PO = 5 W Gain = 26 dB PVCC = 7.4 V TA = 25 °C RL = 4 Ω 90 80 1 60 THD+N (%) Power Efficiency (%) 70 50 40 0.1 30 0.01 20 Gain = 26 dB TA = 25 °C PVCC = 7.4 V 10 0 0 2 4 RL = 4 Ω RL = 8 Ω 6 8 10 Total Output Power (W) 12 14 15 0.001 20 100 1k Frequency (Hz) G004 Figure 3. 8 10k 20k G002 Figure 4. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY 10 10 Gain = 26 dB PVCC = 19 V TA = 25 °C f = 1 kHz 1 THD+N (%) 1 THD+N (%) PO = 1 W PO = 5 W PO =10 W Gain = 26 dB PVCC = 19 V TA = 25 °C RL = 8 Ω 0.1 0.01 0.1 0.01 RL = 4 Ω RL = 8 Ω 0.001 0.01 0.1 1 Output Power per Channel (W) 10 0.001 50 20 100 1k Frequency (Hz) 10k 20k G007 G005 Figure 5. Figure 6. POWER EFFICIENCY (BTL) vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY 10 100 PO = 1 W PO = 10 W PO = 20 W Gain =26dB PVCC = 19 V TA = 25 °C RL = 4 Ω 90 80 1 60 THD+N (%) Power Efficiency (%) 70 50 40 0.1 30 0.01 20 Gain = 26 dB TA = 25 °C PVCC = 19 V 10 0 0 5 RL = 4 Ω RL = 8 Ω 10 15 20 Total Output Power (W) 25 30 0.001 20 100 1k Frequency (Hz) 10k G008 Figure 7. 20k G006 Figure 8. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 9 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) TOTAL HARMONIC DISTORTION + NOISE (TPA3132D2 PBTL) vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE (TPA3132D2 PBTL) vs FREQUENCY 10 10 Gain = 26 dB PVCC = 19 V TA = 25 °C f = 1 kHz 1 THD+N (%) 1 THD+N (%) PO = 1 W PO = 10 W PO = 20 W Gain = 26 dB PVCC = 19 V TA = 25 °C RL = 4 Ω 0.1 0.01 0.1 0.01 RL = 2 Ω RL = 4 Ω 0.001 0.01 0.1 1 Output Power (W) 10 0.001 100 20 100 1k Frequency (Hz) 10k 20k G011 G009 Figure 9. Figure 10. POWER EFFICIENCY (TPA3132D2 PBTL) vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE (TPA3132D2 PBTL) vs FREQUENCY 10 100 PO = 1W PO = 20W PO = 40W Gain = 26dB PVCC = 19V TA = 25°C RL = 2Ω 90 80 1 60 THD+N (%) Power Efficiency (%) 70 50 40 0.1 30 0.01 20 Gain = 26 dB TA = 25 °C PVCC = 19 V 10 0 0 5 10 RL = 2 Ω RL = 4 Ω 15 20 25 30 35 Total Output Power (W) 40 45 50 0.001 20 100 1k Frequency (Hz) G012 Figure 11. 10 10k 20k G010 Figure 12. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) MAXIMUM OUTPUT POWER (BTL) vs PLIMIT VOLTAGE 30 RL = 4 Ω, THD = 10 % RL = 4 Ω, THD = 1 % RL = 8 Ω, THD = 10 % RL = 8 Ω, THD = 1 % RL = 4 Ω, Current Limit TPA3131 RL = 8 Ω, Current Limit TPA3131 80 70 240.0 20 140.0 10 Gain (dB) 60 Output Power (W) 340.0 50 Gain = 26 dB TA = 25 °C PVCC = 26 V 40 40.0 0 −60.0 Phase (°) 90 GAIN/PHASE (BTL) vs FREQUENCY −10 30 −160.0 Gain = 26 dB PVCC = 12 V TA = 25 °C RL = 8 Ω −20 20 10 −30 0 0 1 2 3 4 100 1k Frequency (Hz) 5 PLIMIT Voltage (V) 10k −360.0 100k G016 G013 Figure 13. Figure 14. MAXIMUM OUTPUT POWER (BTL) vs SUPPLY VOLTAGE MAXIMUM OUTPUT POWER (BTL) vs SUPPLY VOLTAGE 60 40 THD+N = 1 % THD+N = 10 % THD+N = 1 % ;PLIMIT = 1.85 V THD+N = 10 % ;PLIMIT = 1.85 V THD+N = 1 % ;PLIMIT = 4.25 V THD+N = 10 % ;PLIMIT = 4.25 V 30 25 20 Gain = 26 dB TA = 25 °C RL = 8 Ω 15 THD+N = 1 % THD+N = 10 % THD+N = 1 % ;PLIMIT = 1.85 V THD+N = 10 % ;PLIMIT = 1.85 V THD+N = 1 % ;PLIMIT = 4.25 V THD+N = 10 % ;PLIMIT = 4.25 V 55 Maximum Output Power per Channel (W) 35 Maximum Output Power per Channel (W) 10 −260.0 Gain Phase 10 50 45 40 35 30 Gain = 26 dB TA = 25 °C RL = 4 Ω 25 20 15 10 5 5 0 4 6 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 26 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 Supply Voltage (V) G014 Figure 15. G015 Figure 16. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 11 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) CROSSTALK (BTL) vs FREQUENCY PSRR vs FREQUENCY 0 0 Gain = 26 dB PVCC = 24 V TA = 25 °C RL = 8 Ω −10 −20 Gain = 26 dB PVCC = 12 DC + 200 mVpp TA = 25 °C RL = 8Ω −10 −20 −30 −30 −50 kSVR (dB) Crosstalk (dB) −40 −60 −70 −80 −40 −50 −60 −70 −90 −80 −100 −120 −90 Right to Left Left to Right −110 20 100 1k Frequency (Hz) 10k 20k −100 Left Channel Right Channel 20 100 1k Frequency (Hz) G017 Figure 17. 12 10k 20k G018 Figure 18. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 DEVICE INFORMATION TYPICAL APPLICATION PVCC PVCC DECOUPLING PVCC OUTPUT FILTER 10nF 1nF 100nF 220µF EMI R-C SNUBBER 10µH 100k GND 3.3R GND FAULTZ 1µF 680nF RP1 RP1 TPA3131D2 7.4V 75kQ 27kQ TPA3132D2 19V 56kQ 39kQ BSPR PVCC OUTPR 25 26 27 FAULTZ PVCC 28 29 INPR GND GND 1nF BSNR 3.3R 10µH 220nF GND GND 220nF BSNL 10µH OUTNL GND GND 3.3R 680nF 1nF 10nF 220nF GND 10nF OUTNR 16 17 GND 680nF OUTPL PVCC 30 8 AM1 3.3R 31 18 9 AM2 7 14 MUTE 20 19 15 1µF 5 21 6 BSPL INPL 22 TPA3131D2 TPA3132D2 4 13 INNL 3 PVCC GND 23 PVCC IN_N_LEFT IN_P_LEFT MUTE GND 24 1nF 10nF GND 2 12 GAIN/SLV 1µF 1 AVCC GVDD 11 RP2 SYNC 20k 10 PLIMIT 1µF 32 RP1 AM0 100k INNR 1µF SDZ 220nF IN_P_RIGHT IN_N_RIGHT GND 680nF GND 1nF 10nF 3.3R PVCC 10µH 1nF 100nF 220µF GND PVCC DECOUPLING Figure 19. Typical Application Schematic GAIN SETTING AND MASTER / SLAVE The gain of the TPA3131D2 is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up and cannot be changed while device is powered. shows the recommended resistor values and the state and gain: Table 1. GAIN and MASTER/SLAVE MASTER / SLAVE MODE GAIN R1 (to GND) Master 20 dB Master 26 dB Master R2 (to GVDD) INPUT IMPEDANCE 5.6 kΩ OPEN 60 kΩ 20 kΩ 100 kΩ 30 kΩ 32 dB 39 kΩ 100 kΩ 15 kΩ Master 36 dB 47 kΩ 75 kΩ 9 kΩ Slave 20 dB 51 kΩ 51 kΩ 60 kΩ Slave 26 dB 75 kΩ 47 kΩ 30 kΩ Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 13 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com Table 1. GAIN and MASTER/SLAVE (continued) MASTER / SLAVE MODE GAIN R1 (to GND) R2 (to GVDD) INPUT IMPEDANCE Slave 32 dB 100 kΩ 39 kΩ 15 kΩ Slave 36 dB 100 kΩ 16 kΩ 9 kΩ 100k R2 PLIMIT 1µF R1 1 GVDD 20k 2 GAIN/SLV 3 AGND GND 4 INNL 5 INPL 6 Figure 20. Gain and Master/Slave Select Resistors In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL logic levels with compliance to GVDD. INPUT IMPEDANCE The TPA3131/32D2 input stage is a fully differential input stage and the input impedance changes with the gain setting from 9 kΩ at 36 dB gain to 60 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 kΩ. The inputs need to be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during powerON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the following cut-off frequency: 1 ƒf = 2pZiCi (1) If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10 times lower capacitors can used – for example, a 1 µF can be used. Table 2. Recommended Input AC-Coupling Capacitors GAIN INPUT IMPEDANCE INPUT CAPACITANCE HIGH-PASS FILTER 20 dB 60 kΩ 1.5 µF 1.8 Hz 26 dB 30 kΩ 3.3 µF 1.6 Hz 32 dB 15 kΩ 5.6 µF 2.3 Hz 36 dB 9 kΩ 10 µF 1.8 Hz Zf Ci Input Signal IN Zi Figure 21. Input AC Coupling The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum or ceramic. If a polarized type is used the positive connection should face the input pins which are biased to 3 Vdc. 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 START-UP/SHUTDOWN OPERATION The TPA3131/32D2 employs a shutdown mode of operation designed to reduce supply current (Icc) to the absolute minimum level during periods of nonuse for power conservation. The SDZ input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low will put the outputs to mute and the amplifier to enter a low-current state. It is not recommended to leave SDZ unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is selected and cannot be changed until the next power-up. PLIMIT OPERATION The TPA3131/32D2 has a built-in voltage limiter that can be used to limit the output voltage level below the supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits the output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Add a 1 µF capacitor from pin PLIMIT to ground to ensure stability. Figure 22. POWER LIMIT Example The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to a fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to PVCC. This "virtual" rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 15 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com ææ ö ö RL çç ç ÷ ´ VP ÷÷ è RL + 2 ´ RS ø ø = è 2 ´ RL POUT 2 for unclipped power (2) Where: RS is the total series resistance including RDS(on), and output filter resistance. RL is the load resistance. VP is the peak amplitude VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP POUT (10%THD) = 1.25 × POUT (unclipped) 7 7 6 6 5 5 PLIMIT [V] PLIMIT [V] Increasing the PLIMIT voltage from a given value increases the maximum output voltage swing until it equals PVCC. Adjusting PLIMIT to a higher value will disable the PLIMIT function and will offer highest available output power, however for TPA3131D2 and TPA3132D2 it is always advised to use the PLIMIT function if PVCC is higher than nominal value to prevent shutdown due to over current protection. If PLIMIT is disabled on TPA3131D2 and TPA3132D2 an over current shutdown can occur with minimum recommended load impedance when PVCC is higher than its nominal value. To disable the PLIMIT function, the PLIMIT pin is simply connected to GVDD. 4 3 2 4 3 2 TPA3131D2 8 1 TPA3131D2 4 1 TPA3132D2 8 TPA3132D2 4 0 0 0 5 10 15 20 25 OUTPUT POWER [W] 30 0 10 20 Figure 23. PLIMIT vs. Max. Output Power, 8Ω load 30 40 50 OUTPUT POWER [W] C001 60 C002 Figure 24. PLIMIT vs. Max. Output Power, 4Ω load Table 3. POWER LIMIT Example (1) MINIMUM PVCC (V) PART NUMBERS PLIMIT VOLTAGE (V) (1) R to GND R to GVDD OUTPUT POWER 8Ω (W) 7.4 V TPA3131D2, TPA3132D2 1.85 27 kΩ 75 kΩ 4 12 V TPA3132D2 2.87 39 kΩ 56 kΩ 10 19 V TPA3132D2 4.26 56 kΩ 36 kΩ 25 PLIMIT measurements taken with EVM gain set to 26dB and input level adjusted for 10% THD. GVDD SUPPLY The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with a X5R ceramic 1 µF capacitor to GND. The GVDD supply is not intended to be used for external supply. It is recommended to limit the current consumption by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 kΩ or more. 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 BSPx AND BSNx CAPACITORS The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220 nF ceramic capacitor of quality X5R or better, rated for at least 16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuit diagram in Figure 19.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the highside MOSFETs turned on. DIFFERENTIAL INPUTS The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3131/32D2 with a differential source, connect the positive lead of the audio source to the RINP or LINP input and the negative lead from the audio source to the RINN or LINN input. To use the TPA3131/32D2 with a single-ended source, ac ground the negative input through a capacitor equal in value to the input capacitor on positive and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same. The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc blocking capacitors to become completely charged during the 10 ms power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched. MONO MODE (PBTL) The TPA3131/32D2 can be connected in MONO mode enabling up to 85W output power. This is done by: • Connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during power up. • Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for the negative terminal. • Analog input signal is applied to INPR and INNR. TPA3131D2 TPA3132D2 4.5V-26V PSU Right Left PBTL Detect Right LC Filter Left LC Filter Figure 25. OUTPUT MODE SELECT Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 17 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com DEVICE PROTECTION SYSTEM The TPA3131/32D2 contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits, overload, over temperature, and under-voltage. The FAULTZ pin will signal if an error is detected according to the fault table below: Table 4. Fault Reporting FAULT TRIGGERING CONDITION (typical value) FAULTZ ACTION LATCHED/SELFCLEARING Over Current Output short or short to PVCC or GND Low Output high impedance Latched Over Temperature Tj > 150°C Low Output high impedance Latched Too High DC Offset DC output voltage Low Output high impedance Latched Under Voltage on PVCC PVCC < 4.5V – Output high impedance Self-clearing Over Voltage on PVCC PVCC > 27V – Output high impedance Self-clearing DC DETECT PROTECTION The TPA3131/32D2 has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the DC Protection function to automatically drive the SDZ pin low which clears the DC Detect protection latch. A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 60% for more than 420 msec at the same polarity. Table x below shows some examples of the typical DC Detect Protection threshold for several values of the supply voltage. This feature protects the speaker from large DC currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at powerup until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults. The minimum output offset voltages required to trigger the DC detect are show in Table 5. The outputs must remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect. Table 5. DC Detect Threshold PVCC (V) VOS - OUTPUT OFFSET VOLTAGE (V) 4.5 0.96 6 1.30 12 2.60 18 3.90 SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE The TPA3131/32D2 has protection from over current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched to a high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SDZ pin through the low state. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the shortcircuit protection latch. In systems where a possibility of a permanent short from the output to PVDD or to a high voltage battery like a car battery can occur, pull the MUTE pin low with the FAULTZ signal with a inverting transistor to ensure a highZ restart, like shown in the figure below: 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 > 1.4sec /FAULTZ 1µF 100k INPR 100k INNR 1µF /FAULTZ IN_P_RIGHT IN_N_RIGHT SDZ mP MUTE TPA3131/32D2 FAULTZ GND 1µF IN_N_LEFT IN_P_LEFT MUTE GND INNL INPL 1µF MUTE 30 31 FAULTZ 4 5 6 7 8 AM1 9 AM2 3 11 GAIN/SLV MUTE 10 100k 1µF 1 2 SYNC GVDD AM0 PLIMIT 32 SDZ GND Figure 26. MUTE Driven by Inverted FAULTZ Figure 27. Timing Requirement for SDZ THERMAL PROTECTION Thermal protection on the TPA3131/32D2 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched fault. Thermal protection faults are reported on the FAULTZ terminal as a low state. If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal protection latch. THERMAL DESIGN Main thermal path for cooling the device is from the bottom side Power-Pad through multiple via connections in the PCB to the bottom side ground plane. The high power efficiency allows TPA3131D2 to be operated continuously at rated output power into both 4Ω and 8Ω load, and TPA3132D2 into 8Ω load using a PCB layout similar to what is used in the TPA3131D2/32D2 EVMs. The rated output power of TPA3132D2 into 4Ω load will be available only for a limited duration of time when using a PCB layout similar to the EVM layout. Sustained power output into 4Ω needs to be limited to prevent excess heating of the device. TPA3132D2 will be able to output full output power for a limited duration of time. The duration depends on the actual PCB layout. For the TPA3132D2 EVM layout the TPA3132D2 full output power with 4Ω load can be illustrated with a burst test at room temp (25°C): Table 6. TPA3132D2 EVM Burst Output Power BURST RATIO FULL POWER 1kHz REDUCED POWER 1kHz (1/8 of full power) MAXIMUM DEVICE TEMPERATURE PCB TEMPERATURE (Bottom Side, Under Device) 1:3 1 Cycle 44W/4Ω 2 Cycles 5.25W/4Ω 116°C 85°C 2:5 2 Cycles 44W/4Ω 3 Cycles 5.25W/4Ω 143°C 102°C Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 19 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com It is not recommended to operate the device with a maximum temperature above 150°C. Figure 28. TPA3132D2 EVM TEMPERATURE WITH 2:5 (42W/5.25W/4Ω) BURST POWER It is advised to use the PLIMT function to avoid thermal shutdown in system designs not using signal processing to limit the average output power. Such systems can accidentally exceed the thermal limits of the amplifier and a OTE shutdown will occur. EFFICIENCY: LC FILTER REQUIRED WITH THE TRADITIONAL CLASS-D MODULATION SCHEME The main reason that the traditional class-D amplifier-based on AD modulation needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3131/32D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. FERRITE BEAD FILTER CONSIDERATIONS Using the Advanced Emissions Suppression Technology in the TPA3131/32D2 amplifier it is possible to design a high efficiency class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the class-D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite beads which have been tested and work well with the TPA3130D2 can be seen in the TPA3130D2EVM user guide SLOU341. A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best. Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to ground. Suggested values for a simple RC series snubber network would be 18 Ω in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the GND pins on the IC. Figure 29. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 21 TPA3131D2 TPA3132D2 SLOS841 – JULY 2013 www.ti.com WHEN TO USE AN OUTPUT FILTER FOR EMI SUPPRESSION The TPA3131/32D2 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 125 cm and high power. The TPA3131/32D2 EVM passes FCC class-B specifications under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency. There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic second order Butterworth filter similar to those shown in the figures below can be used. Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference. 10 µH OUTP C2 L1 0.68 µF 4W-8W 10 µH OUTN C3 L2 0.68 µF Ferrite Chip Bead OUTP 1 nF 4W-8W Ferrite Chip Bead OUTN 1 nF Figure 30. AM AVOIDANCE EMI REDUCTION To reduce interference in the AM radio band, the TPA3131/32D2 has the ability to change the switching frequency via AM<2:0> pins. The recommended frequencies are listed in Table 7. The fundamental frequency and its second harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the switching frequency being demodulated by the AM radio. Table 7. AM Frequencies US EUROPEAN AM FREQUENCY (kHz) AM FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) AM2 AM1 AM0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 522-540 540-917 540-914 500 917-1125 914-1122 600 (or 400) 1125-1375 1122-1373 500 1375-1547 1373-1548 600 (or 400) 1547-1700 22 1548-1701 600 (or 500) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 TPA3131D2 TPA3132D2 www.ti.com SLOS841 – JULY 2013 PRINTED-CIRCUIT BOARD (PCB LAYOUT) The TPA3131/32D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements. • Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should be placed near the TPA3131/32D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality to the PVCC connections at each end of the chip. • Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna. • Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at the IC GND, which should be used as a central ground connection or star ground for the TPA3131/32D2. • Output filter — The ferrite EMI filter (see Figure 30) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded. For an example layout, see the TPA3131/32D2 Evaluation Module (TPA3131/32D2EVM) User Manual. Both the EVM user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: TPA3131D2 TPA3132D2 23 PACKAGE OPTION ADDENDUM www.ti.com 20-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TPA3131D2RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3131 TPA3131D2RHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3131 TPA3132D2RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3132 TPA3132D2RHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3132 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPA3131D2RHBR VQFN RHB 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPA3131D2RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPA3132D2RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPA3132D2RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA3131D2RHBR VQFN RHB 32 3000 367.0 367.0 35.0 TPA3131D2RHBT VQFN RHB 32 250 210.0 185.0 35.0 TPA3132D2RHBR VQFN RHB 32 3000 367.0 367.0 35.0 TPA3132D2RHBT VQFN RHB 32 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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