TI THS7320IYHCR

THS7320
www.ti.com
SBOS565B – JULY 2011 – REVISED SEPTEMBER 2012
3-Channel ED Filter Video Amplifier with 4-V/V Gain
Check for Samples: THS7320
FEATURES
DESCRIPTION
•
Fabricated using the revolutionary, complementary
Silicon-Germanium (SiGe) BiCom-3X process, the
THS7320 is a very low power, single-supply, 2.6-V to
5-V, three-channel integrated video buffer with a gain
of 4 V/V. This device is ideal for battery-powered
applications where size and power are critical
parameters. The total quiescent current is only 3.5
mA at 3 V and the video portion can be reduced
down to 0.15 µA while disabled.
1
2
•
•
•
•
•
•
•
•
•
Very Low Total Quiescent Current:
3.5 mA at 3 V
Disabled Supply Current: 0.15 µA
Third-Order Butterworth Low-Pass Filters:
– –1 dB at 17 MHz
– –3 dB at 20 MHz
– Attenuation: 21 dB at 43 MHz
– Supports Y’P’BP’R 480p/576p or
R’G’B’ Video
– Supports Oversampled Systems
Generating CVBS, S-Video, or
Y’P’BP’R 480i/576i
DC-Coupled Input with 150-mV Output Shift
Built-In Gain: 4 V/V (12 dB)
Single-Supply Operation: +2.6 V to +5 V
Rail-to-Rail Output Supports
AC- or DC-Coupling
Low Differential Gain/Phase: 0.1%/0.1°
Output Pins Support ±8-kV IEC ESD Protection
Ultra Small, WCSP 9-Ball Package:
– Tiny PCB Area: 0.96 mm x 0.96 mm (Typ)
– Very Low Profile Height: 0.5 mm (Max)
– Pitch: 0.3 mm
The THS7320 video section incorporates three
enhanced definition (ED) filter channels with thirdorder Butterworth characteristics. These filters are
useful
as
digital-to-analog
converter
(DAC)
reconstruction filters or as analog-to-digital converter
(ADC) antialiasing filters. The THS7320 is also ideal
for oversampled systems that produce standard
definition (SD) signals including CVBS, S-Video,
480i/576iY’P’BP’R, Y’U’V’, and R’G’B’.
The THS7320 is designed for dc-coupled inputs. To
mitigate any DAC/encoder termination interaction, the
input impedance is a very high 2.4 MΩ. The internal
level shift adds 150-mV offset at the output to
eliminate saturation or clipping concerns. The rail-torail output supports either dc- or ac- coupling.
The THS7320 is available in an ultra small, 9-ball
wafer chip-scale package (WCSP) package that
requires an ultra small, 0.92-mm2 (typ) printed circuit
board (PCB) area.
APPLICATIONS
•
•
•
Personal Media Players
Digital Cameras
Cellular Phone Video Output Buffering
Level
Shift
3-Pole
20-MHz
75 W
2 V/V
Channel 1
Out 1
2 V/V
LPF
75 W
DAC/Encoder
R
Level
Shift
3-Pole
20-MHz
75 W
2 V/V
Channel 2
Out 2
2 V/V
LPF
75 W
R
Level
Shift
2 V/V
Channel 3
3-Pole
20-MHz
75 W
Out 3
2 V/V
LPF
75 W
R
+2.6 V to +5 V
Enable
Simplified Application Circuit
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
THS7320
SBOS565B – JULY 2011 – REVISED SEPTEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PACKAGED DEVICES
PACKAGE TYPE
PACKAGE MARKING
TRANSPORT MEDIA,
QUANTITY
ECO STATUS (2)
THS7320IYHCR
DSBGA (9-Ball WCSP)
QJK
Tape and Reel, 3000
Pb-Free, Green
THS7320IYHCT
DSBGA (9-Ball WCSP)
QJK
Tape and Reel, 250
Pb-Free, Green
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
Eco-Status information. Additional details including specific material content can be accessed at www.ti.com/leadfree.
GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion
dates, go to www.ti.com/leadfree.
Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total
product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage, VS+ to GND
Video input voltage, video enable pin
VALUE
UNIT
–0.4 to +5.5
V
–0.4 to VS+ + 0.4
V
±75
mA
Output current, IO
Continuous power dissipation
See Thermal Information table
Maximum junction temperature, any condition
(2)
+150
°C
Maximum junction temperature, continuous operation, long-term reliability (3), TJ
+125
°C
Storage temperature range, Tstg
+300
°C
Human body model (HBM)
6000
V
Charge device model (CDM)
1000
V
Machine model (MM)
200
V
IEC 61000-4-2 contact discharge
20
kV
ESD ratings: all pins
ESD ratings: video output pins
(1)
(2)
(3)
, TJ
Stresses these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those
specified is not implied.
The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
Supply voltage, VS+
2.6
3
5
V
Ambient temperature, TA
–40
+85
°C
2
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UNIT
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SBOS565B – JULY 2011 – REVISED SEPTEMBER 2012
ELECTRICAL CHARACTERISTICS: VS+ = 3 V, Video Section
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input and output, unless otherwise noted.
THS7320IYHC
PARAMETER
CONDITIONS
MIN
UNIT
TEST
LEVEL (1)
11
MHz
C
17
MHz
A
MHz
B
TYP
MAX
AC PERFORMANCE
Passband bandwidth
–3-dB bandwidth
Normalized stop band gain
–0.1 dB, relative to 1 MHz
±1 dB, relative to 1 MHz
14
Relative to 1 MHz
17
20
f = 43 MHz, relative to 1 MHz
–21
f = 54 MHz, relative to 1 MHz
Group delay
f = 100 kHz
Group delay variation
f = 11 MHz with respect to 1 MHz
Channel-to-channel delay
–12
dB
A
–27
dB
C
19
ns
C
4
ns
C
0.3
ns
C
Differential gain
NTSC and PAL
0.1
%
C
Differential phase
NTSC and PAL
0.1
°
C
Total harmonic distortion
f = 1 MHz, VO = 1.4 VPP
–80
dB
C
100 kHz to 13.5 MHz, non-weighted
65
dB
C
100 kHz to 13.5 MHz, unified weighting
75
dB
C
100 kHz to 6 MHz, non-weighted
69
dB
C
100 kHz to 6 MHz, unified weighting
78
dB
C
Rise/fall time
VOUT = 2-V step
20
ns
C
Slew rate
VOUT = 2-V step
80
V/µs
C
f = 12 MHz
1.4
Ω
C
Signal-to-noise ratio
Output impedance
f = 12 MHz, return loss
41
Disabled
Crosstalk
20 || 11
Output referred at connectors, f = 10 MHz
–51
dB
C
kΩ || pF
C
dB
C
DC PERFORMANCE
Biased output voltage
VIN = 0 V
Input voltage range
At dc input, limited by output
75
Input bias current
150
320
–0.03 to 0.65
–1000
Input resistance
–130
–40
2.4 || 2
Voltage gain
3.92
4
4.08
Channel-to-channel
–1
±0.2
+1
High output voltage swing
RL = 150 Ω to GND
2.62
Low output voltage swing
RL = 150 Ω to GND
Output current
Short-circuit
Gain matching
mV
A
V
C
nA
A
MΩ || pF
C
V/V
A
%
A
OUTPUT CHARACTERISTICS
(1)
2.8
V
A
0.01
V
C
mA
C
65
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation only. (C) Typical value only for information.
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ELECTRICAL CHARACTERISTICS: VS+ = 3 V, Video Section (continued)
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input and output, unless otherwise noted.
THS7320IYHC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
POWER SUPPLY (VS+)
Operating Voltage
VS+ total quiescent current
VS+ power-supply rejection ratio
(PSRR)
VS+
2.5
3
5.5
V
B
Video enable pin = 1.8 V, no load, VIN = 0 V
2.7
3.5
4.7
mA
A
0.15
1
µA
A
dB
A
Video enable pin = 0 V, no load, VIN = 0 V
At dc
44
50
VIDEO ENABLE LOGIC CHARACTERISTICS
VIH
Enabled
VIL
Disabled
1.17
V
A
0.4
V
IIH
Enable pin = 1.8 V, current flows into the pin
A
3
µA
A
IIH
Enable pin = 3 V, current flows into the pin
IIL
Enable pin = 0 V, current flows into the pin
3
5
µA
A
–0.01
–0.5
µA
A
1
MΩ
C
Disable time
130
ns
C
Enable time
120
ns
C
Input resistance
1.8
THERMAL INFORMATION
THS7320IYHC
THERMAL METRIC
(1)
YHC
UNITS
9 PINS
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
2.2
θJB
Junction-to-board thermal resistance
2.4
ψJT
Junction-to-top characterization parameter
8.9
ψJB
Junction-to-board characterization parameter
88.4
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
(1)
4
159.3
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBOS565B – JULY 2011 – REVISED SEPTEMBER 2012
VIDEO PARAMETER MEASUREMENT INFORMATION
Level
Shift
3-Pole
20-MHz
2 V/V
2 V/V
LPF
R
2 V/V
RLOAD
CLOAD
RLOAD
CLOAD
RLOAD
2 V/V
LPF
R
RSOURCE
CLOAD
3-Pole
20-MHz
Level
Shift
Level
Shift
3-Pole
20-MHz
VSOURCE
2 V/V
VBIAS
+
-
2 V/V
LPF
R
0.1 mF
Enable
+
4.7 mF
+VS
Figure 1. Test Circuit
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PIN CONFIGURATION
YHC PACKAGE
WCSP 9-BALL
(TOP VIEW)
1
2
3
Ch 1 IN
GND
Ch 1 OUT
Ch 2 IN
EN
Ch 2 OUT
Ch 3 IN
VS+
Ch 3 OUT
A
B
C
PIN ASSIGNMENTS
NAME
NO.
I/O
Channel 1 input
A1
I
Video input, channel 1
DESCRIPTION
GND
A2
I
Ground for all circuitry
Channel 1 output
A3
O
Video output, channel 1
Channel 2 input
B1
I
Video input, channel 2
EN
B2
I
Video enable pin. Logic high enables the video channels; logic low disables the video
channels.
Channel 2 output
B3
O
Video output, channel 2
Channel 3 input
C1
I
Video input, channel 3
VS+
C2
I
Power-supply pin; connect to +2.6 V up to +5 V.
Channel 3 output
C3
O
Video output, channel 3
FUNCTIONAL BLOCK DIAGRAM
Level
Shift
Channel 1 Input
2 V/V
LPF
Level
Shift
Channel 2 Input
2 V/V
2 V/V
2 V/V
Channel 1 Output
2 V/V
Channel 2 Output
2 V/V
Channel 3 Output
3-Pole
20-MHz
LPF
Level
Shift
Channel 3 Input
3-Pole
20-MHz
3-Pole
20-MHz
LPF
1 MW
VS+
6
Enable
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs: VS+ = 2.6 V
TITLE
Signal Gain vs Frequency
FIGURE
Figure 2, Figure 3
Phase vs Frequency
Figure 4
Group Delay vs Frequency
Figure 5
Differential Gain
Figure 6
Differential Phase
Figure 7
Small-Signal Frequency Response vs Capacitive Load
Figure 8
Small-Signal Frequency Response vs Resistive Load
Figure 9
Crosstalk vs Frequency
Figure 10
Second-Order Harmonic Distortion vs Frequency
Figure 11
Third-Order Harmonic Distortion vs Frequency
Figure 12
Large-Signal Pulse Response vs Time
Figure 13
Small-Signal Pulse Response vs Time
Figure 14
Slew Rate vs Output Voltage
Figure 15
Enable/Disable Response vs Time
Figure 16
Table 2. Table of Graphs: VS+ = 3 V
TITLE
FIGURE
Signal Gain vs Frequency
Figure 17, Figure 18
Small-Signal Frequency vs Temperature
Figure 19, Figure 21
Small-Signal Frequency vs Temperature (Enlarged)
Figure 20, Figure 22
Phase vs Frequency
Figure 23
Group Delay vs Frequency
Figure 24
Differential Gain
Figure 25
Differential Phase
Figure 26
Small-Signal Frequency Response vs Capacitive Load
Figure 27
Small-Signal Frequency Response vs Resistive Load
Figure 28
Crosstalk vs Frequency
Figure 29
Second-Order Harmonic Distortion vs Frequency
Figure 30
Third-Order Harmonic Distortion vs Frequency
Figure 31
Large-Signal Pulse Response vs Time
Figure 32
Small-Signal Pulse Response vs Time
Figure 33
Slew Rate vs Output Voltage
Figure 34
Enable/Disable Response vs Time
Figure 35
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Table 3. Table of Graphs: VS+ = 5 V
TITLE
FIGURE
Signal Gain vs Frequency
Figure 36, Figure 37
Phase vs Frequency
Figure 38
Group Delay vs Frequency
Figure 39
Differential Gain
Figure 40
Differential Phase
Figure 41
Small-Signal Frequency Response vs Capacitive Load
Figure 42
Small-Signal Frequency Response vs Resistive Load
Figure 43
Crosstalk vs Frequency
Figure 44
Second-Order Harmonic Distortion vs Frequency
Figure 45
Third-Order Harmonic Distortion vs Frequency
Figure 46
Large-Signal Pulse Response vs Time
Figure 47
Small-Signal Pulse Response vs Time
Figure 48
Slew Rate vs Output Voltage
Figure 49
Enable/Disable Response vs Time
Figure 50
Table 4. Table of Graphs: General
TITLE
FIGURE
Output Impedance vs Frequency
Figure 51
S22 Output Return Loss vs Frequency
Figure 52
Disabled Output Impedance vs Frequency
Figure 53
Power-Supply Rejection Ratio vs Frequency
Figure 54
8
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SBOS565B – JULY 2011 – REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS: VS+ = 2.6 V
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
SIGNAL GAIN vs FREQUENCY
SIGNAL GAIN vs FREQUENCY
20
12.5
VOUT = 200 mVPP
VOUT = 1 VPP
VOUT = 2 VPP
0
11.5
−10
11
−20
10.5
10
−30
−40
9.5
VS+ = 2.6 V
Input Bias = 0.25 VDC
−50
1M
VS+ = 2.6 V
Input Bias = 0.25 VDC
12
Gain (dB)
Gain (dB)
10
VOUT = 200 mVPP
VOUT = 1 VPP
VOUT = 2 VPP
9
10 M
100 M
Frequency (Hz)
1G
8.5
1M
G014
10M
Frequency (Hz)
Figure 2.
100M
Figure 3.
PHASE vs FREQUENCY
GROUP DELAY vs FREQUENCY
45
30
0
25
Group Delay (ns)
45
Phase (°)
90
135
180
225
270
315
VS+ = 2.6 V
VOUT = 200 mVPP
Input Bias = 0.25 VDC
360
100k
20
15
10
1M
10M
5
1M
100M
Frequency (Hz)
VS+ = 2.6 V
VOUT = 200 mVPP
Input Bias = 0.25 VDC
10 M
Frequency (Hz)
G046
Figure 4.
G004
Figure 5.
DIFFERENTIAL GAIN
DIFFERENTIAL PHASE
0.03
0.14
VS+ = 2.6 V
VS+ = 2.6 V
0.02
0.12
PAL
Differential Phase (°)
Differential Gain (%)
100 M
0.1
PAL
0.08
NTSC
0.06
0.04
0.02
0.01
NTSC
0
-0.01
-0.02
-0.03
-0.04
-0.05
0
1st
2nd
3rd
4th
Step
5th
6th
1st
G028
Figure 6.
2nd
3rd
4th
5th
6th
Step
G043
Figure 7.
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TYPICAL CHARACTERISTICS: VS+ = 2.6 V (continued)
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
vs CAPACITIVE LOAD
SMALL-SIGNAL FREQUENCY RESPONSE
vs RESISTIVE LOAD
20
20
CL = Stray (2 pF)
CL = 6.2 pF
CL = 10 pF
CL =18 pF
10
0
−10
Gain (dB)
Gain (dB)
0
RL = 75 Ω
RL = 150 Ω
RL = Open
10
−20
−30
−40
−50
−60
1M
−10
−20
VS+ = 2.6 V
Load = 150 Ω || CL
VOUT = 200 mVPP
Input Bias = 0.25 VDC
−30
VS+ = 2.6 V
VOUT = 200 mVPP
Input Bias = 0.25 VDC
−40
10 M
100 M
Frequency (Hz)
1G
−50
1M
G029
10M
Figure 8.
SECOND-ORDER HARMONIC DISTORTION
vs FREQUENCY
(1)
Crosstalk (dB)
VS+ = 2.6 V
Ch. 1 into Ch. 2
Ch. 1 into Ch. 3
Ch. 2 into Ch. 1
Ch. 2 into Ch. 3
Ch. 3 into Ch. 1
Ch. 3 into Ch. 2
−60
−70
−80
−90
1M
10 M
Frequency (Hz)
-40
Second-Order Harmonic Distortion (dBc)
−30
−50
1G
Figure 9.
CROSSTALK vs FREQUENCY
−40
100M
Frequency (Hz)
100 M
VOUT = 0.25 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
-50
-60
-70
-80
-90
VS+ = 2.6 V
Input Bias = 0.25 VDC
-100
1M
G001
10M
Frequency (Hz)
Figure 10.
THIRD-ORDER HARMONIC DISTORTION
vs FREQUENCY
-50
-60
LARGE-SIGNAL PULSE RESPONSE vs TIME
4.5
VS+ = 2.6 V
Input Bias = 0.25 VDC
3.5
-70
-80
Input Voltage Waveforms
2.5
2
Input tR/tF = 70 ns
1.5
1
Input tR/tF = 1 ns
0
-0.5
-100
1M
10M
Frequency (Hz)
-50
0
10
-0.25
-0.75
-1.25
Output Voltage Waveforms
VS+ = 2.6 V
-1.75
50
100
150
200
250
Time (ns)
300
350
400
G047
G035
Figure 12.
(1)
0.25
Input tR/tF = 1 ns
3
0.5
-90
0.75
Input tR/tF = 70 ns
4
Output Voltage (V)
VOUT = 0.25 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
Input Voltage (V)
Third-Order Harmonic Distortion (dBc)
-40
G036
Figure 11.
Figure 13.
Measured at output connector relative to source output connector.
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TYPICAL CHARACTERISTICS: VS+ = 2.6 V (continued)
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
SMALL-SIGNAL PULSE RESPONSE vs TIME
1.5
1.45
0.25
Input tR/tF = 70 ns
1.2
1.15
Input tR/tF = 1 ns
1.1
1.05
VS+ = 2.6 V
-50
0
50
80
0.2
0.15
Slew Rate (V/ms)
Input Voltage Waveforms
1.25
1
VS+ = 2.6 V
Positive and Negative Slew Rates
Input tR/tF = 1 ns
1.3
100
Input Voltage (V)
Output Voltage (V)
1.4
1.35
SLEW RATE vs OUTPUT VOLTAGE
0.3
Input tR/tF = 70 ns
0.1
0.05
150
200
250
300
350
0
0.5
400
Time (ns)
40
20
Output Voltage
Waveforms
100
60
1
1.5
Output Voltage (VPP)
G044
Figure 14.
2
G045
Figure 15.
ENABLE/DISABLE RESPONSE vs TIME
4
1.6
VS+ = 2.6 V
3
1.4
Enabled
Output Voltage (V)
1
Enable Input Voltage
1
Disabled
0.8
0
0.6
-1
0.4
-2
Output Voltage
0.2
-3
0
-4
Enable Input Voltage (V)
2
1.2
-5
-0.2
-50
50
150
250
350
450
Time (ns)
550
650
G048
Figure 16.
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TYPICAL CHARACTERISTICS: VS+ = 3 V
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
SIGNAL GAIN vs FREQUENCY
SIGNAL GAIN vs FREQUENCY
20
12.5
VOUT = 200 mVPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 2.5 VPP
10
11.5
−10
Gain (dB)
Gain (dB)
0
−20
−30
−40
11
10.5
10
VOUT = 200 mVPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 2.5 VPP
9.5
VS+ = 3 V
Input Bias = 0.33 VDC
−50
1M
VS+ = 3 V
Input Bias = 0.33 VDC
12
9
10 M
100 M
Frequency (Hz)
1G
8.5
1M
G016
10M
Frequency (Hz)
Figure 17.
Figure 18.
SIGNAL GAIN vs TEMPERATURE
SIGNAL GAIN vs TEMPERATURE
20
12.5
TA = −40°C
TA = 25°C
TA = 85°C
10
Gain (dB)
Gain (dB)
11.5
−10
−20
−40
−50
1M
TA = −40°C
TA = 25°C
TA = 85°C
12
0
−30
10.5
10
VS+ = 3 V
Load = 150 Ω || 6.2 pF
VOUT = 200 mVPP
Input Bias = 0.33 VDC
10M
11
9.5
100M
Frequency (Hz)
VS+ = 3 V
Load = 150 Ω || 6.2 pF
VOUT = 200 mVPP
Input Bias = 0.33 VDC
9
1M
1G
10M
Frequency (Hz)
Figure 19.
SIGNAL GAIN vs TEMPERATURE
SIGNAL GAIN vs TEMPERATURE
12.5
TA = −40°C
TA = 25°C
TA = 85°C
10
Gain (dB)
Gain (dB)
11.5
−10
−20
−50
1M
TA = −40°C
TA = 25°C
TA = 85°C
12
0
−40
100M
Frequency (Hz)
10.5
10
VS+ = 3 V
Load = 150 Ω || 6.2 pF
VOUT = 400 mVPP
Input Bias = 0.33 VDC
10M
11
9.5
1G
VS+ = 3 V
Load = 150 Ω || 6.2 pF
VOUT = 400 mVPP
Input Bias = 0.33 VDC
9
1M
Figure 21.
12
100M
Figure 20.
20
−30
100M
10M
Frequency (Hz)
100M
Figure 22.
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TYPICAL CHARACTERISTICS: VS+ = 3 V (continued)
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
PHASE vs FREQUENCY
GROUP DELAY vs FREQUENCY
45
30
0
25
Group Delay (ns)
45
Phase (°)
90
135
180
225
270
315
VS+ = 3 V
VOUT = 200 mVPP
Input Bias = 0.33 VDC
360
100k
20
15
VS+ = 3 V
VOUT = 200 mVPP
Input Bias = 0.33 VDC
10
1M
10M
5
1M
100M
Frequency (Hz)
10 M
Frequency (Hz)
G009
Figure 23.
DIFFERENTIAL GAIN
DIFFERENTIAL PHASE
0.025
VS+ = 3 V
VS+ = 3 V
0.05
0.04
0.03
NTSC
0.02
Differential Phase (°)
0.02
PAL
Differential Gain (%)
G005
Figure 24.
0.06
NTSC
0.015
0.01
PAL
0.005
0.01
0
0
1st
3rd
2nd
4th
5th
1st
6th
Step
3rd
2nd
4th
5th
6th
Step
G020
G012
Figure 25.
Figure 26.
SMALL-SIGNAL FREQUENCY RESPONSE
vs CAPACITIVE LOAD
SMALL-SIGNAL FREQUENCY RESPONSE
vs RESISTIVE LOAD
20
20
CL = Stray (2 pF)
CL = 6.2 pF
CL = 10 pF
CL =18 pF
10
0
RL = 75 Ω
RL = 150 Ω
RL = Open
10
0
−10
Gain (dB)
Gain (dB)
100 M
−20
−30
−40
−50
−60
1M
VS+ = 3 V
Load = 150 Ω || CL
VOUT = 200 mVPP
Input Bias = 0.33 VDC
10 M
100 M
Frequency (Hz)
−10
−20
−30
−40
1G
G030
VS+ = 3 V
VOUT = 200 mVPP
Input Bias = 0.33 VDC
−50
1M
Figure 27.
10M
100M
Frequency (Hz)
1G
Figure 28.
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TYPICAL CHARACTERISTICS: VS+ = 3 V (continued)
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
CROSSTALK vs FREQUENCY
SECOND-ORDER HARMONIC DISTORTION
vs FREQUENCY
(1)
−40
−50
Crosstalk (dB)
VS+ = 3 V
Ch. 1 into Ch. 2
Ch. 1 into Ch. 3
Ch. 2 into Ch. 1
Ch. 2 into Ch. 3
Ch. 3 into Ch. 1
Ch. 3 into Ch. 2
−60
−70
−80
−90
1M
10 M
Frequency (Hz)
-30
Second-Order Harmonic Distortion (dBc)
−30
100 M
VOUT = 0.25 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
-40
VOUT = 1.4 VPP
VOUT = 2 VPP
VOUT = 2.5 VPP
-50
-60
-70
-80
-90
VS+ = 3 V
Input Bias = 0.3 VDC
-100
1M
G002
10M
Frequency (Hz)
Figure 29.
THIRD-ORDER HARMONIC DISTORTION
vs FREQUENCY
-60
VS+ = 3 V
Input Bias = 0.3 VDC
4
-70
-80
Input Voltage Waveforms
3
2.5
Input tR/tF = 70 ns
2
1.5
Input tR/tF = 1 ns
0
1M
VS+ = 3 V
-50
10M
0
100
Input tR/tF = 1 ns
1.43
VS+ = 3 V
-50
0
0.23
100
150
200
250
Time (ns)
14
G010
VS+ = 3 V
Positive and Negative Slew Rates
80
60
40
300
350
0
0.5
400
G008
Figure 33.
(1)
400
20
0.13
50
350
0.18
Output Voltage
Waveforms
1.38
1.33
0.28
Slew Rate (V/µs)
Output Voltage (V)
Input tR/tF = 70 ns
1.48
100
Input Voltage (V)
Input Voltage Waveforms
1.53
300
120
0.33
1.58
250
SLEW RATE vs OUTPUT VOLTAGE
0.38
Input tR/tF = 1 ns
1.63
200
Figure 32.
Input tR/tF = 70 ns
1.68
150
G022
SMALL-SIGNAL PULSE RESPONSE vs TIME
1.73
-1.15
-1.65
50
Figure 31.
1.78
-0.65
Time (ns)
Frequency (Hz)
1.83
-0.15
Output Voltage
Waveforms
0.5
-100
0.35
Input tR/tF = 1 ns
3.5
1
-90
0.85
Input tR/tF = 70 ns
4.5
Output Voltage (V)
-50
LARGE-SIGNAL PULSE RESPONSE vs TIME
5
VOUT = 0.25 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
VOUT = 2.5 VPP
Input Voltage (V)
Third-Order Harmonic Distortion (dBc)
-40
G023
Figure 30.
1
1.5
2
2.5
Output Voltage (VPP)
Figure 34.
Measured at output connector relative to source output connector.
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TYPICAL CHARACTERISTICS: VS+ = 3 V (continued)
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
ENABLE/DISABLE RESPONSE vs TIME
4
1.6
VS+ = 3 V
3
1.4
Enabled
Output Voltage (V)
1
2
Enable Input Voltage
1
Disabled
0.8
0
0.6
-1
0.4
-2
Output Voltage
0.2
-3
0
-4
Enable Input Voltage (V)
1.2
-5
-0.2
-50
50
150
250
350
450
Time (ns)
550
650
G011
Figure 35.
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TYPICAL CHARACTERISTICS: VS+ = 5 V
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
SIGNAL GAIN vs FREQUENCY
SIGNAL GAIN vs FREQUENCY
20
12.5
VOUT = 200 mVPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 2.5 VPP
10
11.5
−10
Gain (dB)
Gain (dB)
0
−20
11
10.5
10
−30
−40
VOUT = 200 mVPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 2.5 VPP
9.5
VS+ = 5 V
Input Bias = 0.5 VDC
−50
1M
VS+ = 5 V
Input Bias = 0.5 VDC
12
9
10 M
100 M
Frequency (Hz)
1G
8.5
1M
G018
10M
Frequency (Hz)
Figure 36.
100M
Figure 37.
PHASE vs FREQUENCY
GROUP DELAY vs FREQUENCY
45
30
0
25
Group Delay (ns)
45
Phase (°)
90
135
180
225
270
315
VS+ = 5 V
VOUT = 200 mVPP
Input Bias = 0.5 VDC
360
100k
20
15
10
1M
10M
5
1M
100M
Frequency (Hz)
VS+ = 5 V
VOUT = 200 mVPP
Input Bias = 0.5 VDC
10 M
Frequency (Hz)
G038
Figure 38.
DIFFERENTIAL GAIN
DIFFERENTIAL PHASE
0.035
VS+ = 5 V
VS+ = 5 V
Differential Phase (°)
Differential Gain (%)
0.03
NTSC
0.08
0.07
PAL
0.06
0.05
0.04
0.03
0.025
PAL
0.02
0.015
0.01
NTSC
0.02
0.005
0.01
0
1st
2nd
3rd
4th
Step
5th
0
6th
1st
G042
Figure 40.
16
G006
Figure 39.
0.1
0.09
100 M
2nd
3rd
4th
Step
5th
6th
G041
Figure 41.
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TYPICAL CHARACTERISTICS: VS+ = 5 V (continued)
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
SMALL-SIGNAL FREQUENCY RESPONSE
vs CAPACITIVE LOAD
SMALL-SIGNAL FREQUENCY RESPONSE
vs RESISTIVE LOAD
20
20
CL = Stray (2 pF)
CL = 6.2 pF
CL = 10 pF
CL =18 pF
10
0
−10
Gain (dB)
Gain (dB)
0
RL = 75 Ω
RL = 150 Ω
RL = Open
10
−20
−30
−40
−50
−60
1M
−10
−20
VS+ = 5 V
Load = 150 Ω || CL
VOUT = 200 mVPP
Input Bias = 0.5 VDC
−30
VS+ = 5 V
VOUT = 200 mVPP
Input Bias = 0.5 VDC
−40
10 M
100 M
Frequency (Hz)
1G
−50
1M
G031
10M
Figure 42.
SECOND-ORDER HARMONIC DISTORTION
vs FREQUENCY
(1)
Crosstalk (dB)
VS+ = 5 V
Ch. 1 into Ch. 2
Ch. 1 into Ch. 3
Ch. 2 into Ch. 1
Ch. 2 into Ch. 3
Ch. 3 into Ch. 1
Ch. 3 into Ch. 2
−60
−70
−80
−90
1M
10 M
Frequency (Hz)
-40
Second-Order Harmonic Distortion (dBc)
−30
−50
1G
Figure 43.
CROSSTALK vs FREQUENCY
−40
100M
Frequency (Hz)
100 M
VOUT = 0.25 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
VOUT = 3 VPP
-50
-60
VS+ = 5 V
Input Bias = 0.5 VDC
-70
-80
-90
-100
1M
G003
10M
Frequency (Hz)
Figure 44.
THIRD-ORDER HARMONIC DISTORTION
vs FREQUENCY
-50
-60
LARGE-SIGNAL PULSE RESPONSE vs TIME
5.5
VS+ = 5 V
Input Bias = 0.5 VDC
4.5
-70
-80
Input Voltage Waveforms
3.5
3
Input tR/tF = 70 ns
2.5
2
Input tR/tF = 1 ns
1M
10M
Frequency (Hz)
VS+ = 5 V
-50
0
-0.5
-1
-1.5
50
100
150
200
250
300
350
400
Time (ns)
G039
G024
Figure 46.
(1)
0
Output Voltage
Waveforms
1
0.5
-100
0.5
Input tR/tF = 1 ns
4
1.5
-90
1
Input tR/tF = 70 ns
5
Output Voltage (V)
VOUT = 0.25 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 1.4 VPP
VOUT = 2 VPP
VOUT = 3 VPP
Input Voltage (V)
Third-Order Harmonic Distortion (dBc)
-40
G007
Figure 45.
Figure 47.
Measured at output connector relative to source output connector.
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TYPICAL CHARACTERISTICS: VS+ = 5 V (continued)
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
SMALL-SIGNAL PULSE RESPONSE vs TIME
2.5
2.45
VS+ = 5 V
Positive and Negative Slew Rates
0.5
Input tR/tF = 1 ns
120
2.3
2.25
Input tR/tF = 70 ns
2.2
2.15
Input tR/tF = 1 ns
2.1
VS+ = 5 V
0
0.4
100
150
80
60
20
0.3
50
100
40
0.35
Output Voltage
Waveforms
2.05
-50
0.45
Input Voltage (V)
Input Voltage Waveforms
Slew Rate (V/µs)
2.4
Output Voltage (V)
160
140
2.35
2
SLEW RATE vs OUTPUT VOLTAGE
0.55
Input tR/tF = 70 ns
200
250
300
350
0
0.5
400
Time (ns)
1
1.5
2
2.5
3
3.5
4
Output Voltage (VPP)
G037
Figure 48.
Figure 49.
ENABLE/DISABLE RESPONSE vs TIME
4
1.6
VS+ = 5 V
3
1.4
Enabled
Output Voltage (V)
2
Enable Input Voltage
1
1
Disabled
0.8
0
0.6
-1
0.4
-2
Output Voltage
0.2
-3
0
-4
Enable Input Voltage (V)
1.2
-5
-0.2
-50
50
150
250
350
450
Time (ns)
550
650
G040
Figure 50.
18
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TYPICAL CHARACTERISTICS: General
At TA = +25°C, load = 150 Ω || 6.2 pF to GND, and dc-coupled input/output, unless otherwise noted.
OUTPUT IMPEDANCE vs FREQUENCY
S22 OUTPUT RETURN LOSS vs FREQUENCY
10
−10
−15
S22, Output Return Loss (dB)
Output Impedance (W)
VS+ = 2.6 V to 5 V
1
VS+ = 2.6 V to 5 V
−20
−25
−30
−35
−40
−45
−50
−55
0.1
100k
1M
10M
Frequency (Hz)
−60
0.1 M
100M
10 M
Frequency (Hz)
100 M
G021
Figure 51.
Figure 52.
DISABLED OUTPUT IMPEDANCE vs FREQUENCY
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
60
100 k
Power−Supply Rejection Ratio (dB)
VS+ = 2.6 V to 5 V
Disable Mode
Output Impedance (Ω)
1M
G049
10 k
1k
0.1 k
0.1 M
1M
10 M
Frequency (Hz)
100 M
VS+ = 2.6 V to 5 V
50
40
30
20
10
0
10 k
G019
Figure 53.
100 k
1M
Frequency (Hz)
10 M
100 M
G025
Figure 54.
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APPLICATION INFORMATION
The THS7320 includes a triple-channel video output amplifier and filter that supports three enhanced-definition
(ED) video and/or RGB video output buffers. The THS7320 also supports standard definition (SD) video for
oversampled systems with a DAC sampling frequency of 54 MHz or greater. Although the THS7320 can be used
for numerous other applications, the needs and requirements of the video signal are the most important design
parameters. Built on the revolutionary, complementary silicon germanium (SiGe) BiCom3X process, the
THS7320 incorporates many attributes not typically found in integrated video parts while consuming very low
power. The THS7320 video portion includes these features:
• Single-supply 2.6-V to 5-V operation with low total quiescent current of 3.4 mA at 3.3 V
• Enable mode for shutting down the THS7320 video amplifiers to save system power in power-sensitive
applications
• DC input configuration with internal 150-mV dc level shifting to prevent sync crushing and saturation effects
• Third-order, 20-MHz (–3-dB) low-pass filter for DAC reconstruction or ADC image rejection; ideal for:
– NTSC/PAL 480p/576p Y’P’BP’R or G’B’R’ (R’G’B’) signals
– NTSC/PAL/SECAM composite video (CVBS), S-Video Y’/C’, 480i/576i Y’P’BP’R, and G’B’R’ (R’G’B’)
signals for oversampled systems
• Internally-fixed gain of 4-V/V (+12-dB) amplifiers that allow for dc-coupling or traditional ac-coupling
OPERATING VOLTAGE
The THS7320 is designed to operate from 2.6 V to 5 V over the –40°C to +85°C temperature range. The impact
on performance over the entire temperature range is negligible as a result of the implementation of thin film
resistors and high-quality, low-temperature coefficient capacitors. The design of the THS7320 allows operation
down to 2.5 V, but it is recommended to use at least a 2.7-V supply to ensure that no issues arise with headroom
or clipping with 100% color-saturated CVBS signals. If only 75% color saturated CVBS is supported, then the
output voltage requirements are reduced to 2 VPP on the output, allowing a 2.6-V supply to be used without
issues.
A 0.1-μF capacitor should be placed as close as possible to each power-supply pin to avoid potential ringing or
oscillation. Additionally, a large capacitor (such as 4.7 μF to 100 μF) should be placed on the power-supply line
to minimize interference with 50-Hz/60-Hz line frequencies.
VIDEO INPUT VOLTAGE
The THS7320 input range allows for an input signal range from –0.06 V to approximately (VS+ – 1.5 V). However,
because of the internal fixed gain of 4 V/V (+12 dB) and the internal output level shift of 150 mV (typical), the
output is generally the limiting factor for the allowable linear input range. For example, with a 3-V supply, the
linear input range is from 0.15 V to 0.75 V. However, because of the gain and level shift, the linear output range
limits the allowable linear input range from approximately –0.03 V to 0.65 V.
20
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VIDEO INPUT OVERVOLTAGE PROTECTION
The THS7320 is built using a very high-speed, complementary, bipolar CMOS process. The internal junction
breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in
the Absolute Maximum Ratings table. All input and output device pins are protected with internal electrostatic
discharge (ESD) protection diodes to the power supplies, as shown in Figure 55.
These diodes provide moderate protection to input overdrive voltages above and below the supplies as well. The
protection diodes can typically support 30 mA of continuous current when overdriven.
+VS
External
Input/Output
Pin
Internal
Circuitry
Figure 55. Internal ESD Protection For Video Section
TYPICAL VIDEO CONFIGURATION AND VIDEO TERMINOLOGY
A typical application circuit using the THS7320 as a video buffer is shown in Figure 56. It shows a DAC or
encoder dc-coupled to the input channels of the THS7320 and the output of the THS7320 dc-coupled to the
video line. These signals can be NTSC, PAL, or SECAM signals including composite video baseband signal
(CVBS), S-Video Y'C', component Y'P'BP'R video, broadcast G'B'R' video, or computer R'G'B' video signals.
Level
Shift
3 Pole
20 MHz
75 W
x2
Channel 1
Out 1
6 dB
LPF
75 W
DAC/Encoder
R
Level
Shift
3 Pole
20 MHz
75 W
x2
Channel 2
Out 2
6 dB
LPF
75 W
R
Level
Shift
3 Pole
20 MHz
75 W
x2
Channel 3
Out 3
6 dB
LPF
75 W
R
+2.6 V to +5 V
Enable
Figure 56. Typical THS7320 Video Section with DC-Coupled Encoder/DAC and DC-Coupled Line Driving
Note that the Y’ term is used for the luma channels throughout this document rather than the more common
luminance (Y) term. This usage accounts for the definition of luminance as stipulated by the International
Commission on Illumination (CIE). Video departs from true luminance because a nonlinear term, gamma, is
added to the true RGB signals to form R’G’B’ signals. These R’G’B’ signals are then used to mathematically
create luma (Y’). Thus, luminance (Y) is not maintained, providing a difference in terminology.
This rationale is also used for the chroma (C’) term. Chroma is derived from the nonlinear R’G’B’ terms and,
thus, it is nonlinear. Chrominance (C) is derived from linear RGB, giving the difference between chroma (C’) and
chrominance (C). The color difference signals (P’B/P’R/U’/V’) are also referenced in this manner to denote the
nonlinear (gamma corrected) signals.
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R’G’B’ (commonly mislabeled RGB) is also called G’B’R’ (again commonly mislabeled as GBR) in professional
video systems. The Society of Motion Picture and Television Engineers (SMPTE) component standard stipulates
that the luma information is placed on the first channel, the blue color difference is placed on the second
channel, and the red color difference signal is placed on the third channel. This practice is consistent with the
Y'P'BP'R nomenclature. Because the luma channel (Y') carries the sync information and the green channel (G')
also carries the sync information, it makes logical sense that G' be placed first in the system. Because the blue
color difference channel (P'B) is next and the red color difference channel (P'R) is last, then it also makes logical
sense to place the B' signal on the second channel and the R' signal on the third channel, respectfully. Thus,
hardware compatibility is better achieved when using G'B'R' rather than R'G'B'. Note that for many G'B'R'
systems, sync is embedded on all three channels, but this configuration may not always be the case in all
systems.
INPUT OPERATION
The THS7320 allows for dc-coupled inputs. Most DACs or video encoders can be dc-connected to the THS7320
with essentially any DAC termination resistance desired for the system. One of the potential drawbacks to dccoupling is when 0 V is applied to the input from the DAC. Although the input of the THS7320 allows for a 0-V
input signal without issue, the output swing of a traditional amplifier cannot yield a 0-V signal that results in
possible clipping of the signal. This limitation is true for any single-supply amplifier because of the characteristics
of the output transistors. Neither CMOS nor bipolar transistors can achieve 0 V while sinking current. This
transistor characteristic is also the same reason why the highest output voltage is always less than the powersupply voltage when sourcing current.
This output clipping can reduce the sync amplitudes (both horizontal and vertical sync) on the video signal. A
problem occurs if the video signal receiver uses an automatic gain control (AGC) loop to account for losses in the
transmission line. Some video AGC circuits derive gain from the horizontal sync amplitude. If clipping occurs on
the sync amplitude, then the AGC circuit can increase the gain too much—resulting in too much luma and/or
chroma amplitude gain correction. This correction may result in a picture with an overly bright display with too
much color saturation.
Other AGC circuits may use the chroma burst amplitude for amplitude control. For this situation, reduction in the
sync signals does not alter the proper gain setting. However, it is good engineering design practice to ensure that
saturation/clipping does not take place. Transistors always take a finite amount of time to come out of saturation.
This saturation could possibly result in timing delays or other aberrations on the signals that may not be
desirable.
To eliminate saturation or clipping problems, the THS7320 has a 150-mV output level shift feature. This feature
takes the input voltage and adds an internal +37.5-mV shift to the input signal. Because of the 12-dB (4-V/V)
gain, the resulting output with a 0-V applied input signal is approximately 150 mV. The THS7320 rail-to-rail output
stage can create this output level while connected to a typical video load. This configuration ensures the sync
signal clipping or saturation does not occur. This shift is constant, regardless of the input signal. The equation for
this level shift is VOUT = (VIN × 4 V/V) + 0.15 V. For example, if a 0.5-V input is applied, the output is (0.5 V × 4
V/V) + 0.15 V = 2.15 V.
Because the internal gain is fixed at +12 dB (4 V/V), it dictates the allowable linear input voltage range. For
example, if the power supply is set to 3 V, the maximum output is approximately 2.9 V while driving a significant
amount of current. Thus, to avoid clipping, the allowable input is ([2.8 V – 0.15 V]/4) = 0.66 V. This range is valid
for up to the maximum recommended 5-V power supply that allows approximately a ([4.8 V – 0.15 V]/4) = 1.16-V
input range while avoiding clipping on the output.
22
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The input impedance of the THS7320 is dictated by the internal high-impedance gain of 2 V/V initial amplifier, as
shown in Figure 57. This buffer has a very high 2.4-MΩ || 2-pF input impedance that is effectively transparent to
the source with no interactions. Unlike other products where the filter elements are tied directly to the input pin
without buffering, there are no filter performance changes or interaction with the DAC termination resistance.
Note that the internal voltage shift does not appear at the input pin; it only shows at the output pin.
+VS
Input
Pin
Level
Shift
x2
Figure 57. Equivalent Video Section DC Input Mode Circuit
While ac-coupling with dc-biasing using external resistor dividers can be done, it is generally not recommended
because of the large resistor values required. These large resistor values coupled with the input bias current of
the THS7320 input can cause a significant voltage shift to appear on the input. If ac-coupling is necessary for a
system, several elements must be taken into account for a proper design: the high-pass corner frequency
(typically desired to be approximately 2.5 Hz); the size of the input capacitor value; the parallel input resistance
of the voltage divider; and the input bias current. Contact Texas Instruments for design support if ac-coupling is
necessary in the design.
DC-COUPLED OUTPUT
The THS7320 video section incorporates a rail-to-rail output stage that can drive the line directly without the need
for large ac-coupling capacitors. This design offers the best line tilt and field tilt (droop) performance because no
ac-coupling occurs. Keep in mind that if the input is ac-coupled, then the resulting tilt as a result of the input accoupling continues to be seen on the output, regardless of the output coupling. The 70-mA output current drive
capability of the THS7320 is designed to drive the video line while keeping the output dynamic range as wide as
possible.
One concern of dc-coupling, however, arises if the line is terminated to ground. If an ac-bias input configuration
is used or if a dc reference from the DAC is applied, such as S-Video C'/component P'B/or component P'R
signals, the output of the THS7320 then has a dc bias on the output, such as 1 V. This configuration allows a dc
current path to flow, such as 1 V/150 Ω = 6.67 mA. The result of this configuration is a slightly decreased high
output voltage swing and an increase in power dissipation of the THS7320. While the THS7320 was designed to
operate with a junction temperature of up to +125°C, care must be taken to ensure that the junction temperature
does not exceed this level or else long-term reliability could suffer. Using a 5-V supply, this configuration can
result in an additional power dissipation of (5 V – 1 V) × 6.67 mA = 26.7 mW per channel. With a 3.3-V supply,
this dissipation reduces to 15.3 mW per channel. The overall low quiescent current of the THS7320 design
minimizes potential thermal issues even when used at high ambient temperatures, but power and thermal
analysis should always be examined in any system to ensure that no issues arise. Be sure to use RMS power
and not instantaneous power when evaluating the thermal performance.
Note that the THS7320 can drive the line with dc-coupling regardless of the input mode of operation. The only
requirement is to make sure the video line has proper termination in series with the output (typically 75 Ω). This
requirement helps isolate capacitive loading effects from the THS7320 output. Failure to properly isolate
capacitive loads may result in ringing or oscillation. The stray capacitance appearing directly at the THS7320
output pins should be kept below 18 pF. One method to ensure this condition is valid is to verify that the 75-Ω
source resistor is placed next to each THS7320 output pin.
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There are many reasons dc-coupling is desirable, including reduced costs, PCB area reduction, and no line tilt or
field tilt. A common question is whether or not there are any drawbacks to using dc-coupling. There are a few
potential issues that must be examined, such as the dc current bias as discussed above. Another potential risk is
whether this configuration meets industry standards. EIA-770 stipulates that the back porch shall be 0 V ± 1 V as
measured at the receiver. With a double-terminated load system, this requirement implies a 0-V ± 2-V level at the
video amplifier output. The THS7320 can easily meet this requirement without issue. However, in Japan, the
EIAJ CP-1203 specification stipulates a 0-V ± 0.1-V level with no signal. This requirement can be met with the
THS7320 in disable mode, but while active it cannot meet this specification without output ac-coupling.
AC-COUPLED OUTPUT
A very common method of coupling the video signal to the line is with a large capacitor. This capacitor is typically
between 220 μF and 1000 μF, although 470 μF is very typical. The value of this capacitor must be large enough
to minimize the line tilt (droop) and/or field tilt associated with ac-coupling as described previously in this
document. AC-coupling is performed for several reasons, but the most common is to ensure full interoperability
with the receiving video system. This approach ensures that regardless of the reference dc voltage used on the
transmitting side, the receiving side re-establishes the dc reference voltage to its own requirements.
In the same way as the dc output mode of operation discussed previously, each line should have a 75-Ω source
termination resistor in series with the ac-coupling capacitor. This 75-Ω series resistor should be placed next to
the THS7320 output to minimize capacitive loading effects.
Because of the edge rates and frequencies of operation, it is recommended (but not required) to place a 0.1-μF
to 0.01-μF capacitor in parallel with the large 220-μF to 1000-μF capacitor. These large value capacitors are
generally aluminum electrolytic. It is well-known that these capacitors have significantly large equivalent series
resistance (ESR), and the impedance at high frequencies is rather large as a result of the associated
inductances involved with the leads and construction. The small 0.1-μF to 0.01-μF capacitors help pass these
high-frequency signals (greater than 1 MHz) with much lower impedance than the large capacitors.
Although it is common to use the same capacitor values for all the video lines, the frequency bandwidth of the
chroma signal in an S-Video system is not required to perform at as low (or as high) a frequency as the luma
channels. Thus, the capacitor values of the chroma line(s) can be smaller, such as 0.1 μF.
Figure 58 shows a typical configuration where the input is dc-coupled and the output is also ac-coupled. ACcoupled inputs are generally required when current-sink DACs are used or the input is connected to an unknown
source, such as when the THS7320 is used as an input device.
Level
Shift
3 Pole
20 MHz
75 W
x2
Channel 1
330 mF
Out 1
6 dB
LPF
75 W
DAC/Encoder
R
Level
Shift
3 Pole
20 MHz
75 W
x2
Channel 2
330 mF
Out 2
6 dB
LPF
75 W
R
Level
Shift
3 Pole
20 MHz
75 W
x2
Channel 3
330 mF
Out 3
6 dB
LPF
75 W
R
+2.6 V to +5 V
Enable
Figure 58. Typical DC Input System Driving AC-Coupled Video Lines
24
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LOW-PASS FILTER
Each channel of the THS7320 video section incorporates a third-order, low-pass filter. These video
reconstruction filters minimize DAC images from being passed on to the video receiver. Depending on the
receiver design, failure to eliminate these DAC images can cause picture quality problems as a result of aliasing
of the ADC in the receiver. Another benefit of the filter is to smooth out aberrations in the signal that DACs
typically have associated with the digital stepping of the signal. This benefit helps with picture quality and
ensures that the signal meets video bandwidth requirements.
Each filter has an associated Butterworth characteristic. The benefit of the Butterworth response is that the
frequency response is flat with a relatively steep initial attenuation at the corner frequency. The concern with the
Butterworth characteristic is that the group delay rises near the corner frequency. Group delay is defined as the
change in phase (radians/second) divided by a change in frequency. An increase in group delay corresponds to
a time domain pulse response that has overshoot and some possible ringing associated with the overshoot.
The use of other type of filters, such as elliptic or Chebyshev, is not recommended for video applications
because of the very large group delay variations near the corner frequency resulting in significant overshoot and
ringing. While these filters may help meet the video standard specifications with respect to amplitude attenuation,
the group delay is well beyond the standard specifications. Considering this group delay with the fact that video
can go from a white pixel to a black pixel over and over again, it is easy to see that ringing can occur. Ringing
typically causes a display to have ghosting or fuzziness appear on the edges of a sharp transition. On the other
hand, a Bessel filter has ideal group delay response, but the rate of attenuation is typically too low for acceptable
image rejection. Thus, the Butterworth filter is an acceptable compromise for both attenuation and group delay.
The THS7320 filters have a nominal corner (–3-dB) frequency at 20 MHz and a –1-dB passband typically at
17 MHz. This 20-MHz filter is ideal for enhanced definition (ED) NTSC or PAL 480p/576p Y’P’BP’R or
G'B'R'/R'G'B' signals. For oversampled systems, the THS7320 works well for passing standard definition (SD)
NTSC, PAL, or SECAM composite video (CVBS), S-Video signals (Y’C’), 480i/576i Y’P’BP’R, Y’U’V’, broadcast
G’B’R’ signals, and R'G'B' video signals. The 20-MHz, –3-dB corner frequency was designed to achieve 27-dB of
attenuation at 54 MHz—a common sampling frequency between the DAC/ADC second and third Nyquist zones
found in many video systems. This consideration is important because any signal that appears around this
frequency can also appear in the baseband as a result of aliasing effects of an ADC found in a receiver. Another
specification ensured for the THS7320 is attenuation at 43 MHz. This frequency is derived from the fact that the
ED Y' signal has an 11-MHz bandwidth. Following standard sampling theory, this means that the second Nyquist
zone image starts at 54 MHz – 11 MHz = 43 MHz.
Keep in mind that images do not stop at the DAC sampling frequency, fS (for example, 54 MHz for traditional ED
DACs); they continue around the sampling frequency harmonics of 2 × fS, 3 × fS, 4 × fS, and so on (that is,
108 MHz, 162 MHz, 216 MHz, etc.). Because of these multiple images, an ADC can fold down into the baseband
signal, meaning that the low-pass filter must also eliminate these higher-order images. The THS7320 filters are
designed to attenuate all of these higher frequencies without bounce effect that some filters can allow.
The filter frequencies were chosen to account for process variations in the THS7320. To ensure the required
video frequencies are effectively passed, the filter corner frequency must be high enough to allow component
variations. The other consideration is that the attenuation must be large enough to ensure the antialiasing/reconstruction filtering is sufficient to meet the system demands. Thus, the recommendations for the filter
frequencies was not arbitrarily selected and is a good compromise that should meet the demands of most
systems.
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BENEFITS OVER PASSIVE FILTERING
Two key benefits of using an integrated filter system (such as the THS7320) over a passive system are PCB
area and filter variations. The ultra-small MicrostarCSP 9-ball package is much smaller over a passive RLC
network, especially a three-pole passive network for three channels. Additionally, consider that inductors have at
best ±10% tolerances (normally, ±15% to ±20% is common) and capacitors typically have ±10% tolerances. A
Monte
Carlo
analysis
shows
that
the
filter
corner
frequency
(–3
dB),
flatness
(–1 dB), Q-factor (or peaking), and channel-to-channel delay have wide variations. These variances can lead to
potential performance and quality issues in mass-production environments. The THS7320 solves most of these
problems with the corner frequency being essentially the only variable.
Another concern about passive filters is the use of inductors. Inductors are magnetic components, and are
therefore susceptible to electromagnetic coupling/interference (EMC/EMI). Some common coupling can occur
because of other video channels nearby using inductors for filtering, or it can come from nearby switched-mode
power supplies. Some other forms of coupling could be from outside sources with strong EMI radiation and can
cause failure in EMC testing such as required for CE compliance.
One concern about an active filter in an integrated circuit is the variation of the filter characteristics when the
ambient temperature and the subsequent die temperature change. To minimize temperature effects, the
THS7320 uses low-temperature coefficient resistors and high-quality, low-temperature coefficient capacitors
found in the BiCom3X process. These filters have been specified by design to account for process variations and
temperature variations to maintain proper filter characteristics. This approach maintains a low channel-to-channel
time delay that is required for proper video signal performance.
Another benefit of the THS7320 over a passive RLC filter are the input and output impedances. With a passive
filter, the input impedance presented to the DAC varies significantly, from 35 Ω to over 1.5 kΩ, and may cause
voltage variations over frequency. The THS7320 input impedance is 2.4 MΩ, and only the 2-pF input capacitance
plus the PCB trace capacitance impact the input impedance. As such, the voltage variation appearing at the DAC
output is better controlled with a fixed termination resistor and the high input impedance buffer of the THS7320.
On the output side of the filter, a passive filter again has a large impedance variation over frequency. The EIA770
specifications require the return loss to be at least 25 dB over the video frequency range of use. For a video
system, this requirement implies that the source impedance (which includes the source, series resistor, and the
filter) must be better than 75 Ω, +9 Ω/–8 Ω. The THS7320 is an operational amplifier that approximates an ideal
voltage source, which is desirable because the output impedance is very low and can source and sink current.
To properly match the transmission line characteristic impedance of a video line, a 75-Ω series resistor is placed
on the output. To minimize reflections and to maintain a good return loss meeting EIA specifications, this output
impedance must maintain a 75-Ω impedance. A wide impedance variation of a passive filter cannot ensure this
level of performance. On the other hand, the THS7320 has approximately 1.4 Ω of output impedance, or a return
loss of 41 dB, at 11 MHz. Thus, the system is matched significantly better with a THS7320 compared to a
passive filter.
One final benefit of the THS7320 over a passive filter is power dissipation. A DAC driving a video line must be
able to drive a 37.5-Ω load: the receiver 75-Ω resistor and the 75-Ω impedance matching resistor next to the
DAC to maintain the source impedance requirement. This requirement forces the DAC to drive at least 1.25 VP
(100% saturation CVBS)/37.5 Ω = 33.3 mA. A DAC is a current-steering element, and this amount of current
flows internally to the DAC even if the output is 0 V. Thus, power dissipation in the DAC may be very high,
especially when three channels are being driven.
Using the THS7320 with a high input impedance can reduce DAC power dissipation significantly. This outcome is
possible because the resistance that the DAC drives can be substantially increased. It is common to set this
resistance in a DAC by a current-setting resistor on the DAC itself. Thus, the resistance can be 300 Ω or more,
substantially reducing the current drive demands from the DAC and saving significant amounts of power. For
example, a 3.3-V, three-channel DAC dissipates 330 mW alone for the steering current capability (three channels
× 33.3 mA × 3.3 V) if it must drive a 37.5-Ω load. With a 300-Ω load, the DAC power dissipation as a result of
current steering current would only be 41 mW (three channels × 4.16 mA × 3.3 V), or over eight times lower
power. For overall system power, this scenario must also account for the THS7320 power. The THS7320 only
consumes 3.4-mA total quiescent current. The quiescent power added is then 3.3 V × 3.4 mA = 11.2 mW. The
total system power is then 41 mW + 11 mW = 52 mW, or a factor of six times lower power compared to the DAC
driving the line directly. Saving power by adding the THS7320 in a system is easy to see and accomplish, not to
mention that it incorporates the added benefit of a three-pole filter on each channel.
26
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SBOS565B – JULY 2011 – REVISED SEPTEMBER 2012
EVALUATION MODULE
To evaluate the THS7320, an evaluation module (EVM) is available. The EVM allows dc-coupled input and
output configurations. Inputs and outputs include BNC connectors commonly found in video systems along with
75-Ω effective input termination resistors, 75-Ω series source termination resistors, and 75-Ω characteristic
impedance traces. This EVM is designed to be used with a single supply from 2.6 V up to 5 V.
The EVM input configuration sets all channels for dc input coupling. The input signal must be within 0 V to
approximately 0.75 V for proper operation. Failure to be within this range saturates and/or clips the output signal.
Refer to the Application Information section for further information.
The THS7320 incorporates an easy method to configure the enable mode. JP1 controls the enable feature.
Connecting JP1 to GND applies 0 V to the enable pin and the THS7320 is placed into shutdown mode
consuming nominally 0.15 μA of quiescent current. Moving JP1 to +VS causes the THS7320 to be in normal
operation mode where the quiescent current should be nominally 3.4 mA for the entire EVM. This quiescent
current is with no load or no signal applied on the input. Adding a load or input signal causes the quiescent
current to vary accordingly.
An example procedure to confirm proper device operation with standard lab equipment is described in the
following sections.
REQUIRED EQUIPMENT
•
•
•
•
•
•
One dc power supply: +3.0 V, 50-mA output (minimum) is recommended
One dc current meter: resolution to 1 mA, capable of maximum current the dc power supply can supply
Function or arbitrary waveform generator
Oscilloscope: 50-MHz bandwidth (minimum) is recommended
Banana-to-banana patch cords
BNC test cables
BASIC SETUP
1.
2.
3.
4.
5.
6.
Set the dc power supply to +3.0 V. Set the current limit on the dc power supply to 50 mA.
Connect the positive (+) terminal of the power supply to the positive (+) terminal of the current meter.
Connect the negative (–) terminal of the current meter to the VS+ terminal of the EVM (J7).
Connect the common ground terminal of the power supply to the ground (GND) terminal on the EVM (J8).
Connect the output of the waveform generator to the channel 1 input on the EVM (J1)
Connect the probe ground to the GND of the EVM.
TESTING THE EVM
The EVM can be tested by following these steps:
1. Enable the 3.0-VDC power supply.
2. Verify that the current meter is reading nominally 3.5 mA (2.7 mA to 4.7 mA, minimum and maximum).
3. Set the function generator such that a 1-MHz, 0.5-VPP sine wave (with an 0.40-VDC offset) appears on the
THS7320 input pin. The function generator ac and dc levels may have to be adjusted to ensure the proper
voltage appears on the THS7320 input pins because most function generators have a 50-Ω source
impedance and the THS7320 incorporates a double 37.4-Ω resistor termination divider scheme for a total 75Ω termination.
4. Probe the device side of R12, which is connected to the THS7320 channel 1 output pin.
5. Verify that the oscilloscope displays the THS7320 channel 1 output voltage amplitude as 2.0 VPP ±0.1 V with
a nominal 1.75-VDC offset.
6. Repeat steps 3 through 5 for channels 2 and 3.
7. When confirmed, turn off the function generator and power supply.
8. Note that if video equipment is used with the THS7320EVM, the proper input and output 75-Ω terminations
already exist on the EVM along with the proper input voltage divider. This functionality makes the EVM very
easy to test video signals with no modifications to the EVM.
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+
Figure 59 shows the EVM schematic. Figure 60 through Figure 63 illustrate the layers of the EVM PCB,
incorporating standard high-speed layout practices. Table 5 lists the bill of materials as the board comes supplied
from Texas Instruments.
+
+
+
Figure 59. THS7320 EVM Schematic
28
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SBOS565B – JULY 2011 – REVISED SEPTEMBER 2012
Figure 60. THS7320 EVM PCB Top Layer
Figure 61. THS7320 EVM PCB Layer 2
Figure 62. THS7320 EVM PCB Layer 3
Figure 63. THS7320 EVM PCB Bottom Layer
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THS7320IYHC EVM Bill of Materials
Table 5. THS7320 EVM
ITEM
REF DES
QTY
DESCRIPTION
1
FB1
1
Bead, ferrite, 2.5 A, 330 Ω
2
C6
1
Capacitor, 4.7 µF, tantalum, 35V, 10%, low ESR
3
CX1-CX3
3
Open
4
C5
1
5
C7
6
MANUFACTURER
PART NUMBER
SMD SIZE
0805
DISTRIBUTOR
PART NUMBER
(TDK) MPZ2012S331A
(Digi-Key) 445-1569-1-ND
(AVX) TPSC475K035R0600
(Digi-Key) 478-1772-1-ND
0805
—
—
Capacitor, 0.1 µF, ceramic, 16V, X7R
0402
(TDK) C1005X7R1C104K
(Digi-Key) 445-4952-1-ND
1
Capacitor, 0.1 µF, ceramic, 16V, X7R
0603
(AVX) 0603YC104KAT2A
(Digi-Key) 478-1239-1-ND
C1
1
Capacitor, 0.1 µF, ceramic, 50V, X7R
0805
(AVX) 08055C104KAT2A
(Digi-Key) 478-1395-1-ND
7
C2-C4
3
Capacitor, aluminum, 470 µF, 10V, 20%
(Panasonic) EEE-FP1A471AP
(Digi-Key) PCE4526CTND
8
R1-R3, R11,
RX1-RX3
7
Open
0805
—
—
9
Z1-Z3
3
Resistor, 0 Ω, 1/8W
0805
(ROHM) MCR10EZPJ000
(Digi-Key) RHM0.0ARCTND
10
R4-R9
6
Resistor, 37.4 Ω, 1/8W, 1%
0805
(ROHM) MCR10EZHF37R4
(Digi-Key) RHM37.4CCTND
11
R12-R14
3
Resistor, 75 Ω, 1/8W, 1%
0805
(ROHM) MCR10EZHF75.0
(Digi-Key) RHM75.0CCTND
12
R10
1
Resistor, 1 kΩ, 1/8W, 1%
0805
(ROHM) MCR10EZHF1001
(Digi-Key) RHM1.00KCCTND
13
J7, J8
2
Jack, banana receptance, 0.25" dia. hole
—
(SPC) 15459
(Newark) 79K5034
14
J1-J6
6
Connector, BNC, jack, 75 Ω
—
(Amphenol) 31-5329-72RFX
(Newark) 93F7554
15
JP1
1
Header, 0.1" CTRS, 0.025" sq. pins
3 POS.
(Sullins) PBC36SAAN
(Digi-Key) S1011E-36-ND
16
JP1
1
Shunts
—
(Sullins) SSC02SYAN
(Digi-Key) S9002-ND
17
U1
1
IC, THS7320
(TI) THS7320IYHC
—
18
—
4
Standoff, 4-40 HEX, 0.625" length
—
(Keystone) 1808
(Digi-Key) 1808K-ND
19
—
4
Screw, Phillips, 4-40, 0.250"
—
PMSSS 440 0025 PH
(Digi-Key) H703-ND
20
—
1
Board, printed circuit
—
EDGE # 6522214 REV.A
—
C
F
YHC
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2012) to Revision B
•
Added the Required Equipment, Basic Setup, and Testing the EVM sections .................................................................. 27
Changes from Original (July 2011) to Revision A
•
30
Page
Page
Added THS7320IYHCT row to Package/Ordering Information table .................................................................................... 2
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PACKAGE OPTION ADDENDUM
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10-Oct-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
THS7320IYHCR
ACTIVE
DSBGA
YHC
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
THS7320IYHCT
ACTIVE
DSBGA
YHC
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
THS7320IYHCR
DSBGA
YHC
9
3000
180.0
8.4
THS7320IYHCT
DSBGA
YHC
9
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.06
1.06
0.56
4.0
8.0
Q1
1.06
1.06
0.56
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS7320IYHCR
DSBGA
YHC
9
3000
210.0
185.0
35.0
THS7320IYHCT
DSBGA
YHC
9
250
210.0
185.0
35.0
Pack Materials-Page 2
D: Max = 0.99 mm, Min = 0.93 mm
E: Max = 0.99 mm, Min = 0.93 mm
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