TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 10-W STEREO CLASS-D AUDIO POWER AMPLIFIER FEATURES APPLICATIONS • 10-W/Ch (stereo SE) into an 8-Ω Load From a 24-V Supply • 20-W/Ch (mono BTL) into an 8-Ω Load from a 24-V Supply • Operates From 10 V to 26 V • Operates From +24 V LCD Backlight Supply • Efficient Class-D Operation Eliminates Need for Heat Sinks • Four Selectable, Fixed-Gain Settings • Single-Ended Analog Inputs • Thermal and Short-Circuit Protection With Auto Recovery • 20-Pin DIP Package • Advanced Power-Off Pop Reduction • • • • 1 234 Flat Panel Televisions DLP® TVs CRT TVs Powered Speakers DESCRIPTION The TPA3125D2 is a 10-W (per channel), efficient, class-D audio power amplifier for driving stereo speakers in a single-ended configuration; or, a mono speaker in a bridge-tied-load configuration. The TPA3125D2 can drive stereo speakers as low as 4 Ω. The efficiency of the TPA3125D2 eliminates the need for an external heat sink when playing music. The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26, 32, and 36 dB. The patented start-up and shutdown sequences minimize pop noise in the speakers without additional circuitry. The thru-hole package allows single-sided printed circuit boards. placement on SIMPLIFIED APPLICATION CIRCUIT TPA3125D2 1 mF 0.22 mF Left Channel LIN BSR Right Channel RIN ROUT 1 mF 33 mH 0.22 mF PGNDR PGNDL 1 mF BYPASS AGND 470 mF 0.22 mF LOUT 33 mH BSL 470 mF 0.22 mF 10 V to 26 V AVCC 10 V to 26 V PVCCL PVCCR VCLAMP Shutdown Control Mute Control 1 mF SD MUTE GAIN0 4-Step Gain Control GAIN1 S0267-02 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DLP is a registered trademark of Texas Instruments. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DUAL INLINE PACKAGE (TOP VIEW) PVCCL SD MUTE LIN RIN BYPASS AGND AGND VCLAMP PVCCR 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR Table 1. TERMINAL FUNCTIONS TERMINAL NAME 20-PIN (DIP) I/O DESCRIPTION PVCCL 1 Power supply for left channel H-bridge. SD 2 I Shutdown signal for IC (low = outputs disabled, high = operational). TTL logic levels with compliance to AVCC. MUTE 3 I Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle; low = outputs enabled). TTL logic levels with compliance to AVCC. LIN 4 I Audio input for left channel. RIN 5 I Audio input for right channel. BYPASS 6 O Reference for pre-amplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via external capacitor sizing. AGND 7 Analog ground for digital/analog cells in core. AGND 8 Analog ground for digital/analog cells in core. VCLAMP 9 Internally generated voltage supply for bootstrap capacitors. PVCCR 10 Power supply for right channel H-bridge. PGNDR 11 Power ground for right channel H-bridge. ROUT 12 O Class-D H-bridge negative output for right channel. BSR 13 I Bootstrap input for right channel. GAIN1 14 I Gain select most significant bit. TTL logic levels with compliance to AVCC. GAIN0 15 I Gain select least significant bit. TTL logic levels with compliance to AVCC. AVCC 16, 17 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL . BSL 18 I Bootstrap input for left channel. LOUT 19 O Class-D H-bridge positive output for left channel. PGNDL 20 2 Power ground for left channel H-bridge. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VCC (1) Supply voltage AVCC, PVCC Logic input voltage SD, MUTE, GAIN0, GAIN1 Analog input voltage RIN, LIN Continuous total power dissipation VALUE UNIT –0.3 to 30 V –0.3 to VCC + 0.3 V –0.3 to 7 V See Dissipation Rating Table TA Operating free-air temperature range –40 to 85 °C TJ Operating junction temperature range –40 to 150 °C Tstg Storage temperature range –65 to 150 °C ZL Load impedance (minimum value) ESD Electrostatic Discharge (1) SE Output Configuration 3.2 BTL Output Configuration 6 Human body model (all pins) ±2 kV ±500 V Charged-device model (all pins) Ω Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (1) PACKAGE (1) TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C 20-pin DIP 1.87 W 15 mW/°C 1.20 W 0.97 W For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. RECOMMENDED OPERATING CONDITIONS MIN MAX 10 26 UNIT VCC Supply voltage PVCC, AVCC VIH High-level input voltage SD, MUTE, GAIN0, GAIN1 VIL Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 V IIH High-level input current SD, MUTE, GAIN0, GAIN1; VIN = VCC = 26 V 125 µA IIL Low-level input current SD, MUTE, GAIN0, GAIN1; VIN = 0, VCC = 26 V 1 µA TA Operating free-air temperature 85 °C 2 –40 V Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 V 3 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com DC CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 7.5 50 mV 30 mA | VOS | Class-D output offset voltage (measured differentially in BTL mode as shown in Figure 33) VI = 0 V, AV = 36 dB V(BYPASS) Bypass output voltage No load ICC(q) Quiescent supply current SD = 2 V, MUTE = 0 V, no load 16 ICC(q) Quiescent supply current in mute mode MUTE = 0.8 V, no load 16 ICC(q) Quiescent supply current in shutdown mode SD = 0.8 V, no load rDS(on) Drain-source on-state resistance AVCC/8 GAIN1 = 0.8 V G Gain GAIN = 2 V Mute attenuation V mA 0.39 1 mA 210 450 mΩ GAIN0 = 0.8 V 18 20 22 GAIN0 = 2 V 24 26 28 GAIN0 = 0.8 V 30 32 34 GAIN0 = 2 V 34 36 38 VI = 1 Vrms UNIT –80 dB dB AC CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply ripple rejection VCC = 24, Vripple = 0.2 VPP, Gain = 20 dB, freq = 1 kHz Output power at 1% THD+N VCC = 24 V, f = 1 kHz; single-ended output 8 Output power at 10% THD+N VCC = 24 V, f = 1 kHz; single-ended output 10 Output power at 1% THD+N VCC = 12 V, f = 1 kHz; bridge-tied output 7 Output power at 10% THD+N VCC = 12 V, f = 1 kHz; bridge-tied output 9 Output power at 1% THD+N VCC = 24 V, f = 1 kHz; bridge-tied output (output thermally limited to 20W unless heatsink is used) 30 Output power at 10% THD+N VCC = 24 V, f = 1 kHz; bridge-tied output (output thermally limited to 20W unless heatsink is used) 36 THD+N Total harmonic distortion + noise f = 1 kHz, PO = 5 W; single-ended output 0.04% THD+N Total harmonic distortion + noise f = 1 kHz, PO = 10 W; bridge-tied output 0.04% Vn Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB 125 µV RMS –78 dBV Crosstalk PO = 1 W, f = 1 kHz; gain = 20 dB –70 dB Signal-to-noise ratio Max output at THD+N < 1%, f = 1 kHz, gain = 20 dB –92 dB 150 °C kSVR PO SNR –52 W Thermal trip point Thermal hysteresis fOSC 4 dB 30 Oscillator frequency 250 300 °C 350 kHz Mute delay Time from mute input switches high until outputs muted 30 µs Unmute delay Time from mute input switches low until outputs unmuted 120 ms Start-up time Bypass capacitor on pin 6 = 1µF 500 ms Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 FUNCTIONAL BLOCK DIAGRAM BSL AVCC PVCCL AVDD REGULATOR HS + – LOUT VCLAMP LS AVDD AVDD PGNDL LIN SC DETECT AVDD/2 AGND CONTROL BIAS THERMAL SD MUTE VCLAMP MUTE CONTROL OSC/RAMP BYPASS GAIN1 GAIN0 BYPASS AV CONTROL SC DETECT BSR PVCCR HS – + ROUT VCLAMP LS PGNDR AVDD AVDD RIN AVDD/2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 5 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS All tests are conducted at frequency = 1 kHz unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 VCC = 12 V RL = 4 Ω (SE) Gain = 20 dB THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 10 1 PO = 2.5 W PO = 1 W 0.1 0.01 0.001 20 PO = 0.5 W 100 1k VCC = 18 V RL = 6 Ω (SE) Gain = 20 dB 1 PO = 2.5 W PO = 1 W 0.1 0.01 PO = 0.5 W 0.001 20 10k 20k 100 1k f − Frequency − Hz 10k 20k f − Frequency − Hz G001 G002 Figure 1. Figure 2. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 VCC = 18 V RL = 8 Ω (SE) Gain = 20 dB THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 10 1 PO = 2.5 W 0.1 0.01 PO = 1 W 0.001 20 100 1k 10k 20k VCC = 24 V RL = 8 Ω (SE) Gain = 20 dB 1 PO = 5 W PO = 2.5 W 0.1 0.01 PO = 1 W 0.001 20 f − Frequency − Hz 100 1k G003 Figure 3. 6 10k 20k f − Frequency − Hz G004 Figure 4. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) All tests are conducted at frequency = 1 kHz unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 RL = 4 Ω (SE) Gain = 20 dB THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 10 1 VCC = 12 V 0.1 0.01 0.001 0.01 0.1 1 10 PO − Output Power − W 1 VCC = 12 V 0.1 0.01 VCC = 18 V 0.001 0.01 40 0.1 1 10 40 PO − Output Power − W G005 Figure 5. Figure 6. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER CROSSTALK vs FREQUENCY G006 −20 10 RL = 8 Ω (SE) Gain = 20 dB −30 VCC = 12 V RL = 4 Ω (SE) PO = 0.25 W Gain = 20 dB −40 1 VCC = 18 V 0.1 Crosstalk − dB THD+N − Total Harmonic Distortion + Noise − % RL = 6 Ω (SE) Gain = 20 dB VCC = 12 V −50 −60 Right to Left −70 Left to Right −80 0.01 VCC = 24 V −90 0.001 0.01 0.1 1 PO − Output Power − W 10 40 −100 20 100 1k 10k 20k f − Frequency − Hz G008 G007 Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 7 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All tests are conducted at frequency = 1 kHz unless otherwise noted. CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY −20 −20 VCC = 18 V VO = 1 Vrms RL = 8 Ω (SE) PO = 0.125 W Gain = 20 dB −30 −40 −50 Crosstalk − dB −60 Right to Left −70 Left to Right −80 −50 −60 Right to Left −70 Left to Right −80 −90 −90 −100 20 100 1k −100 20 10k 20k 100 f − Frequency − Hz 1k 10k 20k f − Frequency − Hz G009 Figure 10. GAIN/PHASE vs FREQUENCY GAIN/PHASE vs FREQUENCY 600 VCC = 24 V RL = 4 Ω (SE) Gain = 20 dB Lfilt = 22 µH Cfilt = 0.68 µF Cdc = 1000 µF 30 Gain − dB 25 500 35 400 30 300 25 Gain 20 200 Phase 15 10 5 0 20 100 1k 10k 600 40 Phase − ° Gain − dB 40 35 G010 Figure 9. VCC = 24 V RL = 8 Ω (SE) Gain = 20 dB Lfilt = 33 µH Cfilt = 0.22 µF Cdc = 470 µF 500 400 300 Gain 20 100 15 0 10 −100 5 −200 100k 0 200 Phase 100 0 −100 20 100 f − Frequency − Hz 1k 10k −200 100k f − Frequency − Hz G011 Peaking of frequencies above 10 kHz is due to reconstruction filter, not the device. Figure 11. 8 Phase − ° Crosstalk − dB −40 VCC = 24 V VO = 1 Vrms RL = 8 Ω (SE) PO = 0.125 W Gain = 20 dB −30 G012 Peaking of frequencies above 10 kHz is due to reconstruction filter, not the device. Figure 12. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) All tests are conducted at frequency = 1 kHz unless otherwise noted. OUTPUT POWER vs SUPPLY VOLTAGE 22 OUTPUT POWER vs SUPPLY VOLTAGE 14 RL = 4 Ω (SE) Gain = 20 dB 20 12 18 16 PO − Output Power − W PO − Output Power − W RL = 8 Ω (SE) Gain = 20 dB 14 12 THD+N = 10% 10 8 THD+N = 1% 6 10 8 THD+N = 10% 6 THD+N = 1% 4 4 2 2 0 0 10 12 14 16 18 20 22 24 26 VCC − Supply Voltage − V 10 12 14 G013 A dashed line represents thermally limited region. Figure 13. 20 22 24 26 G014 EFFICIENCY vs OUTPUT POWER 100 100 90 90 80 80 VCC = 18 V VCC = 24 V 70 VCC = 12 V Efficiency − % Efficiency − % 18 A dashed line represents thermally limited region. Figure 14. EFFICIENCY vs OUTPUT POWER 70 16 VCC − Supply Voltage − V 60 50 40 60 50 40 30 30 20 20 RL = 4 Ω (SE) Gain = 20 dB 10 RL = 8 Ω (SE) Gain = 20 dB 10 0 0 0 1 2 3 4 5 PO − Output Power − W 6 7 0 G015 Figure 15. 2 4 6 8 10 PO − Output Power − W 12 G016 Figure 16. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 9 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All tests are conducted at frequency = 1 kHz unless otherwise noted. SUPPLY CURRENT vs OUTPUT POWER (PER CHANNEL) 1.5 SUPPLY CURRENT vs OUTPUT POWER (PER CHANNEL) 1.2 RL = 4 Ω (SE) Gain = 20 dB 1.0 ICC − Supply Current − A 1.2 ICC − Supply Current − A RL = 8 Ω (SE) Gain = 20 dB 0.9 VCC = 12 V 0.6 0.3 0.8 0.6 VCC = 24 V 0.4 VCC = 18 V 0.2 0.0 0.0 0 3 6 9 12 15 PO − Output Power (Per Channel) − W 0 5 G017 A dashed line represents thermally limited region. Figure 17. Power Supply Rejection Ratio − dB Power Supply Rejection Ratio − dB −10 −40 −50 −60 −70 −80 −90 G018 −20 VCC = 24 V VO(ripple) = 0.2 VPP RL = 8 Ω (SE) Gain = 20 dB −30 −40 −50 −60 −70 −80 −90 100 1k 10k 20k −100 20 f − Frequency − Hz 100 1k 10k 20k f − Frequency − Hz G019 Figure 19. 10 25 0 VCC = 24 V VO(ripple) = 0.2 VPP RL = 4 Ω (SE) Gain = 20 dB −30 −100 20 20 POWER SUPPLY REJECTION RATIO vs FREQUENCY - SE 0 −20 15 A dashed line represents thermally limited region. Figure 18. POWER SUPPLY REJECTION RATIO vs FREQUENCY −10 10 PO − Output Power (Per Channel) − W G025 Figure 20. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 TYPICAL CHARACTERISTICS (continued) All tests are conducted at frequency = 1 kHz unless otherwise noted. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 VCC = 24 V RL = 8 Ω (BTL) Gain = 20 dB THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 10 1 PO = 20 W PO = 1 W 0.1 0.01 PO = 5 W 0.001 20 100 1k RL = 8 Ω (BTL) Gain = 20 dB 1 VCC = 12 V VCC = 18 V 0.1 0.01 VCC = 24 V 0.001 0.01 10k 20k 0.1 f − Frequency − Hz G020 50 OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs OUTPUT POWER 40 G021 100 90 80 35 70 Efficiency − % PO − Output Power − W Figure 22. 40 30 THD+N = 10% 25 10 Figure 21. RL = 8 Ω (BTL) Gain = 20 dB 45 1 PO − Output Power − W 20 THD+N = 1% 15 VCC = 24 V 60 50 40 30 10 20 5 10 0 RL = 8 Ω (BTL) Gain = 20 dB 0 10 12 14 16 18 20 22 24 VCC − Supply Voltage − V 26 0 G023 A dashed line represents thermally limited region. Figure 23. 2 4 6 8 10 PO − Output Power − W Product Folder Link(s): TPA3125D2 G024 Figure 24. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated 12 11 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) All tests are conducted at frequency = 1 kHz unless otherwise noted. POWER SUPPLY REJECTION RATIO vs FREQUENCY - BTL 0 Power Supply Rejection Ratio − dB −10 −20 VCC = 24 V VO(ripple) = 0.2 VPP RL = 8 Ω (BTL) Gain = 20 dB −30 −40 −50 −60 −70 −80 −90 −100 20 100 1k 10k 20k f − Frequency − Hz G026 Figure 25. 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 APPLICATION INFORMATION CLASS-D OPERATION This section focuses on the class-D operation of the TPA3125D2. Traditional Class-D Modulation Scheme The TPA3125D2 operates in AD mode. There are two main configurations that may be used. For stereo operation, the TPA3125D2 should be configured in a single-ended (SE) half-bridge amplifier. For mono applications, TPA3125D2 may be used as a bridge-tied-load (BTL) amplifier. The traditional class-D modulation scheme, which is used in the TPA3125D2 BTL configuration, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The class-D modulation scheme with voltage and current waveforms is shown in Figure 26. +VCC 0V Output Current Figure 26. Class-D Modulation for TPA3125D2 SE Configuration Supply Pumping One issue encountered in single-ended (SE) class-D amplifier designs is supply pumping. Power-supply pumping is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-D amplifier. This phenomenon is most evident at low audio frequencies and when both channels are operating at the same frequency and phase. At low levels, power-supply pumping results in distortion in the audio output due to fluctuations in supply voltage. At higher levels, pumping can cause the overvoltage protection to operate, which temporarily shuts down the audio output. Several things can be done to relieve power-supply pumping. The lowest impact is to operate the two inputs out of phase 180° and reverse the speaker connections. Because most audio is highly correlated, this causes the supply pumping to be out of phase and not as severe. If this is not enough, the amount of bulk capacitance on the supply must be increased. Also, improvement is realized by hooking other supplies to this node, thereby, sinking some of the excess current. Power-supply pumping should be tested by operating the amplifier at low frequencies and high output levels. Gain Setting via GAIN0 and GAIN1 Inputs The gain of the TPA3125D2 is set by two input terminals, GAIN0 and GAIN1. The gains listed in Table 2 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 8 kΩ, which is the absolute minimum input impedance of the TPA3125D2. At the higher gain settings, the input impedance could increase as high as 72 kΩ. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 13 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com Table 2. Gain Setting GAIN1 GAIN0 AMPLIFIER GAIN (dB), TYPICAL INPUT IMPEDANCE (kΩ), TYPICAL 0 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9 INPUT RESISTANCE Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3-dB cutoff frequency will change when changing gain steps. Zf Ci IN Input Signal Zi The –3-dB frequency can be calculated using Equation 1. Use the ZI values given in Table 2. f = 1 2p Zi Ci (1) INPUT CAPACITOR, Ci In the typical application, input capacitor Ci is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case Ci and the input impedance of the amplifier (Zi) form a high-pass filter with the corner frequency determined in Equation 2. –3 dB fc = 1 2p Zi Ci fc (2) The value of Ci is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where (Zi is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is reconfigured as Equation 3. Ci = 1 2p Zi fc (3) In this example, Ci is 0.4 µF; so, one would likely choose a value of 0.47 µF as this value is commonly used. If the gain is known and is constant, use Zi from Table 2 to calculate Ci. A further consideration for this capacitor is the leakage path from the input source through the input network, Ci, and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 in high-gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at AVCC/8 volts, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages due to leakage, so it is important to ensure that boards are cleaned properly. Single-Ended Output Capacitor, CO In single-ended (SE) applications, the dc blocking capacitor forms a high-pass filter with the speaker impedance. The frequency response rolls off with decreasing frequency at a rate of 20 dB/decade. The cutoff frequency is determined by fc = 1 2p COZi (4) Table 3 shows some common component values and the associated cutoff frequencies: Table 3. Common Filter Responses Speaker Impedance (Ω) Co - DC Blocking Capacitor (µF) fc = 60 Hz (–3 dB) fc = 40 Hz (–3 dB) fc = 20 Hz (–3 dB) 4 680 1000 2200 6 470 680 1500 8 330 470 1000 Bleeder Resistor for Single-Ended Output Capacitor The single-ended application schematic shows a 4.7 kΩ resistor from the IC side of the single-ended output capacitor to ground. This resistor is used to bleed the charge off of the capacitor when the amp is powered down, preventing pop if the amp is power back up quickly. The value of the resistor can be adjusted to control the time required to discharge the capacitor. The discharge time is proportional to the RC time constant of the resistor and capacitor. Output Filter and Frequency Response For the best frequency response, a flat-passband output filter (second-order Butterworth) may be used. The output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins. There are several possible configurations, depending on the speaker impedance and whether the output configuration is single-ended (SE) or bridge-tied load (BTL). Table 4 lists the recommended values for the filter components. It is important to use a high-quality capacitor in this application. A rating of at least X7R and voltage rating of 50V is suggested. Table 4. Recommended Filter Output Components Output Configuration Speaker Impedance (Ω) Filter Inductor (µH) Filter Capacitor (nF) 4 22 680 8 33 220 8 22 680 Single - Ended (SE) Bridge - Tied Load (BTL) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 15 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com LOUT / ROUT LOUT Lfilter Lfilter Cfilter Cfilter ROUT Lfilter Cfilter Figure 27. BTL Filter Configuration Figure 28. SE Filter Configuration Power-Supply Decoupling, CS The TPA3125D2 is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power-supply leads. For higher-frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF to 1 µF, placed as close as possible to the device PVCC pin works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 470 µF or greater placed near the audio power amplifier is recommended. The 470-µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 470-µF or larger capacitor should be connect to each PVCC terminal. A 10-µF capacitor on the AVCC terminal is adequate. These capacitors must be properly derated for voltage and ripple-current rating to ensure reliability. BSN and BSP Capacitors The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be connected from LOUT to BSL, and one 220-nF capacitor must be connected from ROUT to BSR. The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating power supply for the high-side N-channel power MOSFET gate-drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. VCLAMP Capacitor To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, one internal regulator clamps the gate voltage. One 1-µF capacitor must be connected from VCLAMP (pin 11) to ground and must be rated for at least 16 V. The voltages at the VCLAMP terminal may vary with VCC and may not be used for powering any other circuitry. BYPASS Capacitor Selection The scaled supply reference (VBYP) nominally provides an AVCC/8 internal bias for the preamplifier stages. The external capacitor for this reference, CBYP, is a critical component and serves several important functions. During start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts. The start up time is proportional to 0.5 s per microfarad. Thus, the recommended 1-µF capacitor results in a start-up time of approximately 500 ms. The second function is to reduce noise produced by the power supply caused by coupling with the output drive signal. This noise could result in degraded power-supply rejection and THD+N. 16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 The circuit is designed for a CBYP value of 1 µF for best pop performance. The input capacitors should have the same value. A ceramic or tantalum low-ESR capacitor is recommended. SHUTDOWN OPERATION The TPA3125D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high (see specification table for threshold) during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SHUTDOWN unconnected, because amplifier operation would be unpredictable. For the best power-up pop performance, place the amplifier in the shutdown or mute mode prior to applying the power-supply voltage. MUTE Operation The MUTE pin is an input for controlling the output state of the TPA3125D2. A logic high on this terminal causes the outputs to switch at a constant 50% duty cycle. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources. The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be used when the amp will be off for a significant amount of time to reduce the quiescent current to the absolute minimum level. USING LOW-ESR CAPACITORS Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. SHORT-CIRCUIT PROTECTION The TPA3125D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts and output-to-GND shorts after the filter and output capacitor (at the speaker terminal.) Directly at the device terminals, the protection circuitry prevents damage to device during output-to-output, output-to-ground, and output-to-supply. When a short circuit is detected on the outputs, the part immediately disables the output drive. This is an unlatched fault. Normal operation is restored when the fault is removed. The device will try to restart after a 250 ms delay, so in a true fault condition the 250 msec period of the restart attempts can be used to confirm the fault is an over-current type. THERMAL PROTECTION Thermal protection on the TPA3125D2 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device begins normal operation at this point with no external system interaction. PRINTED-CIRCUIT BOARD (PCB) LAYOUT Because the TPA3125D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance. • Decoupling capacitors—The high-frequency 0.1-µF decoupling capacitors should be placed as close to the PVCC (pins 1 and 10) and AVCC (pins 16 and 17) terminals as possible. The BYPASS (pin 6) capacitor and VCLAMP (pin 9) capacitor should also be placed as close to the device as possible. Large (220-µF or greater) bulk power-supply decoupling capacitors should be placed near the TPA3125D2 on the PVCCL and PVCCR terminals. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 17 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com • • • Grounding—The AVCC (pins 16 and 17) decoupling capacitor and BYPASS (pin 6) capacitor should each be grounded to analog ground (AGND, pins 7 and 8). The PVCCx decoupling capacitors and VCLAMP capacitors should each be grounded to power ground (PGND, pins 11 and 20). Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3125D2. Output filter—The reconstruction filter (22µH and 0.68µF network in the output circuit) should be placed as close to the output terminals as possible for the best EMI performance. The capacitors should be grounded to power ground. Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land are described in the mechanical section at the back of the data sheet. See TI Technical Briefs SLMA002 and SLOA120 for more information about using the thermal pad. For recommended PCB footprints, see figures at the end of this data sheet. For an example layout, see the TPA3125D2 Evaluation Module (TPA3125D2 EVM) User Manual, (SLOU250). Both the EVM user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com. 18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 VCC 22uH Shutdown Control 0.1uF Mute Control 470uF 1 2 3 4 5 6 7 8 9 10 1.0uF Left Input Right Input 1.0uF 1.0uF PVCCL SD MUTE LIN RIN BYPASS AGND AGND VCLAMP PVCCR PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR 20 19 18 17 16 15 14 13 12 11 LEFT_OUT 4.7K 0.68uF 4.7K 0.68uF 0.22uF 0.22uF RIGHT_OUT TPA3125D2_PDIP 0.1uF 22uH 470uF 1.0uF 470uF 470uF 0.1uF 10uF Figure 29. Schematic for Single-Ended (SE) Configuration (8-Ω Speaker) VCC 22uH Shutdown Control 0.1uF Mute Control 1 2 3 4 5 6 7 8 9 10 1.0uF Plus Input Minus Input 1.0uF 1.0uF PVCCL SD MUTE LIN RIN BYPASS AGND AGND VCLAMP PVCCR PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR 20 19 18 17 16 15 14 13 12 11 LEFT_OUT 0.68uF 0.22uF 0.22uF RIGHT_OUT TPA3125D2_PDIP 0.68uF 0.1uF 1.0uF 470uF 22uH 470uF 0.1uF 10uF Figure 30. Schematic for Bridge-Tied-Load (BTL) Configuration (8-Ω Speaker) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 19 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com BASIC MEASUREMENT SYSTEM This section focuses on methods that use the basic equipment listed below: • Audio analyzer or spectrum analyzer • Digital multi-meter (DMM) • Oscilloscope • Twisted-pair wires • Signal generator • Power resistor(s) • Linear regulated power supply • Filter components • EVM or other complete audio circuit Figure 31 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal because it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the audio power amplifier (APA) output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two™ audio measurement system (AP-II) by Audio Precision™ includes the signal generator and analyzer in one package. The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the analyzer input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of milliohms and can be ignored for all but the power-related calculations. Figure 31(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal output. This amplifier circuit can be directly connected to the AP-II or other analyzer input. This is not true of the class-D amplifier system shown in Figure 31(b), which requires low-pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers. 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 Power Supply Signal Generator APA RL Analyzer 20 Hz - 20 kHz (a) Basic Class-AB Power Supply Lfilt Signal Generator Class-D APA Cfilt RL Analyzer 20 Hz - 20 kHz (b) Traditional Class-D Figure 31. Audio Measurement Systems Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 21 TPA3125D2 SLOS611 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com SE Input and SE Output (TPA3125D2 Stereo Configuration) The SE input and output configuration is used with class-D amplifiers. A block diagram of a fully SE measurement circuit is shown in Figure 32. SE inputs normally have one input pin per channel. In some cases, two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load through an output ac-coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs are considered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output. The generator should have unbalanced outputs, and the signal should be referenced to the generator ground for best results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop that affects the measurement accuracy. The analyzer should have balanced inputs to cancel out any common-mode noise in the measurement. Evaluation Module Audio Power Amplifier Generator Analyzer CIN VGEN RIN RGEN Lfilt Cfilt Twisted-Pair Wire CL RL RANA CANA RANA CANA Twisted-Pair Wire Figure 32. SE Input—SE Output Measurement Circuit The following general rules should be followed when connecting to APAs with SE inputs and outputs: • Use an unbalanced source to supply the input signal. • Use an analyzer with balanced inputs. • Use twisted-pair wire for all connections. • Use shielding when the system environment is noisy. • Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 5). 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 TPA3125D2 www.ti.com ........................................................................................................................................................................................... SLOS611 – DECEMBER 2008 DIFFERENTIAL INPUT AND BTL OUTPUT (TPA3125D2 Mono Configuration) Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied-load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins. Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing audio signals that are 180° out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc-blocking capacitor. A block diagram of the measurement circuit is shown in Figure 33. The differential input is a balanced input, meaning the positive (+) and negative (–) pins have the same impedance to ground. Similarly, the BTL output equates to a balanced output. Evaluation Module Audio Power Amplifier Generator Analyzer CIN RGEN VGEN Lfilt RIN Cfilt CIN RGEN RL Lfilt RIN Cfilt Twisted-Pair Wire RANA CANA RANA CANA Twisted-Pair Wire Figure 33. Differential Input, BTL Output Measurement Circuit The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in the circuit and providing the most accurate measurement. The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs: • Use a balanced source to supply the input signal. • Use an analyzer with balanced inputs. • Use twisted-pair wire for all connections. • Use shielding when the system environment is noisy. • Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see Table 5). Table 5 shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch (30.5-cm)-long wire with a 20-kHz sine-wave signal at 25°C. Table 5. Recommended Minimum Wire Size for Power Cables DC POWER LOSS (mW) AWG Size AC POWER LOSS (mW) POUT (W) RL(Ω) 10 4 18 22 16 40 18 42 2 4 18 22 3.2 8 3.7 8.5 1 8 22 28 2 8 2.1 8.1 < 0.75 8 22 28 1.5 6.1 1.6 6.2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3125D2 23 PACKAGE OPTION ADDENDUM www.ti.com 19-Jan-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing TPA3125D2N ACTIVE PDIP N Pins Package Eco Plan (2) Qty 20 20 Pb-Free (RoHS) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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