TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 6-W FILTER-FREE STEREO CLASS-D AUDIO POWER AMPLIFIER WITH SPEAKERGUARD™ Check for Samples: TPA3113D2 FEATURES 1 • 2 • • • • • • • • • • 6-W/ch into an 8-Ω Loads at 10% THD+N From a 10-V Supply 12-W into a 4-Ω Mono Load at 10% THD+N From a 10-V Supply 87% Efficient Class-D Operation Eliminates Need for Heat Sinks Wide Supply Voltage Range Allows Operation from 8 V to 26 V Filter-Free Operation SpeakerGuard™ Speaker Protection Includes Adjustable Power Limiter plus DC Protection Flow Through Pin Out Facilitates Easy Board Layout Robust Pin-to-Pin Short Circuit Protection and Thermal Protection with Auto Recovery Option Excellent THD+N / Pop-Free Performance Four Selectable, Fixed Gain Settings Differential Inputs APPLICATIONS • • • Televisions Consumer Audio Equipment Monitors DESCRIPTION The TPA3113D2 is a 6-W (per channel) efficient, Class-D audio power amplifier for driving bridged-tied stereo speakers. Advanced EMI Suppression Technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. SpeakerGuard™ speaker protection circuitry includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter allows the user to set a "virtual" voltage rail lower than the chip supply to limit the amount of current through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs. The TPA3113D2 can drive stereo speakers as low as 4 Ω. The high efficiency of the TPA3113D2, 87%, eliminates the need for an external heat sink when playing music. The outputs are also fully protected against shorts to GND, VCC, and output-to-output. The short-circuit protection and thermal protection includes an auto-recovery feature. 1mF Audio Source OUTL+ LINP OUTL- LINN OUTR+ RINP OUTR- RINN TPA3113D2 OUTPL OUTNL FERRITE BEAD FILTER 6W 8W FERRITE BEAD FILTER 6W 8W GAIN0 GAIN1 OUTPR OUTNR PLIMIT PBTL Fault SD PVCC 8 to 26V Figure 1. TPA3113D2 Simplified Application Schematic 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SpeakerGuard, PowerPad are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC Supply voltage AVCC, PVCC –0.3 V to 30 V SD, GAIN0, GAIN1, PBTL, FAULT VI Interface pin voltage –0.3 V to VCC + 0.3 V PLIMIT –0.3 V to GVDD + 0.3 V RINN, RINP, LINN, LINP –0.3 V to 6.3 V Continuous total power dissipation TA See Dissipation Rating Table Operating free-air temperature range TJ Operating junction temperature range Tstg Storage temperature range RL Minimum Load Resistance –40°C to 85°C (2) –40°C to 150°C –65°C to 150°C BTL: PVCC > 15 V 4.8 BTL: PVCC ≤ 15 V 3.2 PBTL ESD (1) 3.2 Human body model Electrostatic discharge (3) Charged-device model (all pins) (4) ±2 kV (all pins) ±500 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The TPA3113D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad. In accordance with JEDEC Standard 22, Test Method A114-B. In accordance with JEDEC Standard 22, Test Method C101-A (2) (3) (4) DISSIPATION RATINGS PACKAGE (1) TA ≤ 25°C DERATING FACTOR (qJA) TA = 85°C qJP ΨJT 28 pin TSSOP (PWP) 4.48 W 27.87 °C/W 2.33 W 0.72 °C/W 0.45 °C/W (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage PARAMETER PVCC, AVCC 8 26 VIH High-level input voltage SD, GAIN0, GAIN1, PBTL 2 VIL Low-level input voltage SD, GAIN0, GAIN1, PBTL 0.8 VOL Low-level output voltage FAULT, RPULL-UP=100k, VCC=26V 0.8 V IIH High-level input current SD, GAIN0, GAIN1, PBTL, VI = 2V, VCC = 18 V 50 µA IIL Low-level input current SD, GAIN0, GAIN1, PBTL, VI = 0.8 V, VCC = 18 V 5 µA TA Operating free-air temperature 85 °C 2 TEST CONDITIONS –40 Submit Documentation Feedback UNIT V V V Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 DC CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB ICC Quiescent supply current SD = 2 V, no load, PVCC = 24V ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24V rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 500 mA, TJ = 25°C GAIN1 = 0.8 V G Gain GAIN1 = 2 V ton Turn-on time SD = 2 V tOFF Turn-off time SD = 0.8 V GVDD Gate Drive Supply IGVDD = 100mA tDCDET DC Detect time V(RINN) = 6V, VRINP = 0V MIN TYP MAX 1.5 15 mV 32 50 mA 250 400 µA High Side 400 Low side 400 mΩ GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 14 6.9 dB dB ms 2 6.4 UNIT ms 7.4 420 V ms DC CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Class-D output offset voltage (measured differentially) VI = 0 V, Gain = 36 dB ICC Quiescent supply current SD = 2 V, no load, PVCC = 12V ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12V rDS(on) Drain-source on-state resistance VCC = 12 V, IO = 500 mA, TJ = 25°C GAIN1 = 0.8 V G Gain GAIN1 = 2 V tON Turn-on time SD = 2 V tOFF Turn-off time SD = 0.8 V GVDD Gate Drive Supply IGVDD = 2mA VO Output Voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1V rms MIN TYP MAX 1.5 15 mV 20 35 mA 200 High Side 400 Low side 400 µA mΩ GAIN0 = 0.8 V 19 20 21 GAIN0 = 2 V 25 26 27 GAIN0 = 0.8 V 31 32 33 GAIN0 = 2 V 35 36 37 14 Product Folder Link(s) :TPA3113D2 dB dB ms 2 ms 6.4 6.9 7.4 V 6.75 7.90 8.75 V Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated UNIT 3 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com AC CHARACTERISTICS TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN KSVR Power Supply ripple rejection 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs ac-coupled to AGND PO Continuous output power THD+N = 10%, f = 1 kHz, VCC = 10 V THD+N Total harmonic distortion + noise VCC = 16 V, f = 1 kHz, PO = 3 W (half-power) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted fOSC Oscillator frequency 250 Thermal trip point Thermal hysteresis TYP MAX UNIT –70 dB 6 W 0.07 % 65 µV –80 dBV –100 dB 102 dB 310 350 kHz 150 °C 15 °C AC CHARACTERISTICS TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT KSVR Supply ripple rejection 200 mVPP ripple from 20 Hz–1 kHz, Gain = 20 dB, Inputs ac-coupled to AGND –70 THD+N Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 3 W (half-power) 0.06 % 65 µV Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted fOSC Oscillator frequency 250 Thermal trip point Thermal hysteresis dB –80 dBV –100 dB 102 dB 310 350 kHz 150 °C 15 °C PWP (TSSOP) PACKAGE (TOP VIEW) SD FAULT 1 28 2 27 LINP LINN GAIN0 GAIN1 3 26 4 25 AVCC AGND GVDD PLIMIT RINN RINP NC PBTL 4 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 Submit Documentation Feedback PVCCL PVCCL BSPL OUTPL PGND OUTNL BSNL BSNR OUTNR PGND OUTPR BSPR PVCCR PVCCR Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 PIN FUNCTIONS PIN Pin Number I/O/P SD 1 I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. FAULT 2 O Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling PVCC. LINP 3 I Positive audio input for left channel. Biased at 3V. LINN 4 I Negative audio input for left channel. Biased at 3V. GAIN0 5 I Gain select least significant bit. TTL logic levels with compliance to AVCC. GAIN1 6 I Gain select most significant bit. TTL logic levels with compliance to AVCC. AVCC 7 P Analog supply AGND 8 GVDD 9 O High-side FET gate drive supply. Nominal voltage is 7V. Also should be used as supply for PLIMIT function PLIMIT 10 I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. RINN 11 I Negative audio input for right channel. Biased at 3V. RINP 12 I Positive audio input for right channel. Biased at 3V. NC 13 PBTL 14 I Parallel BTL mode switch PVCCR 15 P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally. PVCCR 16 P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally. BSPR 17 I Bootstrap I/O for right channel, positive high-side FET. OUTPR 18 O Class-D H-bridge positive output for right channel. PGND 19 OUTNR 20 O Class-D H-bridge negative output for right channel. BSNR 21 I Bootstrap I/O for right channel, negative high-side FET. BSNL 22 I Bootstrap I/O for left channel, negative high-side FET. OUTNL 23 O Class-D H-bridge negative output for left channel. PGND 24 OUTPL 25 O Class-D H-bridge positive output for left channel. BSPL 26 I Bootstrap I/O for left channel, positive high-side FET. PVCCL 27 P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally. PVCCL 28 P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally. NAME DESCRIPTION Analog signal ground. Connect to the thermal pad. Not connected Power ground for the H-bridges. Power ground for the H-bridges. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 5 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM GVDD PVCCL BSPL PVCCL PBTL Select OUTPL FB Gate Drive OUTPL OUTPL FB LINP Gain Control PGND PWM Logic PLIMIT GVDD LINN PVCCL BSNL PVCCL OUTNL FB OUTNL FB FAULT Gate Drive OUTNL SD GAIN0 TTL Buffer SC Detect Gain Control GAIN1 Ramp Generator Biases and References Startup Protection Logic PLIMIT Reference PLIMIT PGND DC Detect Thermal Detect UVLO/OVLO GVDD AVDD AVCC PVCCL BSNR PVCCL LDO Regulator GVDD Gate Drive GVDD OUTNR OUTNN FB OUTNR FB RINN Gain Control PLIMIT PGND PWM Logic GVDD RINP PVCCL BSPR PVCCL OUTNP FB Gate Drive PBTL TTL Buffer PBTL Select OUTPR PBTL Select OUTPR FB AGND PGND 6 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 TYPICAL CHARACTERISTICS (All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.) TOTAL HARMONIC DISTORTION vs FREQUENCY (BTL) TOTAL HARMONIC DISTORTION vs FREQUENCY (BTL) 10 Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH THD − Total Harmonic Distortion − % THD − Total Harmonic Distortion − % 10 1 0.1 PO = 5 W PO = 0.5 W 0.01 Gain = 20 dB VCC = 18 V ZL = 8 W + 66 mH 1 0.1 PO = 1 W 0.01 PO = 5 W PO = 2.5 W 0.001 20 100 1k 10k 0.001 20 20k 100 1k 10k G002 G001 Figure 2. Figure 3. TOTAL HARMONIC DISTORTION vs FREQUENCY (BTL) TOTAL HARMONIC DISTORTION vs FREQUENCY (BTL) 10 10 Gain = 20 dB VCC = 24 V ZL = 8 W + 66 mH THD − Total Harmonic Distortion − % THD − Total Harmonic Distortion − % 20k f − Frequency − Hz f − Frequency − Hz 1 0.1 PO = 1 W 0.01 Gain = 20 dB VCC = 12 V ZL = 6 Ω + 47 µH 1 0.1 PO = 5 W PO = 0.5 W 0.01 PO = 2.5 W PO = 5 W 0.001 20 100 1k 10k 20k 0.001 20 f − Frequency − Hz G003 Figure 4. 100 1k 10k 20k f − Frequency − Hz G004 Figure 5. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 7 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) (All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.) TOTAL HARMONIC DISTORTION vs FREQUENCY (BTL) TOTAL HARMONIC DISTORTION vs FREQUENCY (BTL) 10 Gain = 20 dB VCC = 18 V ZL = 6 W + 47 mH THD − Total Harmonic Distortion − % THD − Total Harmonic Distortion − % 10 1 0.1 0.01 PO = 1 W Gain = 20 dB VCC = 12 V ZL = 4 W + 33 mH 1 0.1 PO = 1 W 0.01 PO = 5 W PO = 5 W 0.001 20 100 1k 10k 0.001 20 20k 100 f − Frequency − Hz 1k 10k G005 G006 Figure 6. Figure 7. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (BTL) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (BTL) 10 Gain = 20 dB VCC = 12 V ZL = 8 Ω + 66 µH THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 10 1 f = 20 Hz 0.1 f = 1 kHz 0.01 f = 10 kHz 0.001 0.01 0.1 1 PO − Output Power − W 10 Gain = 20 dB VCC = 18 V ZL = 8 Ω + 66 µH 1 f = 1 kHz f = 20 Hz 0.1 0.01 f = 10 kHz 0.001 0.01 G007 Figure 8. 8 20k f − Frequency − Hz 0.1 1 PO − Output Power − W 10 G008 Figure 9. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 TYPICAL CHARACTERISTICS (continued) (All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (BTL) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (BTL) 10 Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % 10 1 f = 1 kHz 0.1 0.01 f = 20 Hz f = 10 kHz 0.001 0.01 0.1 1 0.1 0.01 f = 10 kHz 0.1 1 G009 Figure 10. Figure 11. TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (BTL) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (BTL) 10 G010 10 Gain = 20 dB VCC = 18 V ZL = 6 Ω + 47 µH THD+N − Total Harmonic Distortion + Noise − % THD+N − Total Harmonic Distortion + Noise − % f = 1 kHz f = 20 Hz PO − Output Power − W 10 1 f = 1 kHz f = 20 Hz 0.1 0.01 f = 10 kHz 0.001 0.01 1 0.001 0.01 10 PO − Output Power − W Gain = 20 dB VCC = 12 V ZL = 6 Ω + 47 µH 0.1 1 PO − Output Power − W 10 Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH 1 f = 1 kHz 0.1 0.01 f = 20 Hz f = 10 kHz 0.001 0.01 G011 Figure 12. 0.1 1 PO − Output Power − W 10 G012 Figure 13. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 9 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) (All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.) MAXIMUM OUTPUT POWER vs PLIMIT VOLTAGE (BTL) OUTPUT POWER vs PLIMIT VOLTAGE (BTL) 35 14 Gain = 20 dB VCC = 24 V ZL = 8 Ω + 66 µH Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH 30 12 PO − Output Power − W PO(Max) − Maximum Output Power − W 16 10 8 6 25 20 15 10 4 5 2 0 0.0 0 0.5 1.0 1.5 2.0 2.5 0 3.0 1 2 3 4 5 6 VPLIMIT − PLIMIT Voltage − V VPLIMIT − PLIMIT Voltage − V G014 G013 NOTE: Dashed line represents thermally limited region. NOTE: Dashed line represents thermally limited region. Figure 14. Figure 15. GAIN/PHASE vs FREQUENCY (BTL) EFFICIENCY vs OUTPUT POWER (BTL) 40 100 35 50 100 90 Phase 30 0 25 −50 VCC = 12 V 80 15 10 5 0 20 −100 −150 CI = 1 µF Gain = 20 dB Filter = Audio Precision AUX-0025 VCC = 12 V VI = 0.1 Vrms ZL = 8 Ω + 66 µH 100 1k 10k η − Efficiency − % Gain 20 Phase − ° Gain − dB 70 VCC = 18 V 60 VCC = 24 V 50 40 −200 30 −250 20 Gain = 20 dB ZL = 8 Ω + 66 µH 10 −300 100k 0 f − Frequency − Hz G015 0 1 2 3 4 5 6 7 8 PO − Output Power − W Figure 16. 10 9 10 G018 NOTE: Dashed lines represent thermally limited region. Figure 17. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 TYPICAL CHARACTERISTICS (continued) (All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.) EFFICIENCY vs OUTPUT POWER (BTL with LC FILTER) EFFICIENCY vs OUTPUT POWER (BTL) 100 100 VCC = 12 V 90 90 80 70 70 VCC = 18 V VCC = 24 V η − Efficiency − % η − Efficiency − % VCC = 12 V 80 60 50 40 30 VCC = 18 V 60 50 40 30 20 20 Gain = 20 dB LC Filter = 22 µH + 0.68 µF RL = 8 Ω 10 Gain = 20 dB ZL = 6 Ω + 47 µH 10 0 0 0 1 2 3 4 5 6 7 8 9 PO − Output Power − W 10 0 1 2 G032 NOTE: Dashed lines represent thermally limited region. Figure 18. 4 5 6 7 8 9 10 G019 NOTE: Dashed lines represent thermally limited region. Figure 19. EFFICIENCY vs OUTPUT POWER (BTL with LC FILTER) EFFICIENCY vs OUTPUT POWER (BTL) 100 100 90 Gain = 20 dB VCC = 12 V ZL = 4 Ω + 33 µH 90 VCC = 12 V 80 80 VCC = 18 V 70 η − Efficiency − % 70 η − Efficiency − % 3 PO − Output Power − W 60 50 40 30 60 50 40 30 20 20 Gain = 20 dB LC Filter = 22 µH + 0.68 µF RL = 6 Ω 10 10 0 0 0 1 2 3 4 5 6 7 8 PO − Output Power − W 9 10 0 1 3 4 5 6 7 8 9 PO − Output Power − W G033 NOTE: Dashed lines represent thermally limited region. Figure 20. 2 10 G020 NOTE: Dashed line represents thermally limited region. Figure 21. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 11 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) (All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.) EFFICIENCY vs OUTPUT POWER (BTL with LC FILTER) SUPPLY CURRENT vs TOTAL OUTPUT POWER (BTL) 1.2 100 Gain = 20 dB ZL = 8 Ω + 66 µH 90 1.0 ICC − Supply Current − A 80 η − Efficiency − % 70 60 50 40 30 20 VCC = 18 V 0.6 0.4 VCC = 24 V 0.2 Gain = 20 dB LC Filter = 22 µH + 0.68 µF RL = 4 Ω 10 VCC = 12 V 0.8 0 0.0 0 1 2 3 4 5 6 7 8 9 PO − Output Power − W 10 0 1 KSVR − Supply Ripple Rejection Ratio − dB Crosstalk − dB 6 −60 −70 −80 Right to Left −90 −100 Left to Right −110 −120 8 9 10 G021 100 1k 10k 20k −20 Gain = 20 dB Vripple = 200 mVpp ZL = 8 Ω + 66 µH −40 −60 VCC = 12 V −80 −100 −120 20 f − Frequency − Hz 100 1k 10k 20k f − Frequency − Hz G023 Figure 24. 12 7 0 Gain = 20 dB VCC = 12 V VO = 1 Vrms ZL = 8 Ω + 66 µH −50 −130 20 5 SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY (BTL) −20 −40 4 NOTE: Dashed lines represent thermally limited region. Figure 23. CROSSTALK vs FREQUENCY (BTL) −30 3 PO(Tot) − Total Output Power − W G034 NOTE: Dashed line represents thermally limited region. Figure 22. 2 G024 Figure 25. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 TYPICAL CHARACTERISTICS (continued) (All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.) TOTAL HARMONIC DISTORTION vs FREQUENCY (PBTL) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER (PBTL) 10 THD+N − Total Harmonic Distortion + Noise − % THD − Total Harmonic Distortion − % 10 Gain = 20 dB VCC = 12 V ZL = 4 W + 33 mH 1 PO = 5 W 0.1 PO = 0.5 W 0.01 PO = 2.5 W 0.001 20 100 1k 10k Gain = 20 dB VCC = 12 V ZL = 4 W + 33 mH 1 f = 1 kHz 0.1 0.01 f = 20 Hz f = 10 kHz 0.001 0.01 20k 0.1 f − Frequency − Hz 1 10 G025 Figure 26. Figure 27. GAIN/PHASE vs FREQUENCY (PBTL) EFFICIENCY vs OUTPUT POWER (PBTL) 40 100 100 35 50 90 Phase 30 0 25 −50 50 PO − Output Power − W G026 VCC = 12 V 80 VCC = 18 V 15 10 5 0 20 −100 −150 CI = 1 µF Gain = 20 dB Filter = Audio Precision AUX-0025 VCC = 24 V VI = 0.1 Vrms ZL = 8 Ω + 66 µH 100 1k −200 10k η − Efficiency − % Gain 20 Phase − ° Gain − dB 70 60 50 40 30 −250 20 −300 100k 10 Gain = 20 dB ZL = 4 Ω + 33 µH 0 f − Frequency − Hz G027 0 1 2 3 4 5 6 7 8 9 PO − Output Power − W Figure 28. 10 G029 Figure 29. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 13 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) (All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3113D2 EVM which is available at ti.com.) SUPPLY CURRENT vs OUTPUT POWER (PBTL) SUPPLY RIPPLE REJECTION RATIO vs FREQUENCY (PBTL) 0 1.0 0.9 KSVR − Supply Ripple Rejection Ratio − dB Gain = 20 dB ZL = 4 Ω + 33 µH ICC − Supply Current − A 0.8 0.7 0.6 VCC = 12 V 0.5 0.4 VCC = 18 V 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 PO − Output Power − W 8 9 10 −20 Gain = 20 dB Vripple = 200 mVpp ZL = 8 Ω + 66 µH −40 −60 −80 −100 −120 20 100 1k 10k 20k f − Frequency − Hz G031 G030 Figure 30. 14 VCC = 12 V Figure 31. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 DEVICE INFORMATION Gain Setting Via GAIN0 and GAIN1 Inputs The gain of the TPA3113D2 is set by two input terminals, GAIN0 and GAIN1. The voltage slew rate of these gain terminals, along with terminals 1 and 14, must be restricted to no more than 10V/ms. For higher slew rates, use a 100kΩ resistor in series with the terminals. The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3113D2. At the lower gain settings, the input impedance could increase as high as 72 kΩ Table 1. Gain Setting AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ) TYP TYP 20 60 1 26 30 0 32 15 1 36 9 GAIN1 GAIN0 0 0 0 1 1 SD Operation The TPA3113D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply voltage. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 15 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com PLIMIT The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Also add a 1mF capacitor from pin 10 to ground. Vinput PLIMIT = 6.96V Pout = 11.8W PLIMIT = 3V Pout = 10W PLIMIT = 1.8V Pout = 5W TPA3110D1 Power Limit Function Vin=1.13VPP Freq=1kHz RLoad=8W Figure 32. PLIMIT Circuit Operation The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to PVCC. This "virtual" rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance. POUT ææ ö ö RL çç ç ÷ x VP ÷÷ è RL + 2 x RS ø ø = è 2 x RL 2 for unclipped power (1) Where: RS is the total series resistance including RDS(on), and any resistance in the output filter. RL is the load resistance. VP is the peak amplitude of the output possible within the supply rail. VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP POUT (10%THD) = 1.25 × POUT (unclipped) Table 2. PLIMIT Typical Operation 16 TEST CONDITIONS () PLIMIT VOLTAGE OUTPUT POWER (W) OUTPUT VOLTAGE AMPLITUDE (VP-P) PVCC=24V, Vin=1Vrms, RL=8Ω, Gain=26dB 1.62 5 14 PVCC=24V, Vin=1Vrms, RL=8Ω, Gain=20dB 1.86 5 14.8 PVCC=12V, Vin=1Vrms, RL=8Ω, Gain=20dB 1.76 5 15 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 GVDD Supply The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT voltage divider circuit. Add a 1mF capacitor to ground at this pin. DC Detect TPA3113D2 has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling S D will NOT clear a DC detect fault. A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example, +57%, -43%) for more than 420 msec at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults. The minimum differential input voltages required to trigger the DC detect are show in table 2. The inputs must remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect. Table 3. DC Detect Threshold AV(dB) Vin (mV, differential) 20 112 26 56 32 28 36 17 PBTL Select TPA3113D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly. If the PBTL pin (pin 14) is tied high, the positive and negative outputs of each channel (left and right) are synchronized and in phase. To operate in this PBTL (mono) mode, apply the input signal to the RIGHT input and place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for best efficiency. For an example of the PBTL connection, see the schematic in the APPLICATION INFORMATION section. For normal BTL operation, connect the PBTL pin to local ground. Short-Circuit Protection and Automatic Recovery Feature TPA3113D2 has protection from overcurrent conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state. If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit protection latch. Thermal Protection Thermal protection on the TPA3113D2 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device begins normal operation at this point with no external system interaction. Thermal protection faults are NOT reported on the FAULT terminal. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 17 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com APPLICATION INFORMATION PVCC 100 μF 0.1 μF 1000 pF 100 kΩ Control System 1 SD PVCCL FAULT PVCCL 28 1 kΩ 2 1 mF 3 1 mF 4 5 6 PVCC 10 Ω 7 1 mF 8 1 mF 9 LINP LINN BSPL OUTPL GAIN0 PGND GAIN1 OUTNL 27 26 1000 pF 24 23 22 BSNL TPA3113D2 21 BSNR AGND OUTNR FB 25 AVCC GVDD 0.22 μF 1000 pF 0.22 μF 0.22 μF FB FB 20 1000 pF 1 mF 10 kΩ 10 PLIMIT PGND 19 10 kΩ 1 mF Audio Source 11 12 1 mF 13 14 RINN RINP OUTPR BSPR NC PVCCR PBTL PVCCR 18 1000 pF 17 FB 0.22 μF 16 15 100 μF 0.1 μF 1000 pF GND 29 PowerPAD PVCC Figure 33. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs with Power Limiting 18 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 PVCC 100 μF 0.1 μF 1000 pF 100 kΩ Control System 1 2 3 4 5 AVCC PVCC 6 PVCCL FAULT PVCCL 7 LINP BSPL LINN OUTPL GAIN0 PGND GAIN1 OUTNL AVCC BSNL 10 Ω 8 1 mF 9 1 mF 10 1 mF Audio Source SD 28 1 kΩ 11 12 1 mF 13 TPA3113D AGND BSNR GVDD OUTNR PLIMIT PGND RINN OUTPR RINP BSPR NC PVCCR PBTL PVCCR 27 26 0.47 μF 25 24 FB 23 1000 pF 22 21 1000 pF 20 FB 19 0.47 μF 18 17 16 100 μF AVCC 14 0.1 μF 1000 pF 15 GND 29 PowerPAD PVCC Figure 34. Stereo Class-D Amplifier with PBTL Output and Single-Ended Input Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 19 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com TPA3113D2 Modulation Scheme The TPA3113D2 uses a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the load. OUTP OUTN OUTP OUTP-OUTN No Output 0V Speaker Current OUTP OUTN Positive Output PVCC OUTP-OUTN 0V Speaker Current 0A OUTP Negative Output OUTN OUTP-OUTN 0V -PVCC Speaker 0A Current Figure 35. The TPA3113D2 Output Voltage and Current Waveforms Into an Inductive Load Ferrite Bead Filter Considerations Using the Advanced Emissions Suppression Technology in the TPA3113D2 amplifier it is possible to design a high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the Class D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz. 20 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case, it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current of the amplifier. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite beads which have been tested and work well with the TPA3113D2 include 28L0138-80R-10 and HI1812V101R-10 from Steward and the 742792510 from Wurth Electronics. A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best. Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the PGND or the PowerPad™ beneath the chip. 70 FCC Class B (3m) Limit Level - dBmV/m 60 50 40 30 20 10 0 30M 230M 430M 630M 830M f - Frequency - Hz Figure 36. TPA3113D2 EMC spectrum with FCC Class B Limits Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3113D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 21 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com When to Use an Output Filter for EMI Suppression The TPA3113D2 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 125 cm and high power. The TPA3113D2 EVM passes FCC Class B specifications under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency. There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases, a classic second order Butterworth filter similar to those shown in the figures below can be used. Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these cases, it LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference. 33 mH OUTP L1 C2 1 mF 33 mH OUTN L2 C3 1 mF Figure 37. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω 15 mH OUTP L1 C2 2.2 mF 15 mH OUTN L2 C3 2.2 mF Figure 38. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω Ferrite Chip Bead OUTP 1 nF Ferrite Chip Bead OUTN 1 nF Figure 39. Typical Ferrite Chip Bead Filter (Chip Bead Example) 22 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 Input Resistance Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps. Zf Ci IN Input Signal Zi The -3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 1. f = 1 2p Zi Ci (2) Input Capacitor, CI In the typical application, an input capacitor CI) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a high-pass filter with the corner frequency determined in Equation 3. -3 dB fc = 1 2p Zi Ci fc (3) The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is reconfigured as Equation 4. Ci = 1 2p Zi fc (4) In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 mF as this value is commonly used. If the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is the leakage path from the input source through the input network CI) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 23 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com Power Supply Decoupling, CS The TPA3113D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to the device PVCC pins and system ground (either PGND pins or PowerPad) as possible. For mid-frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality capacitor typically 0.1 mF to 1 µF placed as close as possible to the device PVCC leads works best For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 mF or greater placed near the audio power amplifier is recommended. The 220 mF capacitor also serves as a local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220 µF or larger capacitor should be placed on each PVCC terminal. A 10 µF capacitor on the AVCC terminal is adequate. Also, a small decoupling resistor between AVCC and PVCC can be used to keep high frequency class D noise from entering the linear input amplifiers. BSN and BSP Capacitors The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 0.22 mF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 0.22 mF capacitor must be connected from OUTPx to BSPx, and one 0.22 mF capacitor must be connected from OUTNx to BSNx. (See the application circuit diagram in Figure 1.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. Differential Inputs The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3113D2 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3113D2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same. The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc blocking capacitors to become completely charged during the 14 ms power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched. Using LOW-ESR Capacitors Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor. 24 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 TPA3113D2 www.ti.com SLOS650C – AUGUST 2009 – REVISED JULY 2010 Printed-Circuit Board (PCB) Layout The TPA3113D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements. • Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (220 µF or greater) bulk power supply decoupling capacitors should be placed near the TPA3113D2 on the PVCCL and PVCCR supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1mF and 1mF also of good quality to the PVCC connections at each end of the chip. • Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to PGND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna. • Grounding—The AVCC (pin 7) decoupling capacitor should be grounded to analog ground (AGND). The PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3113D2. • Output filter—The ferrite EMI filter (Figure 39) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter (Figure 37 and Figure 38) should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded to power ground. • Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35mm. Seven rows of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB footprints, see figures at the end of this data sheet. For an example layout, see the TPA3113D2 Evaluation Module (TPA3113D2EVM) User Manual. Both the EVM user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 25 TPA3113D2 SLOS650C – AUGUST 2009 – REVISED JULY 2010 www.ti.com REVISION HISTORY Changes from Original (August 2009) to Revision A Page • Changed Feature From: 90% Efficient Class-D Operation Eliminates Need for Heat Sinks To: 87% Efficient Class-D Operation Eliminates Need for Heat Sinks ........................................................................................................................... 1 • Changed the Drain Source TYP value From: 240 to 400 mΩ. ............................................................................................. 3 • Changed the Drain Source TYP value From: 240 to 400 mΩ. ............................................................................................. 3 • Changed AC Char 24V - PO From: THD+N = 10%, f = 1 kHz, VCC = 16 V (TYP = 15W) To: THD+N = 10%, f = 1 kHz, VCC = 10 V (TYP = 6W) ................................................................................................................................................ 4 • Changed AC Char 24V - THD+N From: VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power) To: VCC = 16 V, f = 1 kHz, PO = 3 W (half-power) TYP From: 0.1 To: 0.07. ................................................................................................................... 4 • Deleted AC Char 12V -, PO - Continuous output power ...................................................................................................... 4 • Changed AC Char 12V - THD+N From: VCC = 16 V, f = 1 kHz, PO = 5 W (half-power) To: VCC = 16 V, f = 1 kHz, PO = 3 W (half-power) ................................................................................................................................................................ 4 • Changed multiple graphs in theTYPICAL CHARACTERISTICS. ......................................................................................... 7 Changes from Revision A (August 2009) to Revision B Page • Added the Pin out illustration. ............................................................................................................................................... 4 • Changed the Stereo Class-D Amplifier with BTL Output and Single-Ended Input illustration Figure 33 - Corrected the pin names. .................................................................................................................................................................... 18 • Changed the Stereo Class-D Amplifier with PBTL Output and Single-Ended Input Figure 34 - Corrected the pin names. ................................................................................................................................................................................ 19 Changes from Revision B (September 2009) to Revision C • 26 Page Added slew rate adjustment information ............................................................................................................................. 15 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s) :TPA3113D2 PACKAGE OPTION ADDENDUM www.ti.com 19-Jun-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPA3113D2PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Purchase Samples TPA3113D2PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPA3113D2PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 28 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA3113D2PWPR HTSSOP PWP 28 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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