AVAGO ACPM-7392

ACPM-7392
UTMS1700/2100(1710-1755MHz) and UMTS1700(1750-1785MHz)
Data Sheet
Description
Features
The ACPM-7392 is a fully matched 10-pin surface mount
module developed for UMTS Band4 and Band9. This power amplifier module operates in the 1710-1785MHz bandwidth. The ACPM-7392 meets stringent UMTS linearity
requirements up to 28.4dBm output power in band4 and
28.0dBm output power in band9. The 4mmx4mm form
factor package is self contained, incorporating 50ohm input and output matching networks
• Thin Package (0.9mm typ)
The ACPM-7392 features 5th generation of CoolPAM circuit technology which supports 3 power modes – bypass,
mid and high power modes. The CoolPAM is stage bypass
technology enhancing PAE (power added efficiency) at
low and medium power range. Active bypass feature is
added to 5th generation to enhance PAE further at low
output range. This helps to extend talk time.
The power amplifier is manufactured on an advanced
InGaP HBT (hetero-junction Bipolar Transistor) MMIC (microwave monolithic integrated circuit) technology offering state-of-the-art reliability, temperature stability and
ruggedness.
• Excellent Linearity
• 3-mode power control with Vbp and Vmode
Bypass / Mid Power Mode / High Power Mode
• High Efficiency at max output power
• 10-pin surface mounting package
• Internal 50ohm matching networks for both RF input
and output
• Lead-free, RoHS compliant, Green
Applications
• UMTS Band4 and Band9
Ordering Information
Part Number
Number of
Devices
Container
ACPM-7392-TR1
1,000
178mm (7”) Tape/Reel
ACPM-7392-BLK
100
BULK
Block Diagram
Ven(5)
Vcc1(1)
Bias Circuit & Control Logic
Vmode(4)
Vbp(3)
Vcc2(10)
RF In(2)
Inter-Stage
Match
Input Match &
Power Divider
Bypass
Circuit
Output
Match
Impedence
Transformer
RF Out(8)
Absolute Maximum Ratings
No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value.
Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal
values may result in permanent damage
Description
Min.
RF Input Power (Pin)
Typ.
Max.
Unit
0
10 *
dBm
DC Supply Voltage (Vcc1, Vcc2)
0
3.4
5.0
V
Enable Voltage (Ven)
0
2.6
3.3
V
Mode Control Voltage (Vmode)
0
2.6
3.3
V
Bypass Control (Vbp)
0
2.6
3.3
V
Storage Temperature (Tstg)
-55
25
+125
°C
* High Power Mode (5dBm for Bypass and Mid Power Mode)
Recommended Operating Condition
Description
Min.
Typ.
Max.
Unit
DC Supply Voltage (Vcc1, Vcc2)
3.2
3.4
4.2
V
Enable Voltage (Ven)
Low
High
0
1.35
0
2.6
0.5
3.1
V
V
Mode Control Voltage (Vmode)
Low
High
0
1.35
0
2.6
0.5
3.1
V
V
Bypass Control Voltage (Vbp)
Low
High
0
1.35
0
2.6
0.5
3.1
V
V
Operating Frequency (fo)
1710
1785
MHz
Ambient Temperature (Ta)
-20
85
°C
25
Operating Logic Table
Power Mode
Ven
Vmode
Vbp
Pout (Rel99)
Pout (HSDPA, HSUPA MPR=0dB)
High Power Mode
High
Low
Low
~ 28.4 dBm (Band4)
~ 28.0 dBm (Band9)
~ 27.4 dBm (Band4)
~ 27.0 dBm (Band9)
Mid Power Mode
High
High
Low
~ 17 dBm
~ 16 dBm
Bypass Mode
High
High
High
~ 8 dBm
~ 7 dBm
Shut Down Mode
Low
Low
Low
-
-
Electrical Characteristics for WCDMA Mode
- Conditions: Vcc=3.4V, Ven=2.6V, T=25°, Zin/Zout=50ohm
- Signal Configuration: 3GPP (DPCCH + 1DPDCH) Up-Link unless specified otherwise.
Characteristics
Condition
Min.
Typ.
Max.
Unit
1710
–
1755
MHz
High Power Mode, Pout=28.4dBm
24.5
28.5
dB
Mid Power Mode, Pout=17dBm
16
22.5
dB
Bypass Mode, Pout=8dBm
8
12.5
16
dB
Operating Frequency Range
Gain
GPS Band Gain relative to Tx Gain,
HPM
Ggps@Pin=-15dBm – Gtx@Pout=28.4dBm
-6
-1
dB
Rx Band Gain relative to Tx Gain
Grx@Pin=-15dBm – Gtx@Pout=28.4dBm
-10
-6
dB
ISM Band Gain relative to Tx Gain
Gism@Pin=-15dBm – Gtx@Pout=28.4dBm
-17
-4
dB
Power Added Efficiency
High Power Mode, Pout=28.4dBm
36.3
40.2
%
Mid Power Mode, Pout=17dBm
14.7
19.5
%
Bypass Mode, Pout=8dBm
8.8
13.5
Total Supply Current
Quiescent Current
%
High Power Mode, Pout=28.4dBm
505
560
mA
Mid Power Mode, Pout=17dBm
75
100
mA
Bypass Mode, Pout=8dBm
13
20
mA
High Power Mode
75
100
125
mA
Mid Power Mode
15
25
40
mA
Bypass Mode
1
3
5
mA
High Power Mode
10
25
µA
Mid Power Mode
10
25
µA
Bypass Mode
10
25
µA
Mid Power Mode
5
25
µA
Bypass Mode
5
25
µA
Bypass Control Current
Bypass
5
25
µA
Total Current in Power-down mode
Ven=0V, Vmode=0V, Vbp=0V
5
µA
Adjacent Channel
Leakage Ratio
5 MHz offset
10 MHz offset
High Power Mode, Pout=28.4dBm
-41
-51
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
High Power Mode, Pout=27.4dBm
(HSDPA, HSUPA MPR=0dB)
-38.5
-51
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
Mid Power Mode, Pout=17dBm
-45
-57
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
Mid Power Mode, Pout=16dBm
(HSDPA, HSUPA MPR=0dB)
-43
-56
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
Bypass Mode, Pout=8dBm
-46
-54
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
Bypass Mode, Pout=7dBm
(HSDPA, HSUPA MPR=0dB)
-43
-53
-36
-46
dBc
dBc
Enable Current
Mode Control Current
Electrical Characteristics for WCDMA Mode
Characteristics
Harmonic
Suppression
Condition
Second
Third
High Power Mode, Pout=28.4dBm
Gain at Harmonics
Second and Third
Input VSWR
High Power Mode
Stability (Spurious Output)
Load VSWR 5:1, All phase
Rx Band Noise Power (Vcc=4.2V)
High Power Mode, Pout=28.4dBm
GPS Band Noise (Vcc=4.2V)
ISM Band Noise (Vcc=4.2V)
Min.
Typ.
Max.
Unit
-41
-62
-35
-40
dBc
dBc
0
dB
1.5:1
2.5:1
-60
dBc
-141
-139
dBm/Hz
High Power Mode, Pout=28.4dBm
-138
-134
dBm/Hz
High Power Mode, Pout=28.4dBm
-146
-143
dBm/Hz
Phase Discontinuity
HPM <--> MPM, Pout=17dBm
MPM <--> BPM, Pout=8dBm
19
40
45
60
deg
deg
Ruggedness
Pout<28.4dBm & Pin<=5dBm, All phase, High
Power Mode
8:1
VSWR
1.
HSDPA
3GPP TS 34.121-1
User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 1: Conformance specification
Annex C (normative): Measurement channels
C.10.1 UL reference measurement channel for HSDPA tests
Table C.10.1.4: β values for transmitter characteristics tests with HS-DPCCH
Sub-test 2 (CM=1.0dB, MPR=0.0dB)
2.
HSUPA
3GPP TS 34.121-1
User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 1: Conformance specification
Annex C (normative): Measurement channels
C.11.1 UL reference measurement channel for E-DCH tests
Table C.11.1.3: β values for transmitter characteristics tests with HS-DPCCH and E-DCH
Sub-test 1 (CM=1.0dB, MPR=0.0dB)
Electrical Characteristics for WCDMA Mode (Band9)
- Conditions: Vcc=3.4V, Ven=2.6V, T=25°, Zin/Zout=50ohm
- Signal Configuration: 3GPP (DPCCH + 1DPDCH) Up-Link unless specified otherwise.
Characteristics
Condition
Min.
Typ.
Max.
Unit
1750
–
1785
MHz
High Power Mode, Pout=28.0dBm
24.5
28.5
dB
Mid Power Mode, Pout=17dBm
16.5
20.5
dB
Bypass Mode, Pout=8dBm
9
13.0
dB
High Power Mode, Pout=28.0dBm
33.1
39.4
%
Mid Power Mode, Pout=17dBm
14.6
19.5
%
Bypass Mode, Pout=8dBm
8.8
14.1
%
Operating Frequency Range
Gain
Power Added Efficiency
Total Supply Current
Quiescent Current
Enable Current
Mode Control Current
High Power Mode, Pout=28.0dBm
470
560
mA
Mid Power Mode, Pout=17dBm
75
100
mA
Bypass Mode, Pout=8dBm
12.5
20
mA
High Power Mode
75
100
125
mA
Mid Power Mode
15
25
40
mA
Bypass Mode
1
3
5
mA
High Power Mode
10
25
µA
Mid Power Mode
10
25
µA
Bypass Mode
10
25
µA
Mid Power Mode
5
25
µA
Bypass Mode
5
25
µA
Bypass Control Current
Bypass
5
25
µA
Total Current in Power-down mode
Ven=0V, Vmode=0V, Vbp=0V
5
µA
Adjacent Channel
Leakage Ratio
5 MHz offset
10 MHz offset
High Power Mode, Pout=28.0dBm
-42
-52
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
High Power Mode, Pout=27.0dBm
(HSDPA, HSUPA MPR=0dB)
-39
-51
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
Mid Power Mode, Pout=17dBm
-43
-57
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
Mid Power Mode, Pout=16dBm
(HSDPA, HSUPA MPR=0dB)
-41
-57
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
Bypass Mode, Pout=8dBm
-44
-54
-36
-46
dBc
dBc
5 MHz offset
10 MHz offset
Bypass Mode, Pout=7dBm
(HSDPA, HSUPA MPR=0dB)
-43
-53
-36
-46
dBc
dBc
Second
Third
High Power Mode, Pout=28.0dBm
-41
-62
-35
-40
dBc
dBc
Harmonic
Suppression
Electrical Characteristics for WCDMA Mode (Band9)
Characteristics
Condition
Input VSWR
High Power Mode
Stability (Spurious Output)
Load VSWR 5:1, All phase
Rx Band Noise Power (Vcc=4.2V)
High Power Mode, Pout=28.0dBm
GPS Band Noise (Vcc=4.2V)
High Power Mode, Pout=28.0dBm
ISM Band Noise (Vcc=4.2V)
Min.
Typ.
Max.
1.5:1
2.5:1
Unit
-60
dBc
-133.5
-130
dBm/Hz
-137
-134
dBm/Hz
High Power Mode, Pout=28.0dBm
-146
-143
dBm/Hz
Phase Discontinuity
HPM <--> MPM, Pout=17dBm
MPM <--> BPM, Pout=8dBm
25
25
45
45
deg
deg
Ruggedness
Pout<28.0dBm & Pin<=5dBm, All phase, High
Power Mode
8:1
VSWR
1.
HSDPA
3GPP TS 34.121-1
User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 1: Conformance specification
Annex C (normative): Measurement channels
C.10.1 UL reference measurement channel for HSDPA tests
Table C.10.1.4: β values for transmitter characteristics tests with HS-DPCCH
Sub-test 2 (CM=1.0dB, MPR=0.0dB)
2.
HSUPA
3GPP TS 34.121-1
User Equipment (UE) conformance specification; Radio transmission and reception (FDD); Part 1: Conformance specification
Annex C (normative): Measurement channels
C.11.1 UL reference measurement channel for E-DCH tests
Table C.11.1.3: β values for transmitter characteristics tests with HS-DPCCH and E-DCH
Sub-test 1 (CM=1.0dB, MPR=0.0dB)
Footprint
PIN Description
0.40
1.90 1.70
0.40
0.10
0.85
Pin #
Name
Description
1
Vcc1
DC Supply Voltage
2
RFin
RF Input
3
Vbp
Bypass Control
4
Vmode
Mode Control
5
Ven
PA Enable
6
GND
Ground
7
GND
Ground
8
RFout
RF Output
9
GND
Ground
10
Vcc2
DC Supply Voltage
1.90
1.20
X-Ray Top View
All dimensions are in millimeter
Package Dimensions
0.60
Pin 1 Mark
1
10
2
9
3
8
4
7
5
6
4 ± 0.1
0.9 ± 0.1
4 ± 0.1
All dimensions are in millimeter
Marking Specification
Pin 1 Mark
AVAGO
ACPM-7392
PYYWW
AAAAAA
Manufacturing Part Number
Lot Number
P
YY
WW
AAAAAA
Manufacturing info
Manufacturing Year
Work Week
Assembly Lot Number
CoolPAM
Average current & Talk time
Avago Technologies’ CoolPAM is stage-bypass PA technology which saves more power compared with conventional PA. With this technology, the ACPM-7392 has very low
quiescent current, and efficiencies at low and medium
output power ranges are high.
Average current consumed by PA can be calculated by
summing up current at each output power weighted with
probability. So it is expressed with integration of multiplication of current and probability at each output power.
The ACPM-7392 has internal bias circuit, which removes
the need for external constant voltage source (LDO). PA
on/off is controlled by Ven. This is digitally control pin.
3-mode power control with two mode control pins
The ACPM-7392 supports three power modes ( bypass
power mode/mid power mode/high power mode) with
two mode control pins (Vmode and Vbp). This control
scheme enables the ACPM-7392 to save power consumption more, which accordingly gives extended talk time.
PDF (probability density function) showing distribution
of output power of mobile in real field gives motivation
for stage-bypass PA. Output power is less than 16dBm for
most of operating time (during talking), so it is important
to save power consumption at low and medium output
power ranges.
Talk time is extended more as average current consumption is lowered.
Mode control pins
Vmode and Vbp are digitally controlled by baseband and
they control the operating mode of the PA. The operating
logic table is summarized on the page 2. These pins do not
require constant voltage for interface. .
UMTS PA performance comparison
– CoolPAM 4 and CoolPAM 5
450
Current (mA)
Incorporation of bias circuit
PDF and Current
400
CP5
350
CP4
300
250
200
150
100
50
0
-10
0
10
Pout(dBm)
20
30
70
60
Current (mA)
50
40
30
20
CP5
CP4
10
0
-10
-8
-6
-4
-2
0
2
4
Pout(dBm)
6
8
10
12
14
16
Icc Comparison of CP5 to CP4 (Avago CoolPAM)
The 5th generation of CoolPAM technology, ACPM-7392
can dramatically reduce Icc down to 3mA at bypass mode,
which improves overall talk time and battery usage time
of handset more compared with the CP4.
Application on mobile phone board
PCB layout and part placement on phone board
Application example in mobile is shown below. C4 and C5
should be placed close to pin1 and pin10. Bypass cap C1,
C2 and C3 should be also placed nearby from pin5, pin4
and pin3, respectively. The length of post-PA transmission
line should be minimized to reduce line loss.
3
1
2
V BATT
Via hole
4
C6
PCB guideline on phone board
C4
C5
Notes
output matching circuit
C9
Vcc1
IN
Vbp
Vmode
Ven
RF In
Vcc2
GND
OUT
GND
GND
ACPM-7392
C3
C2
C1
BB
PA_R1
PA_R0
PA_ON
Peripheral Circuits
1. To prevent voltage drop, make the bias lines as wide as
possible (Pink line).
C8
C7
L1
RF Out
2. Use many via holes to fence off PA RF input and output
traces for better isolation. Output signal of the PA
should be isolated from input signal and the receive
signal. Output signal should not be fed into PA input.
(Green line)
3. Use via holes to connect outer ground plates to internal
ground planes. They help heat spread out more easily
and accordingly the board temperature can be lowered.
They also help to improve RF stability (Yellow square).
4. PA which has a ground slug requires many via holes
which go through all the layers (Red square).
Metallization
PCB Design Guidelines
0.1
0.6
The recommended PCB land pattern is shown in figures on the left side. The substrate is coated with solder
mask between the I/O and conductive paddle to protect
the gold pads from short circuit that is caused by solder
bleeding/bridging.
0.5
0.4
Stencil Design Guidelines
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads.
0.85
The recommended stencil layout is shown here. Reducing
the stencil opening can potentially generate more voids.
On the other hand, stencil openings larger than 100% will
lead to excessive solder paste smear or bridging across
the I/O pads or conductive paddle to adjacent I/O pads.
Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice
is to use laser cut stencil composed of 0.100mm(4mils) or
0.127mm(5mils) thick stainless steel which is capable of
producing the required fine stencil outline.
0.25
Ø 0.3mm
on 0.6mm pitch
Solder Mask Opening
0.7
0.55
0.5
1.8
0.85
2.4
Solder Paste Stencil Aperture
0.6
0.5
0.4
1.6
0.85
2.0
10
Evaluation Board Schematic
Vcc1
RF In
C5
2.2uF
C4
1000pF
1 Vcc1
Vcc2 10
2 RF In
GND 9
3 Vbp
RF Out 8
C6
1000pF
C7
2.2uF
RF Out
Vmode1
Vmode0
C3
100pF
Ven
C2
100pF
C1
100pF
4 Vmode
GND 7
5 Ven
GND 6
Evaluation Board Description
C7
C5
C4
C6
•AVAGO
ACPM-7392
PYYWW
AAAAA
C3
11
Vcc2
C2
C1
Tape and Reel Information
AVAGO
ACPM-7392
PYYWW
AAAAAA
Dimension List
Annote
Millimeter
Annote
Millimeter
A0
4.40±0.10
P2
2.00±0.05
B0
4.40±0.10
P10
40.00±0.20
K0
1.70±0.10
E
1.75±0.10
D0
1.55±0.05
F
5.50±0.05
D1
1.60±0.10
W
12.00±0.30
P0
4.00±0.10
T
0.30±0.05
P1
8.00±0.10
Tape and Reel Format – 4 mm x 4 mm.
12
Reel Drawing
BACK VIEW
Shading indicates
thru slots
18.4 max.
178 +0.4
-0.2
50 min.
25
min wide (ref)
Slot for carrier tape
insertion for attachment
to reel hub (2 places 180° apart)
12.4 +2.0
-0.0
FRONT VIEW
1.5 min.
13.0 ± 0.2
21.0 ± 0.8
Plastic Reel Format (all dimensions are in millimeters)
13
NOTES:
1. Reel shall be labeled with the following
information (as a minimum).
a. manufacturers name or symbol
b. Avago Technologies part number
c. purchase order number
d. date code
e. quantity of units
2. A certificate of compliance (c of c) shall
be issued and accompany each shipment
of product.
3. Reel must not be made with or contain
ozone depleting materials.
4. All dimensions in millimeters (mm)
Handling and Storage
ESD (Electrostatic Discharge)
Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of
neutralization or discharge will be sought. If the acquired
discharge route is through a semiconductor device, destructive damage will result.
ESD countermeasure methods should be developed and
used to control potential ESD damage during handling in
a factory environment at each manufacturing site.
MSL (Moisture Sensitivity Level)
Plastic encapsulated surface mount package is sensitive
to damage induced by absorbed moisture and temperature.
Avago Technologies follows JEDEC Standard J-STD 020B.
Each component and package type is classified for moisture sensitivity by soaking a known dry package at vari-
ous temperatures and relative humidity, and times. After
soak, the components are subjected to three consecutive
simulated reflows.
The out of bag exposure time maximum limits are determined by the classification test describe below which
corresponds to a MSL classification level 6 to 1 according
to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD033.
ACPM-7392 is MSL3. Thus, according to the J-STD-033
p.11 the maximum Manufacturers Exposure Time (MET)
for this part is 168 hours. After this time period, the part
would need to be removed from the reel, de-taped and
then re-baked. MSL classification reflow temperature for
the ACPM-7392 is targeted at 260° +0/-5°. Figure and table on next page show typical SMT profile for maximum
temperature of 260 +0/-5°.
Moisture Classification Level and Floor Life
MSL Level
Floor Life (out of bag) at factory ambient ≤ 30°C/60% RH or as stated
1
Unlimited at ≤ 30°C/85% RH
2
1 year
2a
4 weeks
3
168 hours
4
72 hours
5
48 hours
5a
24 hours
6
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
Note :
1. The MSL Level is marked on the MSL Label on each shipping bag.
14
Reflow Profile Recommendations
tp
Tp
Critical Zone
T L to Tp
Temperature
Ramp-up
TL
tL
Ts max
Ts min
Ramp-down
ts
Preheat
25
t 25oC to Peak
Time
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/ -5°
Profile Feature
Sn-Pb Solder
Pb-Free Solder
Average ramp-up rate (TL to TP)
3°/sec max
3° /sec max
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
100°
150°
60-120 sec
150°
200°
60-180 sec
Tsmax to TL
- Ramp-up Rate
15
3° /sec max
Time maintained above:
- Temperature (TL)
- Time (TL)
183°
60-150 sec
217°
60-150 sec
Peak temperature (Tp)
240 +0/-5°
260 +0/-5°
Time within 5° of actual Peak Temperature (tp)
10-30 sec
20-40 sec
Ramp-down Rate
6° /sec max
6° /sec max
Time 25° to Peak Temperature
6 min max.
8 min max.
Storage Condition
Baking of Populated Boards
Packages described in this document must be stored
in sealed moisture barrier, antistatic bags. Shelf life in a
sealed moisture barrier bag is 12 months at <40° and 90%
relative humidity (RH) J-STD-033 p.7.
Some SMD packages and board materials are not able to
withstand long duration bakes at 125°. Examples of this
are some FR-4 materials, which cannot withstand a 24
hr bake at 125°. Batteries and electrolytic capacitors are
also temperature sensitive. With component and board
temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be
removed. For additional considerations see IPC-7711 andIPC-7721.
Out-of-Bag Time Duration
After unpacking the device must be soldered to the PCB
within 168 hours as listed in the J-STD-020B p.11 with factory conditions <30° and 60% RH.
Baking
It is not necessary to re-bake the part if both conditions
(storage conditions and out-of bag conditions) have been
satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125° for 12 hours J-STD-033 p.8.
CAUTION
Tape and reel materials typically cannot be baked at the
temperature described above. If out-of-bag exposure
time is exceeded, parts must be baked for a longer time
at low temperatures, or the parts must be de-reeled, detaped, re-baked and then put back on tape and reel. (See
moisture sensitive warning label on each shipping bag for
information of baking).
Board Rework
Component Removal, Rework and Remount
If a component is to be removed from the board, it is
recommended that localized heating be used and the
maximum body temperatures of any surface mount component on the board not exceed 200°. This method will
minimize moisture related component damage. If any
component temperature exceeds 200°, the board must
be baked dry per 4-2 prior to rework and/or component
removal. Component temperatures shall be measured at
the top center of the package body. Any SMD packages
that have not exceeded their floor life can be exposed to
a maximum body temperature as high as their specified
maximum reflow temperature.
Removal for Failure Analysis
Not following the above requirements may cause moisture/reflow damage that could hinder or completely prevent the determination of the original failure mechanism.
16
Derating due to Factory Environmental Conditions
Factory floor life exposures for SMD packages removed
from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling
approach is to expose the SMD packages only up to the
maximum time limits for each moisture sensitivity level
as shown in next table. This approach, however, does not
work if the factory humidity or temperature is greater
than the testing conditions of 30°/60% RH. A solution for
addressing this problem is to derate the exposure times
based on the knowledge of moisture diffusion in the
component package materials ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based
on the nominal plastic thickness for each device.
Table on next page lists equivalent derated floor lives for
humidities ranging from 20-90% RH for three temperature, 20°, 25°, and 30°.
Table on next page is applicable to SMDs molded with
novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating this table:
1. Activation Energy for diffusion = 0.35eV (smallest
known value).
2. For ≤60% RH, use Diffusivity = 0.121exp ( -0.35eV/kT)
mm2/s (this used smallest known Diffusivity @ 30°).
3. For >60% RH, use Diffusivity = 1.320exp ( -0.35eV/kT)
mm2/s (this used largest known Diffusivity @ 30°).
Recommended Equivalent Total Floor Life (days) @ 20°, 25° & 30°, 35°
For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified)
Maximum Percent Relative Humidity
Maximum Percent Relative Humidity
Package Type and
Moisture
Body Thickness
Sensitivity Level
5%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Body Thickness ≥3.1 mm
Including
PQFPs >84 pin,
PLCCs (square)
All MQFPs
or
All BGAs ≥1 mm
Level 2a
Level 3
Level 4
Level 5
Level 5a
Body 2.1 mm
≤ Thickness
<3.1 mm including
PLCCs (rectangular)
18-32 pin
SOICs (wide body)
SOICs ≥20 pins,
PQFPs ≤80 pins
Level 2a
Level 3
Level 4
Level 5
Level 5a
Body Thickness <2.1 mm
including
SOICs <18 pin
All TQFPs, TSOPs
or
All BGAs <1 mm body
thickness
Level 2a
Level 3
Level 4
Level 5
Level 5a
17
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5
7
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11
3
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1
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2
3
∞
∞
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7
10
13
18
94
124
167
231
8
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3
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1
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∞
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12
19
25
32
4
5
7
9
2
3
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5
1
1
2
2
∞
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∞
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∞
7
13
18
26
2
3
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60
78
103
7
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4
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9
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∞
7
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6
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4
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35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
35°
30°
25°
20°
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-1907EN - May 8, 2009