ACPM-5007 LTE Band7 (2500-2570 MHz) 3 x 3 mm Power Amplifier Module Data Sheet Description Features The ACPM-5007 is a fully matched 10-pin surface mount module developed for LTE Band7. This power amplifier module operates in the 2500-2570 MHz bandwidth. The ACPM-5007 meets stringent UMTS (Rel 99) linearity requirements up to 28.5 dBm output power and the LTE (MPR = 0 dB) to 27.5 dBm. The 3 x 3 mm form factor package is self contained, incorporating 50 ohm input and output matching networks. Thin Package (0.9 mm typ) The ACPM-5007 features 5th generation of CoolPAM circuit technology which supports 3 power modes – bypass, mid and high power modes. The CoolPAM is stage bypass technology enhancing PAE (power added efficiency) at low and medium power range. Active bypass feature is added to 5th generation to enhance PAE further at low output range. This helps to extend talk time. A directional coupler is integrated into the module and both coupling and isolation ports are available externally, supporting daisy chain. A directional coupler is integrated into the module and both coupling and isolation ports are available externally, supporting daisy chain. The integrated coupler has excellent coupler directivity, which minimizes the coupled output power variation or delivered power variation caused by the load mismatch from the antenna. The coupler directivity, or the output power variation into the mismatched load, is critical to the TRP and SAR performance of the mobile phones in real field operations as well as compliance tests for the system specifications. The ACPM-5007 has integrated on-chip Vref and on-module bias switch as the one of the key features of the CoolPAM-5, so an external constant voltage source is not required, eliminating the external LDO regulators and switches from circuit boards of mobile devices. It also makes the PA fully digital-controllable by the Ven pin that simply turns the PA on and off from the digital control logic input from baseband chipsets. All of the digital Excellent Linearity 3-mode power control with Vbp and Vmode Bypass/Mid Power Mode/High Power Mode High Efficiency at max output power 10-pin surface mounting package Internal 50 ohm matching networks for both RF input and output Integrated coupler Coupler and Isolation ports for daisy chain Green – Lead-free and RoHS complian Applications UMTS & LTE Band7 Handset, Data card Ordering Information Part Number Number of Devices Container ACPM-5007-TR1 1000 178 mm (7”) Tape/Reel ACPM-5007-BLK 100 Bulk Description (Cont.) control input pins such as the Ven, Vmode and Vbp are fully CMOS compatible and can operate down to the 1.35 V logic. The current consumption by digital control pins is negligible. The power amplifier is manufactured on an advanced InGaP HBT (hetero-junction Bipolar Transistor) MMIC (microwave monolithic integrated circuit) technology offering state-of-the-art reliability, temperature stability and ruggedness. Absolute Maximum Ratings No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage. Description Min. RF Input Power (Pin) Typ. Max. Unit 0 10.0 dBm DC Supply Voltage (Vcc1, Vcc2) 0 3.4 5.0 V Enable Voltage (Ven) 0 2.6 3.3 V Mode Control Voltage (Vmode) 0 2.6 3.3 V Bypass Control (Vbp) 0 2.6 3.3 V Storage Temperature (Tstg) -55 25 +125 °C Recommended Operating Condition Description Min. Typ. Max. Unit DC Supply Voltage (Vcc1, Vcc2) 3.2 3.4 4.2 V Enable Voltage (Ven) Low High 0 1.35 0 2.6 0.5 3.1 V V Mode Control Voltage (Vmode) Low High 0 1.35 0 2.6 0.5 3.1 V V Bypass Control Voltage (Vbp) Low High 0 1.35 0 2.6 0.5 3.1 V V 2570 MHz 90 °C Operating Frequency (fo) 2500 Ambient Temperature (Ta) -20 25 Operating Logic Table Power Mode Ven Vmode Vbp Pout (Rel99) Pout (LTE MPR = 0 dB) High Power Mode High Low Low ~ 28.5 dBm ~ 27.5 dBm Mid Power Mode High High Low ~ 17 dBm ~ 16 dBm Bypass Mode High High High ~ 7 dBm ~ 6 dBm Shut Down Mode Low Low Low – – 2 Electrical Characteristics – Conditions: Vcc = 3.4 V, Ven = 2.6 V, Ta = 25° C, Zin/Zout = 50 ohm Characteristics Condition Min. Typ. Max. Unit Operating Frequency Range Maximum Output Power (High Power Mode) WCDMA Rel99 LTE MPR = 0 dB High Power Mode, Pout = 27.5 dBm Mid Power Mode, Pout = 16 dBm Bypass Mode, Pout = 6 dBm High Power Mode, Pout = 28.5 dBm, Rel99 High Power Mode, Pout = 27.5 dBm, LTE MPR = 0 dB Mid Power Mode, Pout = 16 dBm, LTE MPR = 0 dB Bypass Mode, Pout = 6 dBm, LTE MPR = 0 dB High Power Mode, Pout = 28.5 dBm, Rel99 High Power Mode, Pout = 27.5 dBm, LTE MPR = 0 dB Mid Power Mode, Pout = 16 dBm, LTE MPR = 0 dB Bypass Mode, Pout = 6 dBm, LTE MPR = 0 dB High Power Mode Mid Power Mode Bypass Mode High Power Mode Mid Power Mode Bypass Mode Mid Power Mode Bypass Mode Bypass Ven = 0 V, Vmode = 0 V, Vbp = 0 V Pout < (maximum power –MPR) Pout < (maximum power –MPR) Pout < (maximum power –MPR) High Power Mode, Pout = 28.5 dBm 2500 28.5 27.5 25 17 8 – 33.0 – 2570 MHz dBm dBm dB dB dB % 14.5 19.4 5.9 8.2 500 450 – 500 60 80 mA 13 105 18 4 3.7 3.8 3.8 3.7 3.9 3.8 3.5 -37 -39 -60 20 150 30 6 100 100 100 100 100 100 10 -33 -36 -39 -35 -42 mA mA mA mA A A A A A A A dBc dBc dBc dBc dBc dB dB Gain (LTE MPR = 0 dB) Power Added Efficiency Total Supply Current Quiescent Current Enable Current Mode Control Current Bypass Control Current Total Current in Power-down mode LTE E-UTRAACLR Adjacent Channel UTRAACLR1 Leakage Ratio UTRAACLR2 Harmonics 2 fo 3 fo and higher Harmonic Gain 2 fo 3 fo and higher Input VSWR Stability (Spurious Output) Rx band Noise Power Rx band gain GPS Band Noise Power (1574-1577 MHz, Vcc = 4.2 V) GPS band gain ISM band Noise Power ISM band gain Media band gain (716-728 MHz) Phase Discontinuity Ruggedness Coupling factor Daisy Chain Insertion Loss 3 28 21 10.5 41.6 36.7 Where G is gain in TX band G-40 VSWR 5:1, All phase High Power Mode, Pout = 28.5 dBm Where G is gain in Tx band High Power Mode, Pout = 28.5 dBm 2:1 -70 -136 G-2 -140 Where G is gain in Tx band 2400 ~ 2420 MHz 2420 ~ 2440 MHz 2440 ~ 2460 MHz 2460 ~ 2480 MHz Where G is gain in Tx band Where G is gain in Tx band low power modemid power mode, at Pout = 7 dBm mid power modehigh power mode, at Pout = 17 dBm Pout < 28.5 dBm, Pin < 10 dBm, All phase High Power Mode RF Out to CPL port ISO port to CPL port, 698 ~ 2620 MHz, Ven = Low G-11 % % mA dBc dBm/Hz dB dBm/Hz G-0.25 G-25 12 dB dBm/Hz dBm/Hz dBm/Hz dBm/Hz dB dB deg 10 deg -115 -106 -98 -85 10:1 VSWR 20 0.25 dB dB Footprint and Pin Description 1.50 0.10 0.125 Pin 1 VCC1 1 10 VCC2 RFIN 2 9 RFOUT Vpp 3 8 ISO VMODE 4 7 GND VEN 5 6 CPL 0.60 0.35 0.35 0.25 0.10 0.3 X-RAY TOP VIEW All dimensions are in millimeter Pin # Name Description Pin # Name Description 1 Vcc1 DC Supply Voltage 6 CPL Coupling port of Coupler 2 RFin RF Input 7 GND Ground 3 Vbp Bypass Control 8 ISO Isolation port of Coupler 4 Vmode Mode Control 9 RFOut RF Out 5 Ven PA Enable 10 Vcc2 DC Supply Voltage 4 Package Dimensions Pin 1 Mark 0.5 1 10 2 9 3 8 4 7 5 6 3 ± 0.1 3 ± 0.1 0.9 ± 0.1 All dimensions are in millimeter Marking Specification Pin 1 Mark A5007 Manufacturing Part Number PYYWW Lot Number P Manufacturing Info YY Manufacturing Year WW Work Week AAAAA Assemby Lot Number AAAAA Note: Prior to production release, the marking will be ‘E5007’. After the completion of Avago qualification testing and production release, the marking will revert to ‘A5007’. 5 PCB Design Guidelines Metallization The recommended PCB land pattern is shown in figures on the left side. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. on 0.5 mm pitch Ø 0.3 mm 0.45 0.30 0.60 Stencil Design Guidelines A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. 0.35 0.475 connected to a inner layer through a via hole for a better isolation between CPL_IN(ISO) and RFout 0.55 Solder Mask Opening 0.65 0.50 0.45 1.30 0.60 0.525 1.50 Solder Paste Stencil Aperture 0.55 0.45 0.35 1.10 0.60 0.475 1.10 6 The recommended stencil layout is shown here. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100 mm(4 mils) or 0.127 mm(5 mils) thick stainless steel which is capable of producing the required fine stencil outline. Evaluation Board Schematic Vcc1 Vcc2 1 Vcc1 RF In C5 2.2 μF Vcc2 10 C4 1000 pF C6 33 pF RF Out 9 2 RF In Isolation Vbp 3 Vbp Vmode C3 100 pF Ven C2 100 pF C1 100 pF ISO 8 4 Vmode GND 7 5 Ven CPL 6 50 ohm Coupler Evaluation Board Description C5 C7 C4 C6 A5007 PYYWW AAAAA C3 C2 7 C7 2.2 μF RF Out C1 Tape and Reel Information A5007 PYYWW AAAAA Dimension List Annote Millimeter Annote Millimeter A0 3.40±0.10 P2 2.00±0.05 B0 3.40±0.10 P10 40.00±0.20 K0 1.35±0.10 E 1.75±0.10 D0 1.55±0.05 F 5.50±0.05 D1 1.60±0.10 W 12.00±0.30 P0 4.00±0.10 T 0.30±0.05 P1 8.00±0.10 Tape and Reel Format – 3 mm x 3 mm 8 Reel Drawing BACK VIEW Shading indicates thru slots 18.4 max. 178 +0.4 -0.2 50 min. 25 min wide (ref) Slot for carrier tape insertion for attachment to reel hub (2 places 180° apart) 12.4 +2.0 -0.0 FRONT VIEW 1.5 min. 13.0 ± 0.2 21.0 ± 0.8 Plastic Reel Format (all dimensions are in millimeters) 9 NOTES: 1. Reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. Avago Technologies part number c. purchase order number d. date code e. quantity of units 2. A certificate of compliance (c of c) shall be issued and accompany each shipment of product. 3. Reel must not be made with or contain ozone depleting materials. 4. All dimensions in millimeters (mm) Handling and Storage ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. After soak, the components are subjected to three consecutive simulated reflows. The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033. ACPM-5007 is MSL3. Thus, according to the J-STD-033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classification reflow temperature for the ACPM-5007 is targeted at 260° C +0/-5° C. Figure and table on next page show typical SMT profile for maximum temperature of 260 +0/-5° C. Moisture Classification Level and Floor Life MSL Level Floor Life (out of bag) at factory ambient = < 30° C/60% RH or as stated 1 Unlimited at = < 30° C/85% RH 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label Note: 1. The MSL Level is marked on the MSL Label on each shipping bag. 10 Reflow Profile Recommendations tp Tp Critical Zone TL to Tp Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25° C to Peak Time Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5° C Profile Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3° C/sec max 3° C/sec max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 100° C 150° C 60-120 sec 150° C 200° C 60-180 sec Tsmax to TL – Ramp-up Rate 11 3° C/sec max Time maintained above: – Temperature (TL) – Time (TL) 183° C 60-150 sec 217° C 60-150 sec Peak temperature (TP) 240 +0/-5° C 260 +0/-5° C Time within 5° C of actual Peak Temperature (TP) 10-30 sec 20-40 sec Ramp-down Rate 6° C/sec max 6° C/sec max Time 25° C to Peak Temperature 6 min max. 8 min max. Storage Condition Removal for Failure Analysis Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at <40° C and 90% relative humidity (RH) J-STD-033 p.7. Not following the above requirements may cause moisture/ reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions <30° C and 60% RH. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125° C for 12 hours J-STD-033 p.8. CAUTION Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200° C. This method will minimize moisture related component damage. If any component temperature exceeds 200° C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. Some SMD packages and board materials are not able to withstand long duration bakes at 125° C. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125° C. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 andIPC-7721. Derating due to Factory Environmental Conditions Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30°C/60% RH. A solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table on next page lists equivalent derated floor lives for humidities ranging from 20-90% RH for three temperature, 20° C, 25° C, and 30° C. Table on next page is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating this table: 1. Activation Energy for diffusion = 0.35eV (smallest known value). 2. For ≤60% RH, use Diffusivity = 0.121exp (-0.35eV/kT) mm2/s (this used smallest known Diffusivity @ 30° C). 3. For >60% RH, use Diffusivity = 1.320exp (-0.35eV/kT) mm2/s (this used largest known Diffusivity @ 30° C). 12 Recommended Equivalent Total Floor Life (days) @ 20° C, 25° C & 30° C, 35° C For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity Maximum Percent Relative Humidity Package Type and Body Thickness Body Thickness ≥3.1 mm Including PQFPs >84 pin, PLCCs (square) All MQFPs or All BGAs ≥1 mm Moisture Sensitivity Level Level 2a Level 3 Level 4 Level 5 Level 5a Body 2.1 mm ≤ Thickness <3.1 mm including PLCCs (rectangular) 18-32 pin SOICs (wide body) SOICs ≥20 pins, PQFPs ≤80 pins Level 2a Level 3 Level 4 Level 5 Level 5a Body Thickness <2.1 mm including SOICs <18 pin All TQFPs, TSOPs or All BGAs <1 mm body thickness Level 2a Level 3 Level 4 Level 5 Level 5a 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 3 5 6 8 2 4 5 7 1 2 3 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 5 7 9 11 3 4 5 6 1 2 2 3 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 10 13 18 94 124 167 231 8 10 13 17 3 4 5 7 2 3 5 7 1 1 2 4 ∞ ∞ ∞ ∞ 12 19 25 32 4 5 7 9 2 3 4 5 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 13 18 26 2 3 5 6 44 60 78 103 7 9 11 14 3 4 5 7 2 3 4 6 1 1 2 3 ∞ ∞ ∞ ∞ 9 12 15 19 3 4 5 7 2 3 3 5 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 9 12 17 3 5 6 8 1 2 3 4 32 41 53 69 6 8 10 13 2 4 5 7 2 2 4 5 1 1 2 3 58 86 148 ∞ 7 9 12 15 3 4 5 6 2 2 3 4 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 4 5 7 9 2 3 4 6 1 1 2 3 26 33 42 57 6 7 9 12 2 3 5 7 1 2 3 5 1 1 2 3 30 39 51 69 6 8 10 13 2 3 4 6 2 2 3 4 1 1 2 2 ∞ ∞ ∞ ∞ 8 11 14 20 3 4 5 7 2 2 3 5 1 1 2 2 16 28 36 47 6 7 9 12 2 3 4 6 1 2 3 4 1 1 2 2 22 28 37 49 5 7 9 12 2 3 4 5 1 2 3 4 1 1 2 2 17 28 ∞ ∞ 5 7 10 13 2 3 4 6 1 2 3 4 1 1 2 2 7 10 14 19 4 5 7 10 2 3 3 5 1 2 2 3 1 1 1 2 3 4 6 8 2 3 5 7 1 2 3 4 1 1 2 3 1 1 1 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2 5 7 10 13 3 4 6 8 1 2 3 4 1 1 2 3 1 1 1 2 2 3 4 5 2 2 3 5 1 2 2 3 1 1 1 3 0.5 0.5 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 4 6 8 10 3 4 5 7 1 2 3 4 1 1 2 3 1 1 1 2 1 2 3 4 1 2 3 4 1 1 2 3 1 1 1 2 0.5 0.5 1 1 0.5 1 1 1 0.5 1 1 1 0.5 1 1 1 0.5 1 1 1 0.5 0.5 1 1 For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-2977EN - May 23, 2011 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C 35° C 30° C 25° C 20° C