AVAGO ACPM-7822-BLK

ACPM-7822
JCDMA 4x4 Power Amplifier Module
(898-925MHz)
Data Sheet
Description
Features
The ACPM-7822 is a fully matched 10-pin surface mount
module developed for JCDMA. This power amplifier
module operates in the 898-925MHz bandwidth. The
ACPM-7822 meets stringent CDMA linearity requirements
up to 28dBm output power. The 4mmx4mm form factor
package is self contained, incorporating 50ohm input and
output matching networks
• Thin Package (0.9mm typ)
The ACPM-7822 features 5th generation of CoolPAM circuit
• Internal 50ohm matching networks for both RF input
and output
technology which supports 3 power modes – bypass, mid
and high power modes. The CoolPAM is stage bypass technology enhancing PAE (power added efficiency) at low
and medium power range. Active bypass feature is added
to 5th generation to enhance PAE further at low output
range. This helps to extend talk time.
The power amplifier is manufactured on an advanced
InGaP HBT (hetero-junction Bipolar Transistor) MMIC
(microwave monolithic integrated circuit) technology
offering state-of-the-art reliability, temperature stability
and ruggedness.
Component Image
• Excellent Linearity
• 3-mode power control with Vbp and Vmode
Bypass / Mid Power Mode / High Power Mode
• High Efficiency at max output power
• 10-pin surface mounting package
• Lead-free, RoHS compliant, Green
Applications
• Digital Japan CDMA Band (3GPP2 Band Class 3)
Ordering Information
Part Number
Number of
Devices
Container
ACPM-7822-TR1
1000
178mm (7”) Tape/Reel
ACPM-7822-BLK
100
Bulk
Absolute Maximum Ratings
No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal
value.
Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal
values may result in permanent damage.
Description
Min.
RF Input Power (Pin)
Typ.
Max.
Unit
0
10.0
dBm
DC Supply Voltage (Vcc1, Vcc2)
0
3.4
5.0
V
Enable Voltage (Ven)
0
2.6
3.3
V
Mode Control Voltage (Vmode)
0
2.6
3.3
V
Bypass Control (Vbp)
0
2.6
3.3
V
Storage Temperature (Tstg)
-55
25
+125
°C
Description
Min.
Typ.
Max.
Unit
DC Supply Voltage (Vcc1, Vcc2)
3.2
3.4
4.2
V
Low
High
0
1.35
0
2.6
0.5
2.9
V
V
Low
High
0
1.35
0
2.6
0.5
2.9
V
V
Low
High
0
1.35
0
2.6
0.5
2.9
V
V
925
MHz
85
°C
Recommended Operating Condition
Enable Voltage (Ven)
Mode Control Voltage (Vmode)
Bypass Control Voltage (Vbp)
Operating Frequency (fo)
898
Ambient Temperature (Ta)
-30
25
Operating Logic Table
Power Mode
Ven
Vbp
Vmode
Pout
High Power Mode
High
High
Low
~ 28 dBm
Mid Power Mode
High
High
High
~ 18 dBm
Bypass Mode
High
Low
X
~ 11 dBm
Shut Down Mode
Low
Low
Low
–
2
Electrical Characteristics
Conditions: Vcc=3.4V, Ven=2.6V, T=25°C, Zin/Zout=50ohm, IS-95 RL, unless otherwise specified.
Characteristics
Condition
Min.
Typ.
Max.
Unit
898
–
925
MHz
High Power Mode, Pout=28dBm
23
28
dB
Mid Power Mode, Pout=18dBm
13
19
dB
Bypass Mode, Pout=11dBm
8
11.5
dB
High Power Mode, Pout=28dBm
35.3
37.7
%
Mid Power Mode, Pout=18dBm
15.3
22.3
%
Bypass Mode, Pout=11dBm
8.0
11.9
%
Operating Frequency Range
Gain
Power Added Efficiency
Total Supply Current
High Power Mode, Pout=28dBm
492
525
mA
Mid Power Mode, Pout=18dBm
82
120
mA
Bypass Mode, Pout=11dBm
29
43
mA
High Power Mode
93
120
mA
Mid Power Mode
23
30
mA
Bypass Mode
3
5
mA
Enable Current
100
µA
Mode Control Current
100
µA
Bypass Control Current
100
µA
Quiescent Current
Total Current in Power-down mode
Ven=0V, Vmode=0V, Vbp=0V
0.2
5
µA
Adjacent Channel
Power Ratio
900 kHz offset
1.98 MHz offset
High Power Mode, Pout=28dBm
-50
-57
-45
-53
dBc
dBc
900 kHz offset
1.98 MHz offset
Mid Power Mode, Pout=18dBm
-51
-64
-46
-54
dBc
dBc
900 kHz offset
1.98 MHz offset
Bypass Mode, Pout=11dBm
-59
-69
-46
-54
dBc
dBc
Second
Third
High Power Mode, Pout=28dBm
-30
-40
dBc
dBc
Harmonic Suppression
Input VSWR
High Power Mode
Stability (Spurious Output)
In-Band Load VSWR <= 5:1, All Phase
Forwarded Power Fixed,
All Power Modes, with Input Filter
Noise Power in Rx Band (843-870 MHz)
High Power Mode, Pout=28dBm
Noise Power in GPS Band (1575.42 MHz)
High Power Mode, Pout=28dBm
Ruggedness
No Damage
Pout<28dBm & Pin<10dBm,
All phase
High Power Mode
3
2:1
2.5:1
-60
dBc
-135
-132
dBm/Hz
-145
-141
dBm/Hz
10:1
VSWR
Characteristics Data
(Vcc=3.4V, Ven=2.6, Vbp, Vmode= 0V or 2.6V, T=25°C, Zin/Zout=50ohm, IS-95 RL)
30
500
898MHz
915MHz
925MHz
25
300
Gain (dB)
Current (mA)
400
200
0
0
5
10
15
Pout (dBm)
20
25
10
15
Pout (dBm)
20
25
30
10
15
Pout (dBm)
20
25
30
898MHz
915MHz
925MHz
-55
ACPR2 (dBc)
-45
ACPR1 (dBc)
5
-50
898MHz
915MHz
925MHz
-40
-50
-55
-60
-60
-65
-70
-75
-65
0
5
10
15
Pout (dBm)
20
25
30
Adjacent Channel Power Ratio 1 vs. Output Power
898MHz
915MHz
925MHz
35
30
25
20
15
10
5
0
5
10
15
Pout (dBm)
Power Added Efficiency vs. Output Power
-80
0
5
Adjacent Channel Power Ratio 2 vs. Output Power
40
PAE (%)
0
Gain vs. Output Power
-35
4
15
5
30
Total Current vs. Output Power
0
20
10
100
-70
898MHz
915MHz
925MHz
20
25
30
Footprint
All dimensions are in millimeter
1.20
PIN Description
1.90
0.85
1.90 1.70
0.40
0.40
Pin #
Name
Description
1
Ven
PA Enable
2
Vmode
Mode Control
3
Vbp
Bypass Control
4
RFin
RF Input
5
Vcc1
DC Supply Voltage
6
Vcc2
DC Supply Voltage
7
GND
Ground
8
RFout
RF Output
9
GND
Ground
10
GND
Ground
X-RAY TOP VIEW
Package Dimensions
All dimensions are in millimeter
0.6
Pin 1 Mark
1
10
2
9
3
8
4
7
5
6
4 ± 0.1
4 ± 0.1
0.9 ± 0.1
Marking Specification
Pin 1 Mark
AVAGO
ACPM-7822
PYYWW
AAAAA
5
Manufacturing Part Number
Lot Number
P
Manufacturing info
YY
Manufacturing Year
WW
Work Week
AAAAA
Assembly Lot Number
Metallization
0.6
PCB Design Guidelines
The recommended PCB land pattern is shown in figures
on the left side. The substrate is coated with solder mask
between the I/O and conductive paddle to protect the
gold pads from short circuit that is caused by solder
bleeding/bridging.
0.1
0.4
Stencil Design Guidelines
A properly designed solder screen or stencil is required
to ensure optimum amount of solder paste is deposited
onto the PCB pads.
0.85
0.25
The recommended stencil layout is shown here. Reducing
the stencil opening can potentially generate more voids.
On the other hand, stencil openings larger than 100% will
lead to excessive solder paste smear or bridging across
the I/O pads or conductive paddle to adjacent I/O pads.
Considering the fact that solder paste thickness will
directly affect the quality of the solder joint, a good choice
is to use laser cut stencil composed of 0.100mm(4mils) or
0.127mm(5mils) thick stainless steel which is capable of
producing the required fine stencil outline.
0.5
Ø 0.3mm
on 0.6mm pitch
Solder Mask Opening
0.7
0.55
0.5
1.8
0.85
2.4
Solder Paste Stencil Aperture
0.6
0.5
0.4
1.6
0.85
2.0
6
Evaluation Board Schematic
Ven
Vbp
C1
100pF
C2
100pF
RFin
C3
100pF
Vmode
Vcc1
C5
2.2uF
C4
680pF
Evaluation Board Description
7
1 Ven
GND 10
2 Vmode
GND 9
3 Vbp
RFout 8
4 RFin
GND 7
5 Vcc1
Vcc2 6
RFout
Vcc2
C6
680pF
C7
2.2uF
Tape and Reel Information
ACPM-7822
PYYWW
AAAAA
Dimension List
Millimeter
Dimension
Millimeter
A0
4.40±0.10
P2
2.00±0.05
B0
4.40±0.10
P10
40.00±0.20
K0
1.70±0.10
E
1.75±0.10
D0
1.55±0.05
F
5.50±0.05
D1
1.60±0.10
W
12.00±0.30
P0
4.00±0.10
T
0.30±0.05
P1
8.00±0.10
Dimension
8
Reel Drawing
BACK VIEW
Shading indicates
thru slots
18.4 max.
178 +0.4
-0.2
50 min.
25
min wide (ref)
Slot for carrier tape
insertion for attachment
to reel hub (2 places 180° apart)
12.4 +2.0
-0.0
FRONT VIEW
1.5 min.
13.0 ± 0.2
21.0 ± 0.8
Plastic Reel Format (all dimensions are in millimeters)
9
NOTES:
1. Reel shall be labeled with the following
information (as a minimum).
a. manufacturers name or symbol
b. Avago Technologies part number
c. purchase order number
d. date code
e. quantity of units
2. A certificate of compliance (c of c) shall
be issued and accompany each shipment
of product.
3. Reel must not be made with or contain
ozone depleting materials.
4. All dimensions in millimeters (mm)
Handling and Storage
ESD (Electrostatic Discharge)
Electrostatic discharge occurs��������������������������
naturally
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in the environment. With the increase in voltage potential, the outlet of
neutralization or discharge will be sought. If the acquired
discharge route is������������������������������������
through
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a semiconductor device,����
de���
structive damage will result.
ESD countermeasure methods should be developed and
used to control potential ESD damage during handling in
a factory environment at each manufacturing site.
MSL (Moisture Sensitivity Level)
Plastic encapsulated surface mount package is sensitive to
damage induced by absorbed moisture and temperature.
Avago Technologies follows JEDEC Standard J-STD 020B.
Each component and package type is classified for
moisture sensitivity by soaking a known dry package at
various temperatures and relative humidity, and times.
After soak, the components are subjected to three consecutive simulated reflows.
The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level 6 to 1 according to the
JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033.
ACPM-7822 is MSL3. Thus, according to the J-STD-033
p.11 the maximum Manufacturers Exposure Time (MET)
for this part is 168 hours. After this time period, the part
would need to be removed from the reel, de-taped and
then re-baked. MSL classification reflow temperature for
the ACPM-7822 is targeted at 260°C +0/-5°C. Figure and
table on next page show typical SMT profile for maximum
temperature of 260 +0/-5°C.
Moisture Classification Level and Floor Life
MSL Level
Floor Life (out of bag) at factory ambient =< 30°C/60% RH or as stated
1
Unlimited at =< 30°C/85% RH
2
1 year
2a
4 weeks
3
168 hours
4
72 hours
5
48 hours
5a
24 hours
6
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
Note :
1. The MSL Level is marked on the MSL Label on each shipping bag.
10
Reflow Profile Recommendations
tp
Tp
Critical Zone
TL to Tp
Ramp-up
Temperature
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25°C to Peak
Time
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/ -5°C
Profile Feature
Sn-Pb Solder
Pb-Free Solder
Average ramp-up rate (TL to TP)
3°C/sec max
3°C/sec max
100°C
150°C
60-120 sec
150°C
200°C
60-180 sec
Preheat
– Temperature Min (Tsmin)
– Temperature Max (Tsmax)
– Time (min to max) (ts)
Tsmax to TL
– Ramp-up Rate
Time maintained above:
– Temperature (TL)
– Time (TL)
183°C
60-150 sec
217°C
60-150 sec
Peak temperature (Tp)
240 +0/-5°C
260 +0/-5°C
10-30 sec
20-40 sec
Ramp-down Rate
6°C/sec max
6°C/sec max
Time 25°C to Peak Temperature
6 min max.
8 min max.
Time within 5°C of actual Peak Temperature (tp)
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C
11
3°C/sec max
Storage Condition
Baking of Populated Boards
Packages described in this document must be stored
in sealed moisture barrier, antistatic bags. Shelf life in a
sealed moisture barrier bag is 12 months at <40°C and
90% relative humidity (RH) J-STD-033 p.7.
Some SMD packages and board materials are not able to
withstand long duration bakes at 125°C. Examples of this
are some FR-4 materials, which cannot withstand a 24 hr
bake at 125°C. Batteries and electrolytic capacitors are
also temperature sensitive. With component and board
temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the
appropriate bake duration based on the component to
be removed. For additional considerations see IPC-7711
andIPC-7721.
Out-of-Bag Time Duration
After unpacking the device must be soldered to the PCB
within 168 hours as listed in the J-STD-020B p.11 with
factory conditions <30°C and 60% RH.
Baking
It is not necessary to re-bake the part if both conditions
(storage conditions and out-of bag conditions) have been
satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125°C for 12 hours J-STD-033 p.8.
CAUTION
Tape and reel materials typically cannot be baked at the
temperature described above. If out-of-bag exposure
time is exceeded, parts must be baked for a longer time
at low temperatures, or the parts must be de-reeled,
de-taped, re-baked and then put back on tape and reel.
(See moisture sensitive warning label on each shipping
bag for information of baking).
Board Rework
Component Removal, Rework and Remount
If a component is to be removed from the board, it is
recommended that localized heating be used and the
maximum body temperatures of any surface mount
component on the board not exceed 200°C. This method
will minimize moisture related component damage. If any
component temperature exceeds 200°C, the board must
be baked dry per 4-2 prior to rework and/or component
removal. Component temperatures shall be measured at
the top center of the package body. Any SMD packages
that have not exceeded their floor life can be exposed to
a maximum body temperature as high as their specified
maximum reflow temperature.
Removal for Failure Analysis
Not following the above requirements may cause moisture/
reflow damage that could hinder or completely prevent
the determination of the original failure mechanism.
12
Derating due to Factory Environmental Conditions
Factory floor life exposures for SMD packages removed
from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling
approach is to expose the SMD packages only up to the
maximum time limits for each moisture sensitivity level
as shown in next table. This approach, however, does not
work if the factory humidity or temperature is greater
than the testing conditions of 30°C/60% RH. A solution
for addressing this problem is to derate the exposure
times based on the knowledge of moisture diffusion in
the component package materials ref. JESD22-A120).
Recommended equivalent total floor life exposures can
be estimated for a range of humidities and temperatures
based on the nominal plastic thickness for each device.
Table on next page lists equivalent derated floor lives for
humidities ranging from 20-90% RH for three temperature, 20°C, 25°C, and 30°C.
Table on next page is applicable to SMDs molded
with novolac, biphenyl or multifunctional epoxy mold
compounds. The following assumptions were used in calculating this table:
1. Activation Energy for diffusion = 0.35eV (smallest
known value).
2. For ≤60% RH, use Diffusivity = 0.121exp ( -0.35eV/kT)
mm2/s (this used smallest known Diffusivity @ 30°C).
3. For >60% RH, use Diffusivity = 1.320exp ( -0.35eV/kT)
mm2/s (this used largest known Diffusivity @ 30°C).
Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C For ICs with Novolac, Biphenyl and
Multifunctional Epoxies (Reflow at same temperature at which the component was classified)
Maximum Percent Relative Humidity
Package Type and
Body Thickness
Moisture Sensitivity Level
5%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Body Thickness ≥3.1 mm
Including PQFPs >84 pin,
PLCCs (square)
All MQFPs
or
All BGAs ≥1 mm
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
∞
60
78
103
41
53
69
33
42
57
28
36
47
10
14
19
7
10
13
6
8
10
30°C
25°C
20°C
Level 3
∞
∞
∞
∞
∞
∞
10
13
17
9
11
14
8
10
13
7
9
12
7
9
12
5
7
10
4
6
8
4
5
7
30°C
25°C
20°C
Level 4
∞
∞
∞
5
6
8
4
5
7
4
5
7
4
5
7
3
5
7
3
4
6
3
3
5
2
3
4
2
3
4
30°C
25°C
20°C
Level 5
∞
∞
∞
4
5
7
3
5
7
3
4
6
2
4
5
2
3
5
2
3
4
2
2
3
1
2
2
1
2
3
30°C
25°C
20°C
Level 5a
∞
∞
∞
2
3
5
1
2
4
1
2
3
1
2
3
1
2
3
1
2
2
1
1
2
1
1
2
1
1
2
30°C
25°C
20°C
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
86
148
∞
39
51
69
28
37
49
4
6
8
3
4
5
2
3
4
30°C
25°C
20°C
Level 3
∞
∞
∞
∞
∞
∞
19
25
32
12
15
19
9
12
15
8
10
13
7
9
12
3
5
7
2
3
5
2
3
4
30°C
25°C
20°C
Level 4
∞
∞
∞
7
9
11
5
7
9
4
5
7
4
5
6
3
4
6
3
4
5
2
3
4
2
2
3
1
2
3
30°C
25°C
20°C
Level 5
∞
∞
∞
4
5
6
3
4
5
3
3
5
2
3
4
2
3
4
2
3
4
1
2
3
1
1
3
1
1
2
30°C
25°C
20°C
Level 5a
∞
∞
∞
2
2
3
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
1
2
0.5
1
2
0.5
1
1
30°C
25°C
20°C
Level 2a
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
28
∞
∞
1
2
2
1
1
2
1
1
1
30°C
25°C
20°C
Level 3
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
11
14
20
7
10
13
1
2
2
1
1
2
1
1
1
30°C
25°C
20°C
Level 4
∞
∞
∞
∞
∞
∞
∞
∞
∞
9
12
17
5
7
9
4
5
7
3
4
6
1
2
2
1
1
2
1
1
1
30°C
25°C
20°C
Level 5
∞
∞
∞
∞
∞
∞
13
18
26
5
6
8
3
4
6
2
3
5
2
3
4
1
2
2
1
1
2
1
1
1
30°C
25°C
20°C
Level 5a
∞
∞
∞
10
13
18
3
5
6
2
3
4
1
2
3
1
2
2
1
2
2
1
1
2
1
1
2
0.5
1
1
30°C
25°C
20°C
Body 2.1 mm ≤ Thickness
<3.1 mm including
PLCCs (rectangular)
18-32 pin
SOICs (wide body)
SOICs ≥20 pins,
PQFPs ≤80 pins
Body Thickness <2.1 mm
including SOICs <18 pin
All TQFPs, TSOPs
or
All BGAs <1 mm body
thickness
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved.
AV02-1777EN - February 17, 2009